1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * written or collected and sometimes rewritten by
13 * Magnus Damm <damm@bitsmart.com>
15 * minor modifications by
16 * Wolfgang Denk <wd@denx.de>
28 #include <asm/cache.h>
29 #include <asm/cpm_8xx.h>
30 #include <linux/compiler.h>
33 #if defined(CONFIG_OF_LIBFDT)
34 #include <linux/libfdt.h>
35 #include <fdt_support.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 /* ------------------------------------------------------------------------- */
45 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
46 memctl8xx_t __iomem *memctl = &immap->im_memctl;
47 u32 cacheon = rd_ic_cst() & IDC_ENABLED;
48 /* probe in flash memoryarea */
49 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
54 wr_ic_cst(IDC_INVALL);
55 wr_ic_cst(IDC_DISABLE);
56 __asm__ volatile ("isync");
58 while (!((m = rd_ic_cst()) & IDC_CERR2)) {
61 __asm__ volatile ("isync");
64 k += 0x10; /* the number of bytes in a cacheline */
68 wr_ic_cst(IDC_INVALL);
71 wr_ic_cst(IDC_ENABLE);
73 wr_ic_cst(IDC_DISABLE);
75 __asm__ volatile ("isync");
80 /* ------------------------------------------------------------------------- */
82 /* call with cache disabled */
84 static int checkdcache(void)
86 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
87 memctl8xx_t __iomem *memctl = &immap->im_memctl;
88 u32 cacheon = rd_dc_cst() & IDC_ENABLED;
89 /* probe in flash memoryarea */
90 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
95 wr_dc_cst(IDC_INVALL);
96 wr_dc_cst(IDC_DISABLE);
98 while (!((m = rd_dc_cst()) & IDC_CERR2)) {
100 wr_dc_cst(IDC_LDLCK);
102 k += 0x10; /* the number of bytes in a cacheline */
105 wr_dc_cst(IDC_UNALL);
106 wr_dc_cst(IDC_INVALL);
109 wr_dc_cst(IDC_ENABLE);
111 wr_dc_cst(IDC_DISABLE);
116 static int check_CPU(long clock, uint pvr, uint immr)
118 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
122 /* the highest 16 bits should be 0x0050 for a 860 */
124 if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
128 in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
131 * Some boards use sockets so different CPUs can be used.
132 * We have to check chip version in run time.
135 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
136 case 0x08010004: /* Rev. A.0 */
137 printf("MPC866xxxZPnnA");
139 case 0x08000003: /* Rev. 0.3 */
140 printf("MPC866xxxZPnn");
142 case 0x09000000: /* 870/875/880/885 */
147 printf("unknown MPC86x (0x%08x)", k);
151 printf(" at %s MHz: ", strmhz(buf, clock));
153 print_size(checkicache(), " I-Cache ");
154 print_size(checkdcache(), " D-Cache");
156 /* do we have a FEC (860T/P or 852/859/866/885)? */
158 out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
159 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
160 printf(" FEC present");
167 /* ------------------------------------------------------------------------- */
171 ulong clock = gd->cpu_clk;
172 uint immr = get_immr(); /* Return full IMMR contents */
173 uint pvr = get_pvr();
177 return check_CPU(clock, pvr, immr);
180 /* ------------------------------------------------------------------------- */
182 void upmconfig(uint upm, uint *table, uint size)
186 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
187 memctl8xx_t __iomem *memctl = &immap->im_memctl;
189 for (i = 0; i < size; i++) {
190 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
191 out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
196 /* ------------------------------------------------------------------------- */
198 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
202 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
204 /* Checkstop Reset enable */
205 setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
207 /* Interrupts and MMU off */
208 __asm__ volatile ("mtspr 81, 0");
209 __asm__ volatile ("mfmsr %0" : "=r" (msr));
212 __asm__ volatile ("mtmsr %0" : : "r" (msr));
215 * Trying to execute the next instruction at a non-existing address
216 * should cause a machine check, resulting in reset
218 #ifdef CONFIG_SYS_RESET_ADDRESS
219 addr = CONFIG_SYS_RESET_ADDRESS;
222 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
223 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
224 * Better pick an address known to be invalid on your system and assign
225 * it to CONFIG_SYS_RESET_ADDRESS.
226 * "(ulong)-1" used to be a good choice for many systems...
228 addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
230 ((void (*)(void)) addr)();
234 /* ------------------------------------------------------------------------- */
237 * Get timebase clock frequency (like cpu_clk in Hz)
239 * See sections 14.2 and 14.6 of the User's Manual
241 unsigned long get_tbclk(void)
243 immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
244 ulong oscclk, factor, pll;
246 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
247 return gd->cpu_clk / 16;
249 pll = in_be32(&immap->im_clkrst.car_plprcr);
251 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
254 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
255 * factor is calculated as follows:
260 * factor = -----------------
264 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
265 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
267 oscclk = gd->cpu_clk / factor;
269 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
277 * Initializes on-chip ethernet controllers.
278 * to override, implement board_eth_init()
280 int cpu_eth_init(bd_t *bis)
282 #if defined(CONFIG_MPC8XX_FEC)