2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
13 #ifdef CONFIG_ADDR_MAP
17 DECLARE_GLOBAL_DATA_PTR;
19 void invalidate_tlb(u8 tlb)
27 __weak void init_tlbs(void)
31 for (i = 0; i < num_tlb_entries; i++) {
32 write_tlb(tlb_table[i].mas0,
42 #if !defined(CONFIG_NAND_SPL) && \
43 (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
44 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
49 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
50 asm volatile("tlbre;isync");
53 *valid = (_mas1 & MAS1_VALID);
54 *tsize = (_mas1 >> 7) & 0x1f;
55 *epn = mfspr(MAS2) & MAS2_EPN;
56 *rpn = mfspr(MAS3) & MAS3_RPN;
57 #ifdef CONFIG_ENABLE_36BIT_PHYS
58 *rpn |= ((u64)mfspr(MAS7)) << 32;
62 void print_tlbcam(void)
65 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
67 /* walk all the entries */
68 printf("TLBCAM entries\n");
69 for (i = 0; i < num_cam; i++) {
74 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
75 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
76 i, (valid == 0) ? 0 : 1, (unsigned int)epn,
77 (unsigned long long)rpn);
78 print_size(TSIZE_TO_BYTES(tsize), "\n");
82 static inline void use_tlb_cam(u8 idx)
87 gd->arch.used_tlb_cams[i] |= (1 << bit);
90 static inline void free_tlb_cam(u8 idx)
95 gd->arch.used_tlb_cams[i] &= ~(1 << bit);
98 void init_used_tlb_cams(void)
101 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
103 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
104 gd->arch.used_tlb_cams[i] = 0;
106 /* walk all the entries */
107 for (i = 0; i < num_cam; i++) {
108 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
109 asm volatile("tlbre;isync");
110 if (mfspr(MAS1) & MAS1_VALID)
115 int find_free_tlbcam(void)
120 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
121 idx = ffz(gd->arch.used_tlb_cams[i]);
129 if (idx >= CONFIG_SYS_NUM_TLBCAMS)
135 void set_tlb(u8 tlb, u32 epn, u64 rpn,
137 u8 ts, u8 esel, u8 tsize, u8 iprot)
139 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
144 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
146 printf("%s: bad tsize %d on entry %d at 0x%08x\n",
147 __func__, tsize, tlb, epn);
151 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
152 _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
153 _mas2 = FSL_BOOKE_MAS2(epn, wimge);
154 _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
155 _mas7 = FSL_BOOKE_MAS7(rpn);
157 write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
159 #ifdef CONFIG_ADDR_MAP
160 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
161 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
165 void disable_tlb(u8 esel)
167 u32 _mas0, _mas1, _mas2, _mas3;
171 _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
180 #ifdef CONFIG_ENABLE_36BIT_PHYS
183 asm volatile("isync;msync;tlbwe;isync");
185 #ifdef CONFIG_ADDR_MAP
186 if (gd->flags & GD_FLG_RELOC)
187 addrmap_set_entry(0, 0, 0, esel);
191 static void tlbsx (const volatile unsigned *addr)
193 __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
196 /* return -1 if we didn't find anything */
197 int find_tlb_idx(void *addr, u8 tlbsel)
201 /* zero out Search PID, AS */
209 /* we found something, and its in the TLB we expect */
210 if ((MAS1_VALID & _mas1) &&
211 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
212 return ((_mas0 & MAS0_ESEL_MSK) >> 16);
218 #ifdef CONFIG_ADDR_MAP
219 void init_addr_map(void)
222 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
224 /* walk all the entries */
225 for (i = 0; i < num_cam; i++) {
230 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
231 if (valid & MAS1_VALID)
232 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
239 uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
240 enum tlb_map_type map_type)
243 unsigned int tlb_size;
246 unsigned int max_cam, tsize_mask;
248 if (map_type == TLB_MAP_RAM) {
249 perm = MAS3_SX|MAS3_SW|MAS3_SR;
251 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
252 wimge = CONFIG_SYS_PPC_DDR_WIMGE;
255 perm = MAS3_SW|MAS3_SR;
256 wimge = MAS2_I|MAS2_G;
259 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
260 /* Convert (4^max) kB to (2^max) bytes */
261 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
264 /* Convert (2^max) kB to (2^max) bytes */
265 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
269 for (i = 0; size && i < 8; i++) {
270 int tlb_index = find_free_tlbcam();
271 u32 camsize = __ilog2_u64(size) & tsize_mask;
272 u32 align = __ilog2(v_addr) & tsize_mask;
277 if (align == -2) align = max_cam;
281 if (camsize > max_cam)
284 tlb_size = camsize - 10;
286 set_tlb(1, v_addr, p_addr, perm, wimge,
287 0, tlb_index, tlb_size, 1);
289 size -= 1ULL << camsize;
290 v_addr += 1UL << camsize;
291 p_addr += 1UL << camsize;
297 unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
298 unsigned int memsize_in_meg)
300 unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
301 u64 memsize = (u64)memsize_in_meg << 20;
303 memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
304 memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
307 print_size(memsize, " left unmapped\n");
309 return memsize_in_meg;
312 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
315 setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
318 /* Invalidate the DDR TLBs for the requested size */
319 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
321 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
323 u32 tsize, valid, ptr;
326 u64 memsize = (u64)memsize_in_meg << 20;
330 while (ptr < (vstart + memsize)) {
331 ddr_esel = find_tlb_idx((void *)ptr, 1);
332 if (ddr_esel != -1) {
333 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
334 disable_tlb(ddr_esel);
336 ptr += TSIZE_TO_BYTES(tsize);
340 void clear_ddr_tlbs(unsigned int memsize_in_meg)
342 clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);