2 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
86 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
87 /* ISBC uses L2 as stack.
88 * Disable L2 cache here so that u-boot can enable it later
89 * as part of it's normal flow
92 /* Check if L2 is enabled */
95 ori r2, r2, L2CSR0_L2E@l
101 lis r2,(L2CSR0_L2FL)@h
102 ori r2, r2, (L2CSR0_L2FL)@l
109 mfspr r3, SPRN_L2CSR0
113 mfspr r3, SPRN_L2CSR0
115 ori r2, r2, L2CSR0_L2E@l
125 /* clear registers/arrays not reset by hardware */
129 mtspr L1CSR0,r0 /* invalidate d-cache */
130 mtspr L1CSR1,r0 /* invalidate i-cache */
133 mtspr DBSR,r1 /* Clear all valid bits */
136 * Enable L1 Caches early
140 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
141 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
146 /* Enable/invalidate the I-Cache */
147 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
148 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
155 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
156 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
161 andi. r1,r3,L1CSR1_ICE@l
164 /* Enable/invalidate the D-Cache */
165 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
166 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
173 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
174 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
179 andi. r1,r3,L1CSR0_DCE@l
182 /* Setup interrupt vectors */
183 lis r1,CONFIG_SYS_MONITOR_BASE@h
187 mtspr IVOR0,r1 /* 0: Critical input */
189 mtspr IVOR1,r1 /* 1: Machine check */
191 mtspr IVOR2,r1 /* 2: Data storage */
193 mtspr IVOR3,r1 /* 3: Instruction storage */
195 mtspr IVOR4,r1 /* 4: External interrupt */
197 mtspr IVOR5,r1 /* 5: Alignment */
199 mtspr IVOR6,r1 /* 6: Program check */
201 mtspr IVOR7,r1 /* 7: floating point unavailable */
203 mtspr IVOR8,r1 /* 8: System call */
204 /* 9: Auxiliary processor unavailable(unsupported) */
206 mtspr IVOR10,r1 /* 10: Decrementer */
208 mtspr IVOR11,r1 /* 11: Interval timer */
210 mtspr IVOR12,r1 /* 12: Watchdog timer */
212 mtspr IVOR13,r1 /* 13: Data TLB error */
214 mtspr IVOR14,r1 /* 14: Instruction TLB error */
216 mtspr IVOR15,r1 /* 15: Debug */
218 /* Clear and set up some registers. */
221 mtspr DEC,r0 /* prevent dec exceptions */
222 mttbl r0 /* prevent fit & wdt exceptions */
224 mtspr TSR,r1 /* clear all timer exception status */
225 mtspr TCR,r0 /* disable all */
226 mtspr ESR,r0 /* clear exception syndrome register */
227 mtspr MCSR,r0 /* machine check syndrome register */
228 mtxer r0 /* clear integer exception register */
230 #ifdef CONFIG_SYS_BOOK3E_HV
231 mtspr MAS8,r0 /* make sure MAS8 is clear */
234 /* Enable Time Base and Select Time Base Clock */
235 lis r0,HID0_EMCP@h /* Enable machine check */
236 #if defined(CONFIG_ENABLE_36BIT_PHYS)
237 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
239 #ifndef CONFIG_E500MC
240 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
244 #ifndef CONFIG_E500MC
245 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
248 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
250 /* Set MBDD bit also */
251 ori r0, r0, HID1_MBDD@l
256 /* Enable Branch Prediction */
257 #if defined(CONFIG_BTB)
258 lis r0,BUCSR_ENABLE@h
259 ori r0,r0,BUCSR_ENABLE@l
263 #if defined(CONFIG_SYS_INIT_DBCR)
266 mtspr DBSR,r1 /* Clear all status bits */
267 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
268 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
272 #ifdef CONFIG_MPC8569
273 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
274 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
276 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
277 * use address space which is more than 12bits, and it must be done in
278 * the 4K boot page. So we set this bit here.
281 /* create a temp mapping TLB0[0] for LBCR */
282 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
283 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
285 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
286 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
288 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
289 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
291 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
292 (MAS3_SX|MAS3_SW|MAS3_SR))@h
293 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
294 (MAS3_SX|MAS3_SW|MAS3_SR))@l
304 /* Set LBCR register */
305 lis r4,CONFIG_SYS_LBCR_ADDR@h
306 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
308 lis r5,CONFIG_SYS_LBC_LBCR@h
309 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
313 /* invalidate this temp TLB */
314 lis r4,CONFIG_SYS_LBC_ADDR@h
315 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
319 #endif /* CONFIG_MPC8569 */
322 * Search for the TLB that covers the code we're executing, and shrink it
323 * so that it covers only this 4K page. That will ensure that any other
324 * TLB we create won't interfere with it. We assume that the TLB exists,
325 * which is why we don't check the Valid bit of MAS1.
327 * This is necessary, for example, when booting from the on-chip ROM,
328 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
329 * If we don't shrink this TLB now, then we'll accidentally delete it
330 * in "purge_old_ccsr_tlb" below.
332 bl nexti /* Find our address */
333 nexti: mflr r1 /* R1 = our PC */
335 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
338 tlbsx 0, r1 /* This must succeed */
340 /* Set the size of the TLB to 4KB */
343 andc r3, r3, r2 /* Clear the TSIZE bits */
344 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
348 * Set the base address of the TLB to our PC. We assume that
349 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
352 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
354 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
359 mtspr MAS2, r2 /* Set the EPN to our PC base address */
364 mtspr MAS3, r2 /* Set the RPN to our PC base address */
371 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
372 * location is not where we want it. This typically happens on a 36-bit
373 * system, where we want to move CCSR to near the top of 36-bit address space.
375 * To move CCSR, we create two temporary TLBs, one for the old location, and
376 * another for the new location. On CoreNet systems, we also need to create
377 * a special, temporary LAW.
379 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
380 * long-term TLBs, so we use TLB0 here.
382 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
384 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
385 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
389 lis r8, CONFIG_SYS_CCSRBAR@h
390 ori r8, r8, CONFIG_SYS_CCSRBAR@l
391 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
392 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
395 * In a multi-stage boot (e.g. NAND boot), a previous stage may have
396 * created a TLB for CCSR, which will interfere with our relocation
397 * code. Since we're going to create a new TLB for CCSR anyway,
398 * it should be safe to delete this old TLB here. We have to search
403 mtspr MAS6, r1 /* Search the current address space and PID */
408 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
409 beq 1f /* Skip if no TLB found */
411 rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
420 * Create a TLB for the new location of CCSR. Register R8 is reserved
421 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
423 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
424 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
425 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
426 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
427 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
428 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
429 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
430 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
431 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
432 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
443 * Create a TLB for the current location of CCSR. Register R9 is reserved
444 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
447 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
448 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
449 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
450 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
451 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
452 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
453 li r7, 0 /* The default CCSR address is always a 32-bit number */
455 /* MAS1 is the same as above */
464 * We have a TLB for what we think is the current (old) CCSR. Let's
465 * verify that, otherwise we won't be able to move it.
466 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
467 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
470 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
471 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
472 #ifdef CONFIG_FSL_CORENET
473 lwz r1, 4(r9) /* CCSRBARL */
475 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
482 * If the value we read from CCSRBARL is not what we expect, then
483 * enter an infinite loop. This will at least allow a debugger to
484 * halt execution and examine TLBs, etc. There's no point in going
488 bne infinite_debug_loop
490 #ifdef CONFIG_FSL_CORENET
492 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
493 #define LAW_EN 0x80000000
494 #define LAW_SIZE_4K 0xb
495 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
496 #define CCSRAR_C 0x80000000 /* Commit */
500 * On CoreNet systems, we create the temporary LAW using a special LAW
501 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
503 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
504 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
505 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
506 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
507 lis r2, CCSRBAR_LAWAR@h
508 ori r2, r2, CCSRBAR_LAWAR@l
510 stw r0, 0xc00(r9) /* LAWBARH0 */
511 stw r1, 0xc04(r9) /* LAWBARL0 */
513 stw r2, 0xc08(r9) /* LAWAR0 */
516 * Read back from LAWAR to ensure the update is complete. e500mc
517 * cores also require an isync.
519 lwz r0, 0xc08(r9) /* LAWAR0 */
523 * Read the current CCSRBARH and CCSRBARL using load word instructions.
524 * Follow this with an isync instruction. This forces any outstanding
525 * accesses to configuration space to completion.
528 lwz r0, 0(r9) /* CCSRBARH */
529 lwz r0, 4(r9) /* CCSRBARL */
533 * Write the new values for CCSRBARH and CCSRBARL to their old
534 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
535 * has a new value written it loads a CCSRBARH shadow register. When
536 * the CCSRBARL is written, the CCSRBARH shadow register contents
537 * along with the CCSRBARL value are loaded into the CCSRBARH and
538 * CCSRBARL registers, respectively. Follow this with a sync
542 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
543 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
544 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
545 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
547 ori r2, r2, CCSRAR_C@l
549 stw r0, 0(r9) /* Write to CCSRBARH */
550 sync /* Make sure we write to CCSRBARH first */
551 stw r1, 4(r9) /* Write to CCSRBARL */
555 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
556 * Follow this with a sync instruction.
561 /* Delete the temporary LAW */
570 #else /* #ifdef CONFIG_FSL_CORENET */
574 * Read the current value of CCSRBAR using a load word instruction
575 * followed by an isync. This forces all accesses to configuration
582 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
583 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
584 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
586 /* Write the new value to CCSRBAR. */
587 lis r0, CCSRBAR_PHYS_RS12@h
588 ori r0, r0, CCSRBAR_PHYS_RS12@l
593 * The manual says to perform a load of an address that does not
594 * access configuration space or the on-chip SRAM using an existing TLB,
595 * but that doesn't appear to be necessary. We will do the isync,
601 * Read the contents of CCSRBAR from its new location, followed by
607 #endif /* #ifdef CONFIG_FSL_CORENET */
609 /* Delete the temporary TLBs */
611 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
612 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
614 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
615 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
623 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
624 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
625 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
626 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
632 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
634 create_init_ram_area:
635 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
636 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
638 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
639 /* create a temp mapping in AS=1 to the 4M boot window */
640 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
641 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
643 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
644 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
646 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
647 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
648 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
649 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
650 /* create a temp mapping in AS = 1 for Flash mapping
651 * created by PBL for ISBC code
653 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
654 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
656 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
657 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
659 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
660 (MAS3_SX|MAS3_SW|MAS3_SR))@h
661 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
662 (MAS3_SX|MAS3_SW|MAS3_SR))@l
665 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
666 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
668 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
669 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
671 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
672 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
674 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
675 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
686 /* create a temp mapping in AS=1 to the stack */
687 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
688 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
690 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
691 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
693 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
694 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
696 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
697 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
698 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
699 (MAS3_SX|MAS3_SW|MAS3_SR))@h
700 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
701 (MAS3_SX|MAS3_SW|MAS3_SR))@l
702 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
705 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
706 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
717 lis r6,MSR_IS|MSR_DS@h
718 ori r6,r6,MSR_IS|MSR_DS@l
720 ori r7,r7,switch_as@l
727 /* L1 DCache is used for initial RAM */
729 /* Allocate Initial RAM in data cache.
731 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
732 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
735 /* cache size * 1024 / (2 * L1 line size) */
736 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
742 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
745 /* Jump out the last 4K page and continue to 'normal' start */
746 #ifdef CONFIG_SYS_RAMBOOT
749 /* Calculate absolute address in FLASH and jump there */
750 /*--------------------------------------------------------------*/
751 lis r3,CONFIG_SYS_MONITOR_BASE@h
752 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
753 addi r3,r3,_start_cont - _start + _START_OFFSET
761 .long 0x27051956 /* U-BOOT Magic Number */
762 .globl version_string
764 .ascii U_BOOT_VERSION_STRING, "\0"
769 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
770 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
771 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
775 stwu r0,-4(r1) /* Terminate call chain */
777 stwu r1,-8(r1) /* Save back chain and move SP */
778 lis r0,RESET_VECTOR@h /* Address of reset vector */
779 ori r0,r0,RESET_VECTOR@l
780 stwu r1,-8(r1) /* Save back chain and move SP */
781 stw r0,+12(r1) /* Save return addr (underflow vect) */
786 /* switch back to AS = 0 */
787 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
788 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
796 /* NOTREACHED - board_init_f() does not return */
798 #ifndef CONFIG_NAND_SPL
799 . = EXC_OFF_SYS_RESET
800 .globl _start_of_vectors
803 /* Critical input. */
804 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
807 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
809 /* Data Storage exception. */
810 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
812 /* Instruction Storage exception. */
813 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
815 /* External Interrupt exception. */
816 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
818 /* Alignment exception. */
821 EXCEPTION_PROLOG(SRR0, SRR1)
826 addi r3,r1,STACK_FRAME_OVERHEAD
827 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
829 /* Program check exception */
832 EXCEPTION_PROLOG(SRR0, SRR1)
833 addi r3,r1,STACK_FRAME_OVERHEAD
834 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
837 /* No FPU on MPC85xx. This exception is not supposed to happen.
839 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
843 * r0 - SYSCALL number
847 addis r11,r0,0 /* get functions table addr */
848 ori r11,r11,0 /* Note: this code is patched in trap_init */
849 addis r12,r0,0 /* get number of functions */
855 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
859 li r20,0xd00-4 /* Get stack pointer */
861 subi r12,r12,12 /* Adjust stack pointer */
862 li r0,0xc00+_end_back-SystemCall
863 cmplw 0,r0,r12 /* Check stack overflow */
874 li r12,0xc00+_back-SystemCall
882 mfmsr r11 /* Disable interrupts */
886 SYNC /* Some chip revs need this... */
890 li r12,0xd00-4 /* restore regs */
900 addi r12,r12,12 /* Adjust stack pointer */
908 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
909 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
910 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
912 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
913 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
915 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
917 .globl _end_of_vectors
921 . = . + (0x100 - ( . & 0xff )) /* align for debug */
924 * This code finishes saving the registers to the exception frame
925 * and jumps to the appropriate handler for the exception.
926 * Register r21 is pointer into trap frame, r1 has new stack pointer.
928 .globl transfer_to_handler
940 andi. r24,r23,0x3f00 /* get vector offset */
944 mtspr SPRG2,r22 /* r1 is now kernel sp */
946 lwz r24,0(r23) /* virtual address of handler */
947 lwz r23,4(r23) /* where to go when done */
952 rfi /* jump to handler, enable MMU */
955 mfmsr r28 /* Disable interrupts */
959 SYNC /* Some chip revs need this... */
974 lwz r2,_NIP(r1) /* Restore environment */
985 mfmsr r28 /* Disable interrupts */
989 SYNC /* Some chip revs need this... */
1004 lwz r2,_NIP(r1) /* Restore environment */
1015 mfmsr r28 /* Disable interrupts */
1019 SYNC /* Some chip revs need this... */
1034 lwz r2,_NIP(r1) /* Restore environment */
1036 mtspr SPRN_MCSRR0,r2
1037 mtspr SPRN_MCSRR1,r0
1048 .globl invalidate_icache
1051 ori r0,r0,L1CSR1_ICFI
1056 blr /* entire I cache */
1058 .globl invalidate_dcache
1061 ori r0,r0,L1CSR0_DCFI
1068 .globl icache_enable
1071 bl invalidate_icache
1081 .globl icache_disable
1085 ori r3,r3,L1CSR1_ICE
1091 .globl icache_status
1094 andi. r3,r3,L1CSR1_ICE
1097 .globl dcache_enable
1100 bl invalidate_dcache
1112 .globl dcache_disable
1116 ori r4,r4,L1CSR0_DCE
1122 .globl dcache_status
1125 andi. r3,r3,L1CSR0_DCE
1148 /*------------------------------------------------------------------------------- */
1150 /* Description: Input 8 bits */
1151 /*------------------------------------------------------------------------------- */
1157 /*------------------------------------------------------------------------------- */
1158 /* Function: out8 */
1159 /* Description: Output 8 bits */
1160 /*------------------------------------------------------------------------------- */
1167 /*------------------------------------------------------------------------------- */
1168 /* Function: out16 */
1169 /* Description: Output 16 bits */
1170 /*------------------------------------------------------------------------------- */
1177 /*------------------------------------------------------------------------------- */
1178 /* Function: out16r */
1179 /* Description: Byte reverse and output 16 bits */
1180 /*------------------------------------------------------------------------------- */
1187 /*------------------------------------------------------------------------------- */
1188 /* Function: out32 */
1189 /* Description: Output 32 bits */
1190 /*------------------------------------------------------------------------------- */
1197 /*------------------------------------------------------------------------------- */
1198 /* Function: out32r */
1199 /* Description: Byte reverse and output 32 bits */
1200 /*------------------------------------------------------------------------------- */
1207 /*------------------------------------------------------------------------------- */
1208 /* Function: in16 */
1209 /* Description: Input 16 bits */
1210 /*------------------------------------------------------------------------------- */
1216 /*------------------------------------------------------------------------------- */
1217 /* Function: in16r */
1218 /* Description: Input 16 bits and byte reverse */
1219 /*------------------------------------------------------------------------------- */
1225 /*------------------------------------------------------------------------------- */
1226 /* Function: in32 */
1227 /* Description: Input 32 bits */
1228 /*------------------------------------------------------------------------------- */
1234 /*------------------------------------------------------------------------------- */
1235 /* Function: in32r */
1236 /* Description: Input 32 bits and byte reverse */
1237 /*------------------------------------------------------------------------------- */
1242 #endif /* !CONFIG_NAND_SPL */
1244 /*------------------------------------------------------------------------------*/
1247 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1255 #ifdef CONFIG_ENABLE_36BIT_PHYS
1259 #ifdef CONFIG_SYS_BOOK3E_HV
1269 * void relocate_code (addr_sp, gd, addr_moni)
1271 * This "function" does not return, instead it continues in RAM
1272 * after relocating the monitor code.
1276 * r5 = length in bytes
1277 * r6 = cachelinesize
1279 .globl relocate_code
1281 mr r1,r3 /* Set new stack pointer */
1282 mr r9,r4 /* Save copy of Init Data pointer */
1283 mr r10,r5 /* Save copy of Destination Address */
1286 mr r3,r5 /* Destination Address */
1287 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1288 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1289 lwz r5,GOT(__init_end)
1291 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1296 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1302 /* First our own GOT */
1304 /* the the one used by the C code */
1314 beq cr1,4f /* In place copy is not necessary */
1315 beq 7f /* Protect against 0 count */
1334 * Now flush the cache: note that we must start from a cache aligned
1335 * address. Otherwise we might miss one cache line.
1339 beq 7f /* Always flush prefetch queue in any case */
1347 sync /* Wait for all dcbst to complete on bus */
1353 7: sync /* Wait for all icbi to complete on bus */
1357 * Re-point the IVPR at RAM
1362 * We are done. Do not return, instead branch to second part of board
1363 * initialization, now running from RAM.
1366 addi r0,r10,in_ram - _start + _START_OFFSET
1368 blr /* NEVER RETURNS! */
1373 * Relocation Function, r12 point to got2+0x8000
1375 * Adjust got2 pointers, no need to check for 0, this code
1376 * already puts a few entries in the table.
1378 li r0,__got2_entries@sectoff@l
1379 la r3,GOT(_GOT2_TABLE_)
1380 lwz r11,GOT(_GOT2_TABLE_)
1392 * Now adjust the fixups and the pointers to the fixups
1393 * in case we need to move ourselves again.
1395 li r0,__fixup_entries@sectoff@l
1396 lwz r3,GOT(_FIXUP_TABLE_)
1412 * Now clear BSS segment
1414 lwz r3,GOT(__bss_start)
1415 lwz r4,GOT(__bss_end__)
1428 mr r3,r9 /* Init Data pointer */
1429 mr r4,r10 /* Destination Address */
1432 #ifndef CONFIG_NAND_SPL
1434 * Copy exception vector code to low memory
1437 * r7: source address, r8: end address, r9: target address
1441 mflr r4 /* save link register */
1443 lwz r7,GOT(_start_of_vectors)
1444 lwz r8,GOT(_end_of_vectors)
1446 li r9,0x100 /* reset vector always at 0x100 */
1449 bgelr /* return if r7>=r8 - just in case */
1459 * relocate `hdlr' and `int_return' entries
1461 li r7,.L_CriticalInput - _start + _START_OFFSET
1463 li r7,.L_MachineCheck - _start + _START_OFFSET
1465 li r7,.L_DataStorage - _start + _START_OFFSET
1467 li r7,.L_InstStorage - _start + _START_OFFSET
1469 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1471 li r7,.L_Alignment - _start + _START_OFFSET
1473 li r7,.L_ProgramCheck - _start + _START_OFFSET
1475 li r7,.L_FPUnavailable - _start + _START_OFFSET
1477 li r7,.L_Decrementer - _start + _START_OFFSET
1479 li r7,.L_IntervalTimer - _start + _START_OFFSET
1480 li r8,_end_of_vectors - _start + _START_OFFSET
1483 addi r7,r7,0x100 /* next exception vector */
1490 mtlr r4 /* restore link register */
1493 .globl unlock_ram_in_cache
1494 unlock_ram_in_cache:
1495 /* invalidate the INIT_RAM section */
1496 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1497 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1500 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1503 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1507 /* Invalidate the TLB entries for the cache */
1508 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1509 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1522 mfspr r3,SPRN_L1CFG0
1524 rlwinm r5,r3,9,3 /* Extract cache block size */
1525 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1526 * are currently defined.
1529 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1530 * log2(number of ways)
1532 slw r5,r4,r5 /* r5 = cache block size */
1534 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1535 mulli r7,r7,13 /* An 8-way cache will require 13
1540 /* save off HID0 and set DCFA */
1542 ori r9,r8,HID0_DCFA@l
1549 1: lwz r3,0(r4) /* Load... */
1557 1: dcbf 0,r4 /* ...and flush. */
1570 #include "fixed_ivor.S"
1572 #endif /* !CONFIG_NAND_SPL */