2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
15 #include <asm-offsets.h>
20 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
22 #include <ppc_asm.tmpl>
25 #include <asm/cache.h>
29 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
31 #if defined(CONFIG_NAND_SPL) || \
32 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
36 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
37 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
42 * Set up GOT: Global Offset Table
44 * Use r12 to access the GOT
47 GOT_ENTRY(_GOT2_TABLE_)
48 GOT_ENTRY(_FIXUP_TABLE_)
52 GOT_ENTRY(_start_of_vectors)
53 GOT_ENTRY(_end_of_vectors)
54 GOT_ENTRY(transfer_to_handler)
59 GOT_ENTRY(__bss_start)
63 * e500 Startup -- after reset only the last 4KB of the effective
64 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
65 * section is located at THIS LAST page and basically does three
66 * things: clear some registers, set up exception tables and
67 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
68 * continue the boot procedure.
70 * Once the boot rom is mapped by TLB entries we can proceed
71 * with normal startup.
79 /* Enable debug exception */
83 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
86 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
90 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
91 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
96 /* Not a supported revision affected by erratum */
100 1: li r27,1 /* Remember for later that we have the erratum */
101 /* Erratum says set bits 55:60 to 001001 */
112 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
113 /* ISBC uses L2 as stack.
114 * Disable L2 cache here so that u-boot can enable it later
115 * as part of it's normal flow
118 /* Check if L2 is enabled */
119 mfspr r3, SPRN_L2CSR0
121 ori r2, r2, L2CSR0_L2E@l
125 mfspr r3, SPRN_L2CSR0
127 lis r2,(L2CSR0_L2FL)@h
128 ori r2, r2, (L2CSR0_L2FL)@l
135 mfspr r3, SPRN_L2CSR0
139 mfspr r3, SPRN_L2CSR0
141 ori r2, r2, L2CSR0_L2E@l
151 /* clear registers/arrays not reset by hardware */
155 mtspr L1CSR0,r0 /* invalidate d-cache */
156 mtspr L1CSR1,r0 /* invalidate i-cache */
159 mtspr DBSR,r1 /* Clear all valid bits */
162 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
163 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
164 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
166 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
167 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
169 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
170 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
172 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
173 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
175 lis \scratch, \phy_high@h
176 ori \scratch, \scratch, \phy_high@l
184 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
185 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
186 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
188 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
189 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
191 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
192 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
194 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
195 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
197 lis \scratch, \phy_high@h
198 ori \scratch, \scratch, \phy_high@l
206 .macro delete_tlb1_entry esel scratch
207 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
208 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
218 .macro delete_tlb0_entry esel epn wimg scratch
219 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
220 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
224 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
225 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
233 /* Interrupt vectors do not fit in minimal SPL. */
234 #if !defined(MINIMAL_SPL)
235 /* Setup interrupt vectors */
236 lis r1,CONFIG_SYS_MONITOR_BASE@h
239 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
240 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
242 addi r4,r3,CriticalInput - _start + _START_OFFSET
243 mtspr IVOR0,r4 /* 0: Critical input */
244 addi r4,r3,MachineCheck - _start + _START_OFFSET
245 mtspr IVOR1,r4 /* 1: Machine check */
246 addi r4,r3,DataStorage - _start + _START_OFFSET
247 mtspr IVOR2,r4 /* 2: Data storage */
248 addi r4,r3,InstStorage - _start + _START_OFFSET
249 mtspr IVOR3,r4 /* 3: Instruction storage */
250 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
251 mtspr IVOR4,r4 /* 4: External interrupt */
252 addi r4,r3,Alignment - _start + _START_OFFSET
253 mtspr IVOR5,r4 /* 5: Alignment */
254 addi r4,r3,ProgramCheck - _start + _START_OFFSET
255 mtspr IVOR6,r4 /* 6: Program check */
256 addi r4,r3,FPUnavailable - _start + _START_OFFSET
257 mtspr IVOR7,r4 /* 7: floating point unavailable */
258 addi r4,r3,SystemCall - _start + _START_OFFSET
259 mtspr IVOR8,r4 /* 8: System call */
260 /* 9: Auxiliary processor unavailable(unsupported) */
261 addi r4,r3,Decrementer - _start + _START_OFFSET
262 mtspr IVOR10,r4 /* 10: Decrementer */
263 addi r4,r3,IntervalTimer - _start + _START_OFFSET
264 mtspr IVOR11,r4 /* 11: Interval timer */
265 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
266 mtspr IVOR12,r4 /* 12: Watchdog timer */
267 addi r4,r3,DataTLBError - _start + _START_OFFSET
268 mtspr IVOR13,r4 /* 13: Data TLB error */
269 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
270 mtspr IVOR14,r4 /* 14: Instruction TLB error */
271 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
272 mtspr IVOR15,r4 /* 15: Debug */
275 /* Clear and set up some registers. */
278 mtspr DEC,r0 /* prevent dec exceptions */
279 mttbl r0 /* prevent fit & wdt exceptions */
281 mtspr TSR,r1 /* clear all timer exception status */
282 mtspr TCR,r0 /* disable all */
283 mtspr ESR,r0 /* clear exception syndrome register */
284 mtspr MCSR,r0 /* machine check syndrome register */
285 mtxer r0 /* clear integer exception register */
287 #ifdef CONFIG_SYS_BOOK3E_HV
288 mtspr MAS8,r0 /* make sure MAS8 is clear */
291 /* Enable Time Base and Select Time Base Clock */
292 lis r0,HID0_EMCP@h /* Enable machine check */
293 #if defined(CONFIG_ENABLE_36BIT_PHYS)
294 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
296 #ifndef CONFIG_E500MC
297 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
301 #ifndef CONFIG_E500MC
302 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
305 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
307 /* Set MBDD bit also */
308 ori r0, r0, HID1_MBDD@l
313 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
319 /* Enable Branch Prediction */
320 #if defined(CONFIG_BTB)
321 lis r0,BUCSR_ENABLE@h
322 ori r0,r0,BUCSR_ENABLE@l
326 #if defined(CONFIG_SYS_INIT_DBCR)
329 mtspr DBSR,r1 /* Clear all status bits */
330 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
331 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
335 #ifdef CONFIG_MPC8569
336 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
337 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
339 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
340 * use address space which is more than 12bits, and it must be done in
341 * the 4K boot page. So we set this bit here.
344 /* create a temp mapping TLB0[0] for LBCR */
345 create_tlb0_entry 0, \
346 0, BOOKE_PAGESZ_4K, \
347 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
348 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
351 /* Set LBCR register */
352 lis r4,CONFIG_SYS_LBCR_ADDR@h
353 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
355 lis r5,CONFIG_SYS_LBC_LBCR@h
356 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
360 /* invalidate this temp TLB */
361 lis r4,CONFIG_SYS_LBC_ADDR@h
362 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
366 #endif /* CONFIG_MPC8569 */
369 * Search for the TLB that covers the code we're executing, and shrink it
370 * so that it covers only this 4K page. That will ensure that any other
371 * TLB we create won't interfere with it. We assume that the TLB exists,
372 * which is why we don't check the Valid bit of MAS1. We also assume
375 * This is necessary, for example, when booting from the on-chip ROM,
376 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
378 bl nexti /* Find our address */
379 nexti: mflr r1 /* R1 = our PC */
381 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
384 tlbsx 0, r1 /* This must succeed */
386 mfspr r14, MAS0 /* Save ESEL for later */
387 rlwinm r14, r14, 16, 0xfff
389 /* Set the size of the TLB to 4KB */
392 andc r3, r3, r2 /* Clear the TSIZE bits */
393 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
394 oris r3, r3, MAS1_IPROT@h
398 * Set the base address of the TLB to our PC. We assume that
399 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
402 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
404 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
409 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
412 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
413 rlwinm r2, r2, 0, ~MAS2_I
417 mtspr MAS2, r2 /* Set the EPN to our PC base address */
422 mtspr MAS3, r2 /* Set the RPN to our PC base address */
429 * Clear out any other TLB entries that may exist, to avoid conflicts.
430 * Our TLB entry is in r14.
432 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
436 mfspr r4, SPRN_TLB1CFG
437 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
442 rlwinm r5, r3, 16, MAS0_ESEL_MSK
444 beq 2f /* skip the entry we're executing from */
446 oris r5, r5, MAS0_TLBSEL(1)@h
457 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
459 * TLB entry for debuggging in AS1
460 * Create temporary TLB entry in AS0 to handle debug exception
461 * As on debug exception MSR is cleared i.e. Address space is changed
462 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
468 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
469 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
470 * and this window is outside of 4K boot window.
472 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
473 0, BOOKE_PAGESZ_4M, \
474 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
475 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
478 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
479 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
480 0, BOOKE_PAGESZ_1M, \
481 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
482 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
486 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
487 * because "nexti" will resize TLB to 4K
489 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
490 0, BOOKE_PAGESZ_256K, \
491 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
492 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
498 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
499 * location is not where we want it. This typically happens on a 36-bit
500 * system, where we want to move CCSR to near the top of 36-bit address space.
502 * To move CCSR, we create two temporary TLBs, one for the old location, and
503 * another for the new location. On CoreNet systems, we also need to create
504 * a special, temporary LAW.
506 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
507 * long-term TLBs, so we use TLB0 here.
509 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
511 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
512 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
517 * Create a TLB for the new location of CCSR. Register R8 is reserved
518 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
520 lis r8, CONFIG_SYS_CCSRBAR@h
521 ori r8, r8, CONFIG_SYS_CCSRBAR@l
522 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
523 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
524 create_tlb0_entry 0, \
525 0, BOOKE_PAGESZ_4K, \
526 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
527 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
528 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
530 * Create a TLB for the current location of CCSR. Register R9 is reserved
531 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
534 create_tlb0_entry 1, \
535 0, BOOKE_PAGESZ_4K, \
536 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
537 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
538 0, r3 /* The default CCSR address is always a 32-bit number */
542 * We have a TLB for what we think is the current (old) CCSR. Let's
543 * verify that, otherwise we won't be able to move it.
544 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
545 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
548 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
549 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
550 #ifdef CONFIG_FSL_CORENET
551 lwz r1, 4(r9) /* CCSRBARL */
553 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
560 * If the value we read from CCSRBARL is not what we expect, then
561 * enter an infinite loop. This will at least allow a debugger to
562 * halt execution and examine TLBs, etc. There's no point in going
566 bne infinite_debug_loop
568 #ifdef CONFIG_FSL_CORENET
570 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
571 #define LAW_EN 0x80000000
572 #define LAW_SIZE_4K 0xb
573 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
574 #define CCSRAR_C 0x80000000 /* Commit */
578 * On CoreNet systems, we create the temporary LAW using a special LAW
579 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
581 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
582 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
583 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
584 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
585 lis r2, CCSRBAR_LAWAR@h
586 ori r2, r2, CCSRBAR_LAWAR@l
588 stw r0, 0xc00(r9) /* LAWBARH0 */
589 stw r1, 0xc04(r9) /* LAWBARL0 */
591 stw r2, 0xc08(r9) /* LAWAR0 */
594 * Read back from LAWAR to ensure the update is complete. e500mc
595 * cores also require an isync.
597 lwz r0, 0xc08(r9) /* LAWAR0 */
601 * Read the current CCSRBARH and CCSRBARL using load word instructions.
602 * Follow this with an isync instruction. This forces any outstanding
603 * accesses to configuration space to completion.
606 lwz r0, 0(r9) /* CCSRBARH */
607 lwz r0, 4(r9) /* CCSRBARL */
611 * Write the new values for CCSRBARH and CCSRBARL to their old
612 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
613 * has a new value written it loads a CCSRBARH shadow register. When
614 * the CCSRBARL is written, the CCSRBARH shadow register contents
615 * along with the CCSRBARL value are loaded into the CCSRBARH and
616 * CCSRBARL registers, respectively. Follow this with a sync
620 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
621 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
622 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
623 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
625 ori r2, r2, CCSRAR_C@l
627 stw r0, 0(r9) /* Write to CCSRBARH */
628 sync /* Make sure we write to CCSRBARH first */
629 stw r1, 4(r9) /* Write to CCSRBARL */
633 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
634 * Follow this with a sync instruction.
639 /* Delete the temporary LAW */
648 #else /* #ifdef CONFIG_FSL_CORENET */
652 * Read the current value of CCSRBAR using a load word instruction
653 * followed by an isync. This forces all accesses to configuration
660 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
661 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
662 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
664 /* Write the new value to CCSRBAR. */
665 lis r0, CCSRBAR_PHYS_RS12@h
666 ori r0, r0, CCSRBAR_PHYS_RS12@l
671 * The manual says to perform a load of an address that does not
672 * access configuration space or the on-chip SRAM using an existing TLB,
673 * but that doesn't appear to be necessary. We will do the isync,
679 * Read the contents of CCSRBAR from its new location, followed by
685 #endif /* #ifdef CONFIG_FSL_CORENET */
687 /* Delete the temporary TLBs */
689 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
690 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
692 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
694 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
697 * Create a TLB for the MMR location of CCSR
698 * to access L2CSR0 register
700 create_tlb0_entry 0, \
701 0, BOOKE_PAGESZ_4K, \
702 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
703 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
704 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
706 enable_l2_cluster_l2:
707 /* enable L2 cache */
708 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
709 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
710 li r4, 33 /* stash id */
712 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
713 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
715 stw r4, 0(r3) /* invalidate L2 */
722 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
723 ori r4, r4, (L2CSR0_L2REP_MODE)@l
725 stw r4, 0(r3) /* enable L2 */
727 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
731 * Enable the L1. On e6500, this has to be done
732 * after the L2 is up.
735 #ifdef CONFIG_SYS_CACHE_STASHING
736 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
741 /* Enable/invalidate the I-Cache */
742 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
743 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
750 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
751 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
756 andi. r1,r3,L1CSR1_ICE@l
759 /* Enable/invalidate the D-Cache */
760 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
761 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
768 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
769 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
774 andi. r1,r3,L1CSR0_DCE@l
776 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
777 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
778 #define LAW_SIZE_1M 0x13
779 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
785 * Create a TLB entry for CCSR
787 * We're executing out of TLB1 entry in r14, and that's the only
788 * TLB entry that exists. To allocate some TLB entries for our
789 * own use, flip a bit high enough that we won't flip it again
794 lis r0, MAS0_TLBSEL(1)@h
795 rlwimi r0, r8, 16, MAS0_ESEL_MSK
796 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
797 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
798 lis r7, CONFIG_SYS_CCSRBAR@h
799 ori r7, r7, CONFIG_SYS_CCSRBAR@l
800 ori r2, r7, MAS2_I|MAS2_G
801 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
802 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
803 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
804 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
815 /* Map DCSR temporarily to physical address zero */
817 lis r3, DCSRBAR_LAWAR@h
818 ori r3, r3, DCSRBAR_LAWAR@l
820 stw r0, 0xc00(r7) /* LAWBARH0 */
821 stw r0, 0xc04(r7) /* LAWBARL0 */
823 stw r3, 0xc08(r7) /* LAWAR0 */
825 /* Read back from LAWAR to ensure the update is complete. */
826 lwz r3, 0xc08(r7) /* LAWAR0 */
829 /* Create a TLB entry for DCSR at zero */
832 lis r0, MAS0_TLBSEL(1)@h
833 rlwimi r0, r9, 16, MAS0_ESEL_MSK
834 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
835 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
836 li r6, 0 /* DCSR effective address */
837 ori r2, r6, MAS2_I|MAS2_G
838 li r3, MAS3_SW|MAS3_SR
850 /* enable the timebase */
851 #define CTBENR 0xe2084
853 addis r4, r7, CTBENR@ha
859 .macro erratum_set_ccsr offset value
860 addis r3, r7, \offset@ha
862 addi r3, r3, \offset@l
867 .macro erratum_set_dcsr offset value
868 addis r3, r6, \offset@ha
870 addi r3, r3, \offset@l
875 erratum_set_dcsr 0xb0e08 0xe0201800
876 erratum_set_dcsr 0xb0e18 0xe0201800
877 erratum_set_dcsr 0xb0e38 0xe0400000
878 erratum_set_dcsr 0xb0008 0x00900000
879 erratum_set_dcsr 0xb0e40 0xe00a0000
880 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
881 erratum_set_ccsr 0x10f00 0x415e5000
882 erratum_set_ccsr 0x11f00 0x415e5000
884 /* Make temp mapping uncacheable again, if it was initially */
889 rlwimi r4, r15, 0, MAS2_I
890 rlwimi r4, r15, 0, MAS2_G
897 /* Clear the cache */
898 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
899 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
909 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
910 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
920 /* Remove temporary mappings */
921 lis r0, MAS0_TLBSEL(1)@h
922 rlwimi r0, r9, 16, MAS0_ESEL_MSK
932 stw r3, 0xc08(r7) /* LAWAR0 */
936 lis r0, MAS0_TLBSEL(1)@h
937 rlwimi r0, r8, 16, MAS0_ESEL_MSK
948 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
950 /* Lock two cache lines into I-Cache */
952 mfspr r11, SPRN_L1CSR1
953 rlwinm r11, r11, 0, ~L1CSR1_ICUL
956 mtspr SPRN_L1CSR1, r11
967 mfspr r11, SPRN_L1CSR1
968 3: andi. r11, r11, L1CSR1_ICUL
975 mfspr r11, SPRN_L1CSR1
976 3: andi. r11, r11, L1CSR1_ICUL
981 /* Inside a locked cacheline, wait a while, write, then wait a while */
985 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
986 4: mfspr r5, SPRN_TBRL
993 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
994 4: mfspr r5, SPRN_TBRL
1001 * Fill out the rest of this cache line and the next with nops,
1002 * to ensure that nothing outside the locked area will be
1003 * fetched due to a branch.
1010 mfspr r11, SPRN_L1CSR1
1011 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1014 mtspr SPRN_L1CSR1, r11
1023 create_init_ram_area:
1024 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1025 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1028 /* create a temp mapping in AS=1 to the 4M boot window */
1029 create_tlb1_entry 15, \
1030 1, BOOKE_PAGESZ_4M, \
1031 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1032 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1035 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1036 /* create a temp mapping in AS = 1 for Flash mapping
1037 * created by PBL for ISBC code
1039 create_tlb1_entry 15, \
1040 1, BOOKE_PAGESZ_1M, \
1041 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1042 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1046 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1047 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1049 create_tlb1_entry 15, \
1050 1, BOOKE_PAGESZ_1M, \
1051 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1052 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1056 /* create a temp mapping in AS=1 to the stack */
1057 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1058 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1059 create_tlb1_entry 14, \
1060 1, BOOKE_PAGESZ_16K, \
1061 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1062 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1063 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1066 create_tlb1_entry 14, \
1067 1, BOOKE_PAGESZ_16K, \
1068 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1069 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1073 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1074 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1076 ori r7,r7,switch_as@l
1083 /* L1 DCache is used for initial RAM */
1085 /* Allocate Initial RAM in data cache.
1087 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1088 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1091 /* cache size * 1024 / (2 * L1 line size) */
1092 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1098 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1101 /* Jump out the last 4K page and continue to 'normal' start */
1102 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1103 /* We assume that we're already running at the address we're linked at */
1106 /* Calculate absolute address in FLASH and jump there */
1107 /*--------------------------------------------------------------*/
1108 lis r3,CONFIG_SYS_MONITOR_BASE@h
1109 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1110 addi r3,r3,_start_cont - _start + _START_OFFSET
1118 .long 0x27051956 /* U-BOOT Magic Number */
1119 .globl version_string
1121 .ascii U_BOOT_VERSION_STRING, "\0"
1126 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1127 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1128 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1130 stw r0,0(r3) /* Terminate Back Chain */
1131 stw r0,+4(r3) /* NULL return address. */
1132 mr r1,r3 /* Transfer to SP(r1) */
1137 /* switch back to AS = 0 */
1138 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1139 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1147 /* NOTREACHED - board_init_f() does not return */
1150 . = EXC_OFF_SYS_RESET
1151 .globl _start_of_vectors
1154 /* Critical input. */
1155 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1158 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1160 /* Data Storage exception. */
1161 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1163 /* Instruction Storage exception. */
1164 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1166 /* External Interrupt exception. */
1167 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1169 /* Alignment exception. */
1172 EXCEPTION_PROLOG(SRR0, SRR1)
1177 addi r3,r1,STACK_FRAME_OVERHEAD
1178 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1180 /* Program check exception */
1183 EXCEPTION_PROLOG(SRR0, SRR1)
1184 addi r3,r1,STACK_FRAME_OVERHEAD
1185 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1186 MSR_KERNEL, COPY_EE)
1188 /* No FPU on MPC85xx. This exception is not supposed to happen.
1190 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1194 * r0 - SYSCALL number
1198 addis r11,r0,0 /* get functions table addr */
1199 ori r11,r11,0 /* Note: this code is patched in trap_init */
1200 addis r12,r0,0 /* get number of functions */
1206 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1210 li r20,0xd00-4 /* Get stack pointer */
1212 subi r12,r12,12 /* Adjust stack pointer */
1213 li r0,0xc00+_end_back-SystemCall
1214 cmplw 0,r0,r12 /* Check stack overflow */
1225 li r12,0xc00+_back-SystemCall
1233 mfmsr r11 /* Disable interrupts */
1237 SYNC /* Some chip revs need this... */
1241 li r12,0xd00-4 /* restore regs */
1251 addi r12,r12,12 /* Adjust stack pointer */
1259 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1260 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1261 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1263 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1264 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1266 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1268 .globl _end_of_vectors
1272 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1275 * This code finishes saving the registers to the exception frame
1276 * and jumps to the appropriate handler for the exception.
1277 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1279 .globl transfer_to_handler
1280 transfer_to_handler:
1291 andi. r24,r23,0x3f00 /* get vector offset */
1295 mtspr SPRG2,r22 /* r1 is now kernel sp */
1297 lwz r24,0(r23) /* virtual address of handler */
1298 lwz r23,4(r23) /* where to go when done */
1303 rfi /* jump to handler, enable MMU */
1306 mfmsr r28 /* Disable interrupts */
1310 SYNC /* Some chip revs need this... */
1325 lwz r2,_NIP(r1) /* Restore environment */
1336 mfmsr r28 /* Disable interrupts */
1340 SYNC /* Some chip revs need this... */
1355 lwz r2,_NIP(r1) /* Restore environment */
1366 mfmsr r28 /* Disable interrupts */
1370 SYNC /* Some chip revs need this... */
1385 lwz r2,_NIP(r1) /* Restore environment */
1387 mtspr SPRN_MCSRR0,r2
1388 mtspr SPRN_MCSRR1,r0
1399 .globl invalidate_icache
1402 ori r0,r0,L1CSR1_ICFI
1407 blr /* entire I cache */
1409 .globl invalidate_dcache
1412 ori r0,r0,L1CSR0_DCFI
1419 .globl icache_enable
1422 bl invalidate_icache
1432 .globl icache_disable
1436 ori r3,r3,L1CSR1_ICE
1442 .globl icache_status
1445 andi. r3,r3,L1CSR1_ICE
1448 .globl dcache_enable
1451 bl invalidate_dcache
1463 .globl dcache_disable
1467 ori r4,r4,L1CSR0_DCE
1473 .globl dcache_status
1476 andi. r3,r3,L1CSR0_DCE
1499 /*------------------------------------------------------------------------------- */
1501 /* Description: Input 8 bits */
1502 /*------------------------------------------------------------------------------- */
1508 /*------------------------------------------------------------------------------- */
1509 /* Function: out8 */
1510 /* Description: Output 8 bits */
1511 /*------------------------------------------------------------------------------- */
1518 /*------------------------------------------------------------------------------- */
1519 /* Function: out16 */
1520 /* Description: Output 16 bits */
1521 /*------------------------------------------------------------------------------- */
1528 /*------------------------------------------------------------------------------- */
1529 /* Function: out16r */
1530 /* Description: Byte reverse and output 16 bits */
1531 /*------------------------------------------------------------------------------- */
1538 /*------------------------------------------------------------------------------- */
1539 /* Function: out32 */
1540 /* Description: Output 32 bits */
1541 /*------------------------------------------------------------------------------- */
1548 /*------------------------------------------------------------------------------- */
1549 /* Function: out32r */
1550 /* Description: Byte reverse and output 32 bits */
1551 /*------------------------------------------------------------------------------- */
1558 /*------------------------------------------------------------------------------- */
1559 /* Function: in16 */
1560 /* Description: Input 16 bits */
1561 /*------------------------------------------------------------------------------- */
1567 /*------------------------------------------------------------------------------- */
1568 /* Function: in16r */
1569 /* Description: Input 16 bits and byte reverse */
1570 /*------------------------------------------------------------------------------- */
1576 /*------------------------------------------------------------------------------- */
1577 /* Function: in32 */
1578 /* Description: Input 32 bits */
1579 /*------------------------------------------------------------------------------- */
1585 /*------------------------------------------------------------------------------- */
1586 /* Function: in32r */
1587 /* Description: Input 32 bits and byte reverse */
1588 /*------------------------------------------------------------------------------- */
1593 #endif /* !MINIMAL_SPL */
1595 /*------------------------------------------------------------------------------*/
1598 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1606 #ifdef CONFIG_ENABLE_36BIT_PHYS
1610 #ifdef CONFIG_SYS_BOOK3E_HV
1620 * void relocate_code (addr_sp, gd, addr_moni)
1622 * This "function" does not return, instead it continues in RAM
1623 * after relocating the monitor code.
1627 * r5 = length in bytes
1628 * r6 = cachelinesize
1630 .globl relocate_code
1632 mr r1,r3 /* Set new stack pointer */
1633 mr r9,r4 /* Save copy of Init Data pointer */
1634 mr r10,r5 /* Save copy of Destination Address */
1637 mr r3,r5 /* Destination Address */
1638 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1639 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1640 lwz r5,GOT(__init_end)
1642 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1647 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1653 /* First our own GOT */
1655 /* the the one used by the C code */
1665 beq cr1,4f /* In place copy is not necessary */
1666 beq 7f /* Protect against 0 count */
1685 * Now flush the cache: note that we must start from a cache aligned
1686 * address. Otherwise we might miss one cache line.
1690 beq 7f /* Always flush prefetch queue in any case */
1698 sync /* Wait for all dcbst to complete on bus */
1704 7: sync /* Wait for all icbi to complete on bus */
1708 * We are done. Do not return, instead branch to second part of board
1709 * initialization, now running from RAM.
1712 addi r0,r10,in_ram - _start + _START_OFFSET
1715 * As IVPR is going to point RAM address,
1716 * Make sure IVOR15 has valid opcode to support debugger
1721 * Re-point the IVPR at RAM
1726 blr /* NEVER RETURNS! */
1731 * Relocation Function, r12 point to got2+0x8000
1733 * Adjust got2 pointers, no need to check for 0, this code
1734 * already puts a few entries in the table.
1736 li r0,__got2_entries@sectoff@l
1737 la r3,GOT(_GOT2_TABLE_)
1738 lwz r11,GOT(_GOT2_TABLE_)
1750 * Now adjust the fixups and the pointers to the fixups
1751 * in case we need to move ourselves again.
1753 li r0,__fixup_entries@sectoff@l
1754 lwz r3,GOT(_FIXUP_TABLE_)
1770 * Now clear BSS segment
1772 lwz r3,GOT(__bss_start)
1773 lwz r4,GOT(__bss_end)
1786 mr r3,r9 /* Init Data pointer */
1787 mr r4,r10 /* Destination Address */
1792 * Copy exception vector code to low memory
1795 * r7: source address, r8: end address, r9: target address
1799 mflr r4 /* save link register */
1801 lwz r7,GOT(_start_of_vectors)
1802 lwz r8,GOT(_end_of_vectors)
1804 li r9,0x100 /* reset vector always at 0x100 */
1807 bgelr /* return if r7>=r8 - just in case */
1817 * relocate `hdlr' and `int_return' entries
1819 li r7,.L_CriticalInput - _start + _START_OFFSET
1821 li r7,.L_MachineCheck - _start + _START_OFFSET
1823 li r7,.L_DataStorage - _start + _START_OFFSET
1825 li r7,.L_InstStorage - _start + _START_OFFSET
1827 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1829 li r7,.L_Alignment - _start + _START_OFFSET
1831 li r7,.L_ProgramCheck - _start + _START_OFFSET
1833 li r7,.L_FPUnavailable - _start + _START_OFFSET
1835 li r7,.L_Decrementer - _start + _START_OFFSET
1837 li r7,.L_IntervalTimer - _start + _START_OFFSET
1838 li r8,_end_of_vectors - _start + _START_OFFSET
1841 addi r7,r7,0x100 /* next exception vector */
1845 /* Update IVORs as per relocated vector table address */
1847 mtspr IVOR0,r7 /* 0: Critical input */
1849 mtspr IVOR1,r7 /* 1: Machine check */
1851 mtspr IVOR2,r7 /* 2: Data storage */
1853 mtspr IVOR3,r7 /* 3: Instruction storage */
1855 mtspr IVOR4,r7 /* 4: External interrupt */
1857 mtspr IVOR5,r7 /* 5: Alignment */
1859 mtspr IVOR6,r7 /* 6: Program check */
1861 mtspr IVOR7,r7 /* 7: floating point unavailable */
1863 mtspr IVOR8,r7 /* 8: System call */
1864 /* 9: Auxiliary processor unavailable(unsupported) */
1866 mtspr IVOR10,r7 /* 10: Decrementer */
1868 mtspr IVOR11,r7 /* 11: Interval timer */
1870 mtspr IVOR12,r7 /* 12: Watchdog timer */
1872 mtspr IVOR13,r7 /* 13: Data TLB error */
1874 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1876 mtspr IVOR15,r7 /* 15: Debug */
1881 mtlr r4 /* restore link register */
1884 .globl unlock_ram_in_cache
1885 unlock_ram_in_cache:
1886 /* invalidate the INIT_RAM section */
1887 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1888 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1891 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1895 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1899 /* Invalidate the TLB entries for the cache */
1900 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1901 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1914 mfspr r3,SPRN_L1CFG0
1916 rlwinm r5,r3,9,3 /* Extract cache block size */
1917 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1918 * are currently defined.
1921 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1922 * log2(number of ways)
1924 slw r5,r4,r5 /* r5 = cache block size */
1926 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1927 mulli r7,r7,13 /* An 8-way cache will require 13
1932 /* save off HID0 and set DCFA */
1934 ori r9,r8,HID0_DCFA@l
1941 1: lwz r3,0(r4) /* Load... */
1949 1: dcbf 0,r4 /* ...and flush. */
1962 #include "fixed_ivor.S"
1964 #endif /* !MINIMAL_SPL */