2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
85 /* Enable debug exception */
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
102 /* Not a supported revision affected by erratum */
106 1: li r27,1 /* Remember for later that we have the erratum */
107 /* Erratum says set bits 55:60 to 001001 */
118 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
119 /* ISBC uses L2 as stack.
120 * Disable L2 cache here so that u-boot can enable it later
121 * as part of it's normal flow
124 /* Check if L2 is enabled */
125 mfspr r3, SPRN_L2CSR0
127 ori r2, r2, L2CSR0_L2E@l
131 mfspr r3, SPRN_L2CSR0
133 lis r2,(L2CSR0_L2FL)@h
134 ori r2, r2, (L2CSR0_L2FL)@l
141 mfspr r3, SPRN_L2CSR0
145 mfspr r3, SPRN_L2CSR0
147 ori r2, r2, L2CSR0_L2E@l
157 /* clear registers/arrays not reset by hardware */
161 mtspr L1CSR0,r0 /* invalidate d-cache */
162 mtspr L1CSR1,r0 /* invalidate i-cache */
165 mtspr DBSR,r1 /* Clear all valid bits */
168 * Enable L1 Caches early
172 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
173 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
178 /* Enable/invalidate the I-Cache */
179 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
180 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
187 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
188 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
193 andi. r1,r3,L1CSR1_ICE@l
196 /* Enable/invalidate the D-Cache */
197 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
198 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
205 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
206 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
211 andi. r1,r3,L1CSR0_DCE@l
214 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
215 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
216 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
218 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
219 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
221 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
222 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
224 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
225 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
227 lis \scratch, \phy_high@h
228 ori \scratch, \scratch, \phy_high@l
236 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
237 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
238 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
240 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
241 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
243 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
244 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
246 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
247 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
249 lis \scratch, \phy_high@h
250 ori \scratch, \scratch, \phy_high@l
258 .macro delete_tlb1_entry esel scratch
259 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
260 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
270 .macro delete_tlb0_entry esel epn wimg scratch
271 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
272 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
276 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
277 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
285 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
287 * TLB entry for debuggging in AS1
288 * Create temporary TLB entry in AS0 to handle debug exception
289 * As on debug exception MSR is cleared i.e. Address space is changed
290 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
294 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
296 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
297 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
298 * and this window is outside of 4K boot window.
300 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
301 0, BOOKE_PAGESZ_4M, \
302 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
303 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
306 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
307 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
308 0, BOOKE_PAGESZ_1M, \
309 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
310 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
314 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
315 * because "nexti" will resize TLB to 4K
317 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
318 0, BOOKE_PAGESZ_256K, \
319 CONFIG_SYS_MONITOR_BASE, MAS2_I, \
320 CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
326 * Ne need to setup interrupt vector for NAND SPL
327 * because NAND SPL never compiles it.
329 #if !defined(CONFIG_NAND_SPL)
330 /* Setup interrupt vectors */
331 lis r1,CONFIG_SYS_MONITOR_BASE@h
334 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
335 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
337 addi r4,r3,CriticalInput - _start + _START_OFFSET
338 mtspr IVOR0,r4 /* 0: Critical input */
339 addi r4,r3,MachineCheck - _start + _START_OFFSET
340 mtspr IVOR1,r4 /* 1: Machine check */
341 addi r4,r3,DataStorage - _start + _START_OFFSET
342 mtspr IVOR2,r4 /* 2: Data storage */
343 addi r4,r3,InstStorage - _start + _START_OFFSET
344 mtspr IVOR3,r4 /* 3: Instruction storage */
345 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
346 mtspr IVOR4,r4 /* 4: External interrupt */
347 addi r4,r3,Alignment - _start + _START_OFFSET
348 mtspr IVOR5,r4 /* 5: Alignment */
349 addi r4,r3,ProgramCheck - _start + _START_OFFSET
350 mtspr IVOR6,r4 /* 6: Program check */
351 addi r4,r3,FPUnavailable - _start + _START_OFFSET
352 mtspr IVOR7,r4 /* 7: floating point unavailable */
353 addi r4,r3,SystemCall - _start + _START_OFFSET
354 mtspr IVOR8,r4 /* 8: System call */
355 /* 9: Auxiliary processor unavailable(unsupported) */
356 addi r4,r3,Decrementer - _start + _START_OFFSET
357 mtspr IVOR10,r4 /* 10: Decrementer */
358 addi r4,r3,IntervalTimer - _start + _START_OFFSET
359 mtspr IVOR11,r4 /* 11: Interval timer */
360 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
361 mtspr IVOR12,r4 /* 12: Watchdog timer */
362 addi r4,r3,DataTLBError - _start + _START_OFFSET
363 mtspr IVOR13,r4 /* 13: Data TLB error */
364 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
365 mtspr IVOR14,r4 /* 14: Instruction TLB error */
366 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
367 mtspr IVOR15,r4 /* 15: Debug */
370 /* Clear and set up some registers. */
373 mtspr DEC,r0 /* prevent dec exceptions */
374 mttbl r0 /* prevent fit & wdt exceptions */
376 mtspr TSR,r1 /* clear all timer exception status */
377 mtspr TCR,r0 /* disable all */
378 mtspr ESR,r0 /* clear exception syndrome register */
379 mtspr MCSR,r0 /* machine check syndrome register */
380 mtxer r0 /* clear integer exception register */
382 #ifdef CONFIG_SYS_BOOK3E_HV
383 mtspr MAS8,r0 /* make sure MAS8 is clear */
386 /* Enable Time Base and Select Time Base Clock */
387 lis r0,HID0_EMCP@h /* Enable machine check */
388 #if defined(CONFIG_ENABLE_36BIT_PHYS)
389 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
391 #ifndef CONFIG_E500MC
392 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
396 #ifndef CONFIG_E500MC
397 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
400 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
402 /* Set MBDD bit also */
403 ori r0, r0, HID1_MBDD@l
408 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
414 /* Enable Branch Prediction */
415 #if defined(CONFIG_BTB)
416 lis r0,BUCSR_ENABLE@h
417 ori r0,r0,BUCSR_ENABLE@l
421 #if defined(CONFIG_SYS_INIT_DBCR)
424 mtspr DBSR,r1 /* Clear all status bits */
425 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
426 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
430 #ifdef CONFIG_MPC8569
431 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
432 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
434 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
435 * use address space which is more than 12bits, and it must be done in
436 * the 4K boot page. So we set this bit here.
439 /* create a temp mapping TLB0[0] for LBCR */
440 create_tlb0_entry 0, \
441 0, BOOKE_PAGESZ_4K, \
442 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
443 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
446 /* Set LBCR register */
447 lis r4,CONFIG_SYS_LBCR_ADDR@h
448 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
450 lis r5,CONFIG_SYS_LBC_LBCR@h
451 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
455 /* invalidate this temp TLB */
456 lis r4,CONFIG_SYS_LBC_ADDR@h
457 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
461 #endif /* CONFIG_MPC8569 */
464 * Search for the TLB that covers the code we're executing, and shrink it
465 * so that it covers only this 4K page. That will ensure that any other
466 * TLB we create won't interfere with it. We assume that the TLB exists,
467 * which is why we don't check the Valid bit of MAS1. We also assume
470 * This is necessary, for example, when booting from the on-chip ROM,
471 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
473 bl nexti /* Find our address */
474 nexti: mflr r1 /* R1 = our PC */
476 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
479 tlbsx 0, r1 /* This must succeed */
481 mfspr r14, MAS0 /* Save ESEL for later */
482 rlwinm r14, r14, 16, 0xfff
484 /* Set the size of the TLB to 4KB */
487 andc r3, r3, r2 /* Clear the TSIZE bits */
488 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
489 oris r3, r3, MAS1_IPROT@h
493 * Set the base address of the TLB to our PC. We assume that
494 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
497 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
499 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
504 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
507 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
508 rlwinm r2, r2, 0, ~MAS2_I
512 mtspr MAS2, r2 /* Set the EPN to our PC base address */
517 mtspr MAS3, r2 /* Set the RPN to our PC base address */
524 * Clear out any other TLB entries that may exist, to avoid conflicts.
525 * Our TLB entry is in r14.
527 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
531 mfspr r4, SPRN_TLB1CFG
532 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
537 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
538 cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
539 cror cr0*4+eq, cr0*4+eq, cr1*4+eq
541 rlwinm r5, r3, 16, MAS0_ESEL_MSK
543 beq 2f /* skip the entry we're executing from */
545 oris r5, r5, MAS0_TLBSEL(1)@h
557 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
558 * location is not where we want it. This typically happens on a 36-bit
559 * system, where we want to move CCSR to near the top of 36-bit address space.
561 * To move CCSR, we create two temporary TLBs, one for the old location, and
562 * another for the new location. On CoreNet systems, we also need to create
563 * a special, temporary LAW.
565 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
566 * long-term TLBs, so we use TLB0 here.
568 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
570 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
571 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
576 * Create a TLB for the new location of CCSR. Register R8 is reserved
577 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
579 lis r8, CONFIG_SYS_CCSRBAR@h
580 ori r8, r8, CONFIG_SYS_CCSRBAR@l
581 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
582 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
583 create_tlb0_entry 0, \
584 0, BOOKE_PAGESZ_4K, \
585 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
586 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
587 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
589 * Create a TLB for the current location of CCSR. Register R9 is reserved
590 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
593 create_tlb0_entry 1, \
594 0, BOOKE_PAGESZ_4K, \
595 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
596 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
597 0, r3 /* The default CCSR address is always a 32-bit number */
601 * We have a TLB for what we think is the current (old) CCSR. Let's
602 * verify that, otherwise we won't be able to move it.
603 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
604 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
607 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
608 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
609 #ifdef CONFIG_FSL_CORENET
610 lwz r1, 4(r9) /* CCSRBARL */
612 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
619 * If the value we read from CCSRBARL is not what we expect, then
620 * enter an infinite loop. This will at least allow a debugger to
621 * halt execution and examine TLBs, etc. There's no point in going
625 bne infinite_debug_loop
627 #ifdef CONFIG_FSL_CORENET
629 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
630 #define LAW_EN 0x80000000
631 #define LAW_SIZE_4K 0xb
632 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
633 #define CCSRAR_C 0x80000000 /* Commit */
637 * On CoreNet systems, we create the temporary LAW using a special LAW
638 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
640 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
641 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
642 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
643 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
644 lis r2, CCSRBAR_LAWAR@h
645 ori r2, r2, CCSRBAR_LAWAR@l
647 stw r0, 0xc00(r9) /* LAWBARH0 */
648 stw r1, 0xc04(r9) /* LAWBARL0 */
650 stw r2, 0xc08(r9) /* LAWAR0 */
653 * Read back from LAWAR to ensure the update is complete. e500mc
654 * cores also require an isync.
656 lwz r0, 0xc08(r9) /* LAWAR0 */
660 * Read the current CCSRBARH and CCSRBARL using load word instructions.
661 * Follow this with an isync instruction. This forces any outstanding
662 * accesses to configuration space to completion.
665 lwz r0, 0(r9) /* CCSRBARH */
666 lwz r0, 4(r9) /* CCSRBARL */
670 * Write the new values for CCSRBARH and CCSRBARL to their old
671 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
672 * has a new value written it loads a CCSRBARH shadow register. When
673 * the CCSRBARL is written, the CCSRBARH shadow register contents
674 * along with the CCSRBARL value are loaded into the CCSRBARH and
675 * CCSRBARL registers, respectively. Follow this with a sync
679 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
680 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
681 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
682 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
684 ori r2, r2, CCSRAR_C@l
686 stw r0, 0(r9) /* Write to CCSRBARH */
687 sync /* Make sure we write to CCSRBARH first */
688 stw r1, 4(r9) /* Write to CCSRBARL */
692 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
693 * Follow this with a sync instruction.
698 /* Delete the temporary LAW */
707 #else /* #ifdef CONFIG_FSL_CORENET */
711 * Read the current value of CCSRBAR using a load word instruction
712 * followed by an isync. This forces all accesses to configuration
719 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
720 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
721 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
723 /* Write the new value to CCSRBAR. */
724 lis r0, CCSRBAR_PHYS_RS12@h
725 ori r0, r0, CCSRBAR_PHYS_RS12@l
730 * The manual says to perform a load of an address that does not
731 * access configuration space or the on-chip SRAM using an existing TLB,
732 * but that doesn't appear to be necessary. We will do the isync,
738 * Read the contents of CCSRBAR from its new location, followed by
744 #endif /* #ifdef CONFIG_FSL_CORENET */
746 /* Delete the temporary TLBs */
748 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
749 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
751 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
753 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
754 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
755 #define LAW_SIZE_1M 0x13
756 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
762 * Create a TLB entry for CCSR
764 * We're executing out of TLB1 entry in r14, and that's the only
765 * TLB entry that exists. To allocate some TLB entries for our
766 * own use, flip a bit high enough that we won't flip it again
771 lis r0, MAS0_TLBSEL(1)@h
772 rlwimi r0, r8, 16, MAS0_ESEL_MSK
773 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
774 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
775 lis r7, CONFIG_SYS_CCSRBAR@h
776 ori r7, r7, CONFIG_SYS_CCSRBAR@l
777 ori r2, r7, MAS2_I|MAS2_G
778 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
779 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
780 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
781 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
792 /* Map DCSR temporarily to physical address zero */
794 lis r3, DCSRBAR_LAWAR@h
795 ori r3, r3, DCSRBAR_LAWAR@l
797 stw r0, 0xc00(r7) /* LAWBARH0 */
798 stw r0, 0xc04(r7) /* LAWBARL0 */
800 stw r3, 0xc08(r7) /* LAWAR0 */
802 /* Read back from LAWAR to ensure the update is complete. */
803 lwz r3, 0xc08(r7) /* LAWAR0 */
806 /* Create a TLB entry for DCSR at zero */
809 lis r0, MAS0_TLBSEL(1)@h
810 rlwimi r0, r9, 16, MAS0_ESEL_MSK
811 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
812 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
813 li r6, 0 /* DCSR effective address */
814 ori r2, r6, MAS2_I|MAS2_G
815 li r3, MAS3_SW|MAS3_SR
827 /* enable the timebase */
828 #define CTBENR 0xe2084
830 addis r4, r7, CTBENR@ha
836 .macro erratum_set_ccsr offset value
837 addis r3, r7, \offset@ha
839 addi r3, r3, \offset@l
844 .macro erratum_set_dcsr offset value
845 addis r3, r6, \offset@ha
847 addi r3, r3, \offset@l
852 erratum_set_dcsr 0xb0e08 0xe0201800
853 erratum_set_dcsr 0xb0e18 0xe0201800
854 erratum_set_dcsr 0xb0e38 0xe0400000
855 erratum_set_dcsr 0xb0008 0x00900000
856 erratum_set_dcsr 0xb0e40 0xe00a0000
857 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
858 erratum_set_ccsr 0x10f00 0x415e5000
859 erratum_set_ccsr 0x11f00 0x415e5000
861 /* Make temp mapping uncacheable again, if it was initially */
866 rlwimi r4, r15, 0, MAS2_I
867 rlwimi r4, r15, 0, MAS2_G
874 /* Clear the cache */
875 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
876 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
886 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
887 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
897 /* Remove temporary mappings */
898 lis r0, MAS0_TLBSEL(1)@h
899 rlwimi r0, r9, 16, MAS0_ESEL_MSK
909 stw r3, 0xc08(r7) /* LAWAR0 */
913 lis r0, MAS0_TLBSEL(1)@h
914 rlwimi r0, r8, 16, MAS0_ESEL_MSK
925 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
927 /* Lock two cache lines into I-Cache */
929 mfspr r11, SPRN_L1CSR1
930 rlwinm r11, r11, 0, ~L1CSR1_ICUL
933 mtspr SPRN_L1CSR1, r11
944 mfspr r11, SPRN_L1CSR1
945 3: andi. r11, r11, L1CSR1_ICUL
952 mfspr r11, SPRN_L1CSR1
953 3: andi. r11, r11, L1CSR1_ICUL
958 /* Inside a locked cacheline, wait a while, write, then wait a while */
962 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
963 4: mfspr r5, SPRN_TBRL
970 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
971 4: mfspr r5, SPRN_TBRL
978 * Fill out the rest of this cache line and the next with nops,
979 * to ensure that nothing outside the locked area will be
980 * fetched due to a branch.
987 mfspr r11, SPRN_L1CSR1
988 rlwinm r11, r11, 0, ~L1CSR1_ICUL
991 mtspr SPRN_L1CSR1, r11
1000 create_init_ram_area:
1001 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1002 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1004 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
1005 /* create a temp mapping in AS=1 to the 4M boot window */
1006 create_tlb1_entry 15, \
1007 1, BOOKE_PAGESZ_4M, \
1008 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1009 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1012 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1013 /* create a temp mapping in AS = 1 for Flash mapping
1014 * created by PBL for ISBC code
1016 create_tlb1_entry 15, \
1017 1, BOOKE_PAGESZ_1M, \
1018 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
1019 CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1023 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1024 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1026 create_tlb1_entry 15, \
1027 1, BOOKE_PAGESZ_1M, \
1028 CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
1029 CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
1033 /* create a temp mapping in AS=1 to the stack */
1034 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1035 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1036 create_tlb1_entry 14, \
1037 1, BOOKE_PAGESZ_16K, \
1038 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1039 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1040 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
1043 create_tlb1_entry 14, \
1044 1, BOOKE_PAGESZ_16K, \
1045 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1046 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1050 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1051 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1053 ori r7,r7,switch_as@l
1060 /* L1 DCache is used for initial RAM */
1062 /* Allocate Initial RAM in data cache.
1064 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1065 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1068 /* cache size * 1024 / (2 * L1 line size) */
1069 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1075 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1078 /* Jump out the last 4K page and continue to 'normal' start */
1079 #ifdef CONFIG_SYS_RAMBOOT
1082 /* Calculate absolute address in FLASH and jump there */
1083 /*--------------------------------------------------------------*/
1084 lis r3,CONFIG_SYS_MONITOR_BASE@h
1085 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1086 addi r3,r3,_start_cont - _start + _START_OFFSET
1094 .long 0x27051956 /* U-BOOT Magic Number */
1095 .globl version_string
1097 .ascii U_BOOT_VERSION_STRING, "\0"
1102 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1103 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1104 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1106 stw r0,0(r3) /* Terminate Back Chain */
1107 stw r0,+4(r3) /* NULL return address. */
1108 mr r1,r3 /* Transfer to SP(r1) */
1113 /* switch back to AS = 0 */
1114 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1115 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1123 /* NOTREACHED - board_init_f() does not return */
1125 #ifndef CONFIG_NAND_SPL
1126 . = EXC_OFF_SYS_RESET
1127 .globl _start_of_vectors
1130 /* Critical input. */
1131 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1134 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1136 /* Data Storage exception. */
1137 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1139 /* Instruction Storage exception. */
1140 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1142 /* External Interrupt exception. */
1143 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1145 /* Alignment exception. */
1148 EXCEPTION_PROLOG(SRR0, SRR1)
1153 addi r3,r1,STACK_FRAME_OVERHEAD
1154 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1156 /* Program check exception */
1159 EXCEPTION_PROLOG(SRR0, SRR1)
1160 addi r3,r1,STACK_FRAME_OVERHEAD
1161 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1162 MSR_KERNEL, COPY_EE)
1164 /* No FPU on MPC85xx. This exception is not supposed to happen.
1166 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1170 * r0 - SYSCALL number
1174 addis r11,r0,0 /* get functions table addr */
1175 ori r11,r11,0 /* Note: this code is patched in trap_init */
1176 addis r12,r0,0 /* get number of functions */
1182 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1186 li r20,0xd00-4 /* Get stack pointer */
1188 subi r12,r12,12 /* Adjust stack pointer */
1189 li r0,0xc00+_end_back-SystemCall
1190 cmplw 0,r0,r12 /* Check stack overflow */
1201 li r12,0xc00+_back-SystemCall
1209 mfmsr r11 /* Disable interrupts */
1213 SYNC /* Some chip revs need this... */
1217 li r12,0xd00-4 /* restore regs */
1227 addi r12,r12,12 /* Adjust stack pointer */
1235 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1236 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1237 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1239 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1240 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1242 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1244 .globl _end_of_vectors
1248 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1251 * This code finishes saving the registers to the exception frame
1252 * and jumps to the appropriate handler for the exception.
1253 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1255 .globl transfer_to_handler
1256 transfer_to_handler:
1267 andi. r24,r23,0x3f00 /* get vector offset */
1271 mtspr SPRG2,r22 /* r1 is now kernel sp */
1273 lwz r24,0(r23) /* virtual address of handler */
1274 lwz r23,4(r23) /* where to go when done */
1279 rfi /* jump to handler, enable MMU */
1282 mfmsr r28 /* Disable interrupts */
1286 SYNC /* Some chip revs need this... */
1301 lwz r2,_NIP(r1) /* Restore environment */
1312 mfmsr r28 /* Disable interrupts */
1316 SYNC /* Some chip revs need this... */
1331 lwz r2,_NIP(r1) /* Restore environment */
1342 mfmsr r28 /* Disable interrupts */
1346 SYNC /* Some chip revs need this... */
1361 lwz r2,_NIP(r1) /* Restore environment */
1363 mtspr SPRN_MCSRR0,r2
1364 mtspr SPRN_MCSRR1,r0
1375 .globl invalidate_icache
1378 ori r0,r0,L1CSR1_ICFI
1383 blr /* entire I cache */
1385 .globl invalidate_dcache
1388 ori r0,r0,L1CSR0_DCFI
1395 .globl icache_enable
1398 bl invalidate_icache
1408 .globl icache_disable
1412 ori r3,r3,L1CSR1_ICE
1418 .globl icache_status
1421 andi. r3,r3,L1CSR1_ICE
1424 .globl dcache_enable
1427 bl invalidate_dcache
1439 .globl dcache_disable
1443 ori r4,r4,L1CSR0_DCE
1449 .globl dcache_status
1452 andi. r3,r3,L1CSR0_DCE
1475 /*------------------------------------------------------------------------------- */
1477 /* Description: Input 8 bits */
1478 /*------------------------------------------------------------------------------- */
1484 /*------------------------------------------------------------------------------- */
1485 /* Function: out8 */
1486 /* Description: Output 8 bits */
1487 /*------------------------------------------------------------------------------- */
1494 /*------------------------------------------------------------------------------- */
1495 /* Function: out16 */
1496 /* Description: Output 16 bits */
1497 /*------------------------------------------------------------------------------- */
1504 /*------------------------------------------------------------------------------- */
1505 /* Function: out16r */
1506 /* Description: Byte reverse and output 16 bits */
1507 /*------------------------------------------------------------------------------- */
1514 /*------------------------------------------------------------------------------- */
1515 /* Function: out32 */
1516 /* Description: Output 32 bits */
1517 /*------------------------------------------------------------------------------- */
1524 /*------------------------------------------------------------------------------- */
1525 /* Function: out32r */
1526 /* Description: Byte reverse and output 32 bits */
1527 /*------------------------------------------------------------------------------- */
1534 /*------------------------------------------------------------------------------- */
1535 /* Function: in16 */
1536 /* Description: Input 16 bits */
1537 /*------------------------------------------------------------------------------- */
1543 /*------------------------------------------------------------------------------- */
1544 /* Function: in16r */
1545 /* Description: Input 16 bits and byte reverse */
1546 /*------------------------------------------------------------------------------- */
1552 /*------------------------------------------------------------------------------- */
1553 /* Function: in32 */
1554 /* Description: Input 32 bits */
1555 /*------------------------------------------------------------------------------- */
1561 /*------------------------------------------------------------------------------- */
1562 /* Function: in32r */
1563 /* Description: Input 32 bits and byte reverse */
1564 /*------------------------------------------------------------------------------- */
1569 #endif /* !CONFIG_NAND_SPL */
1571 /*------------------------------------------------------------------------------*/
1574 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1582 #ifdef CONFIG_ENABLE_36BIT_PHYS
1586 #ifdef CONFIG_SYS_BOOK3E_HV
1596 * void relocate_code (addr_sp, gd, addr_moni)
1598 * This "function" does not return, instead it continues in RAM
1599 * after relocating the monitor code.
1603 * r5 = length in bytes
1604 * r6 = cachelinesize
1606 .globl relocate_code
1608 mr r1,r3 /* Set new stack pointer */
1609 mr r9,r4 /* Save copy of Init Data pointer */
1610 mr r10,r5 /* Save copy of Destination Address */
1613 mr r3,r5 /* Destination Address */
1614 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1615 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1616 lwz r5,GOT(__init_end)
1618 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1623 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1629 /* First our own GOT */
1631 /* the the one used by the C code */
1641 beq cr1,4f /* In place copy is not necessary */
1642 beq 7f /* Protect against 0 count */
1661 * Now flush the cache: note that we must start from a cache aligned
1662 * address. Otherwise we might miss one cache line.
1666 beq 7f /* Always flush prefetch queue in any case */
1674 sync /* Wait for all dcbst to complete on bus */
1680 7: sync /* Wait for all icbi to complete on bus */
1684 * We are done. Do not return, instead branch to second part of board
1685 * initialization, now running from RAM.
1688 addi r0,r10,in_ram - _start + _START_OFFSET
1691 * As IVPR is going to point RAM address,
1692 * Make sure IVOR15 has valid opcode to support debugger
1697 * Re-point the IVPR at RAM
1702 blr /* NEVER RETURNS! */
1707 * Relocation Function, r12 point to got2+0x8000
1709 * Adjust got2 pointers, no need to check for 0, this code
1710 * already puts a few entries in the table.
1712 li r0,__got2_entries@sectoff@l
1713 la r3,GOT(_GOT2_TABLE_)
1714 lwz r11,GOT(_GOT2_TABLE_)
1726 * Now adjust the fixups and the pointers to the fixups
1727 * in case we need to move ourselves again.
1729 li r0,__fixup_entries@sectoff@l
1730 lwz r3,GOT(_FIXUP_TABLE_)
1746 * Now clear BSS segment
1748 lwz r3,GOT(__bss_start)
1749 lwz r4,GOT(__bss_end__)
1762 mr r3,r9 /* Init Data pointer */
1763 mr r4,r10 /* Destination Address */
1766 #ifndef CONFIG_NAND_SPL
1768 * Copy exception vector code to low memory
1771 * r7: source address, r8: end address, r9: target address
1775 mflr r4 /* save link register */
1777 lwz r7,GOT(_start_of_vectors)
1778 lwz r8,GOT(_end_of_vectors)
1780 li r9,0x100 /* reset vector always at 0x100 */
1783 bgelr /* return if r7>=r8 - just in case */
1793 * relocate `hdlr' and `int_return' entries
1795 li r7,.L_CriticalInput - _start + _START_OFFSET
1797 li r7,.L_MachineCheck - _start + _START_OFFSET
1799 li r7,.L_DataStorage - _start + _START_OFFSET
1801 li r7,.L_InstStorage - _start + _START_OFFSET
1803 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1805 li r7,.L_Alignment - _start + _START_OFFSET
1807 li r7,.L_ProgramCheck - _start + _START_OFFSET
1809 li r7,.L_FPUnavailable - _start + _START_OFFSET
1811 li r7,.L_Decrementer - _start + _START_OFFSET
1813 li r7,.L_IntervalTimer - _start + _START_OFFSET
1814 li r8,_end_of_vectors - _start + _START_OFFSET
1817 addi r7,r7,0x100 /* next exception vector */
1821 /* Update IVORs as per relocated vector table address */
1823 mtspr IVOR0,r7 /* 0: Critical input */
1825 mtspr IVOR1,r7 /* 1: Machine check */
1827 mtspr IVOR2,r7 /* 2: Data storage */
1829 mtspr IVOR3,r7 /* 3: Instruction storage */
1831 mtspr IVOR4,r7 /* 4: External interrupt */
1833 mtspr IVOR5,r7 /* 5: Alignment */
1835 mtspr IVOR6,r7 /* 6: Program check */
1837 mtspr IVOR7,r7 /* 7: floating point unavailable */
1839 mtspr IVOR8,r7 /* 8: System call */
1840 /* 9: Auxiliary processor unavailable(unsupported) */
1842 mtspr IVOR10,r7 /* 10: Decrementer */
1844 mtspr IVOR11,r7 /* 11: Interval timer */
1846 mtspr IVOR12,r7 /* 12: Watchdog timer */
1848 mtspr IVOR13,r7 /* 13: Data TLB error */
1850 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1852 mtspr IVOR15,r7 /* 15: Debug */
1857 mtlr r4 /* restore link register */
1860 .globl unlock_ram_in_cache
1861 unlock_ram_in_cache:
1862 /* invalidate the INIT_RAM section */
1863 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1864 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1867 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1870 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1874 /* Invalidate the TLB entries for the cache */
1875 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1876 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1889 mfspr r3,SPRN_L1CFG0
1891 rlwinm r5,r3,9,3 /* Extract cache block size */
1892 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1893 * are currently defined.
1896 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1897 * log2(number of ways)
1899 slw r5,r4,r5 /* r5 = cache block size */
1901 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1902 mulli r7,r7,13 /* An 8-way cache will require 13
1907 /* save off HID0 and set DCFA */
1909 ori r9,r8,HID0_DCFA@l
1916 1: lwz r3,0(r4) /* Load... */
1924 1: dcbf 0,r4 /* ...and flush. */
1937 #include "fixed_ivor.S"
1939 #endif /* !CONFIG_NAND_SPL */