2 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
31 #include <asm-offsets.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
45 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
48 * Set up GOT: Global Offset Table
50 * Use r12 to access the GOT
53 GOT_ENTRY(_GOT2_TABLE_)
54 GOT_ENTRY(_FIXUP_TABLE_)
56 #ifndef CONFIG_NAND_SPL
58 GOT_ENTRY(_start_of_vectors)
59 GOT_ENTRY(_end_of_vectors)
60 GOT_ENTRY(transfer_to_handler)
64 GOT_ENTRY(__bss_end__)
65 GOT_ENTRY(__bss_start)
69 * e500 Startup -- after reset only the last 4KB of the effective
70 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
71 * section is located at THIS LAST page and basically does three
72 * things: clear some registers, set up exception tables and
73 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
74 * continue the boot procedure.
76 * Once the boot rom is mapped by TLB entries we can proceed
77 * with normal startup.
85 /* Enable debug exception */
89 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
92 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
96 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
97 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
102 /* Not a supported revision affected by erratum */
106 1: li r27,1 /* Remember for later that we have the erratum */
107 /* Erratum says set bits 55:60 to 001001 */
118 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
119 /* ISBC uses L2 as stack.
120 * Disable L2 cache here so that u-boot can enable it later
121 * as part of it's normal flow
124 /* Check if L2 is enabled */
125 mfspr r3, SPRN_L2CSR0
127 ori r2, r2, L2CSR0_L2E@l
131 mfspr r3, SPRN_L2CSR0
133 lis r2,(L2CSR0_L2FL)@h
134 ori r2, r2, (L2CSR0_L2FL)@l
141 mfspr r3, SPRN_L2CSR0
145 mfspr r3, SPRN_L2CSR0
147 ori r2, r2, L2CSR0_L2E@l
157 /* clear registers/arrays not reset by hardware */
161 mtspr L1CSR0,r0 /* invalidate d-cache */
162 mtspr L1CSR1,r0 /* invalidate i-cache */
165 mtspr DBSR,r1 /* Clear all valid bits */
168 * Enable L1 Caches early
172 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
173 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
178 /* Enable/invalidate the I-Cache */
179 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
180 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
187 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
188 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
193 andi. r1,r3,L1CSR1_ICE@l
196 /* Enable/invalidate the D-Cache */
197 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
198 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
205 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
206 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
211 andi. r1,r3,L1CSR0_DCE@l
214 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
216 * TLB entry for debuggging in AS1
217 * Create temporary TLB entry in AS0 to handle debug exception
218 * As on debug exception MSR is cleared i.e. Address space is changed
219 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
223 lis r6,FSL_BOOKE_MAS0(1,
224 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
225 ori r6,r6,FSL_BOOKE_MAS0(1,
226 CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
228 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
230 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
231 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
232 * and this window is outside of 4K boot window.
234 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
235 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
237 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
239 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
242 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
243 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
244 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
245 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
246 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
247 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
249 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
250 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
252 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
253 (MAS3_SX|MAS3_SW|MAS3_SR))@h
254 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
255 (MAS3_SX|MAS3_SW|MAS3_SR))@l
258 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
259 * because "nexti" will resize TLB to 4K
261 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
262 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
264 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
265 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
267 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
268 (MAS3_SX|MAS3_SW|MAS3_SR))@h
269 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
270 (MAS3_SX|MAS3_SW|MAS3_SR))@l
281 * Ne need to setup interrupt vector for NAND SPL
282 * because NAND SPL never compiles it.
284 #if !defined(CONFIG_NAND_SPL)
285 /* Setup interrupt vectors */
286 lis r1,CONFIG_SYS_MONITOR_BASE@h
289 lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
290 ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
292 addi r4,r3,CriticalInput - _start + _START_OFFSET
293 mtspr IVOR0,r4 /* 0: Critical input */
294 addi r4,r3,MachineCheck - _start + _START_OFFSET
295 mtspr IVOR1,r4 /* 1: Machine check */
296 addi r4,r3,DataStorage - _start + _START_OFFSET
297 mtspr IVOR2,r4 /* 2: Data storage */
298 addi r4,r3,InstStorage - _start + _START_OFFSET
299 mtspr IVOR3,r4 /* 3: Instruction storage */
300 addi r4,r3,ExtInterrupt - _start + _START_OFFSET
301 mtspr IVOR4,r4 /* 4: External interrupt */
302 addi r4,r3,Alignment - _start + _START_OFFSET
303 mtspr IVOR5,r4 /* 5: Alignment */
304 addi r4,r3,ProgramCheck - _start + _START_OFFSET
305 mtspr IVOR6,r4 /* 6: Program check */
306 addi r4,r3,FPUnavailable - _start + _START_OFFSET
307 mtspr IVOR7,r4 /* 7: floating point unavailable */
308 addi r4,r3,SystemCall - _start + _START_OFFSET
309 mtspr IVOR8,r4 /* 8: System call */
310 /* 9: Auxiliary processor unavailable(unsupported) */
311 addi r4,r3,Decrementer - _start + _START_OFFSET
312 mtspr IVOR10,r4 /* 10: Decrementer */
313 addi r4,r3,IntervalTimer - _start + _START_OFFSET
314 mtspr IVOR11,r4 /* 11: Interval timer */
315 addi r4,r3,WatchdogTimer - _start + _START_OFFSET
316 mtspr IVOR12,r4 /* 12: Watchdog timer */
317 addi r4,r3,DataTLBError - _start + _START_OFFSET
318 mtspr IVOR13,r4 /* 13: Data TLB error */
319 addi r4,r3,InstructionTLBError - _start + _START_OFFSET
320 mtspr IVOR14,r4 /* 14: Instruction TLB error */
321 addi r4,r3,DebugBreakpoint - _start + _START_OFFSET
322 mtspr IVOR15,r4 /* 15: Debug */
325 /* Clear and set up some registers. */
328 mtspr DEC,r0 /* prevent dec exceptions */
329 mttbl r0 /* prevent fit & wdt exceptions */
331 mtspr TSR,r1 /* clear all timer exception status */
332 mtspr TCR,r0 /* disable all */
333 mtspr ESR,r0 /* clear exception syndrome register */
334 mtspr MCSR,r0 /* machine check syndrome register */
335 mtxer r0 /* clear integer exception register */
337 #ifdef CONFIG_SYS_BOOK3E_HV
338 mtspr MAS8,r0 /* make sure MAS8 is clear */
341 /* Enable Time Base and Select Time Base Clock */
342 lis r0,HID0_EMCP@h /* Enable machine check */
343 #if defined(CONFIG_ENABLE_36BIT_PHYS)
344 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
346 #ifndef CONFIG_E500MC
347 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
351 #ifndef CONFIG_E500MC
352 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
355 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
357 /* Set MBDD bit also */
358 ori r0, r0, HID1_MBDD@l
363 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
369 /* Enable Branch Prediction */
370 #if defined(CONFIG_BTB)
371 lis r0,BUCSR_ENABLE@h
372 ori r0,r0,BUCSR_ENABLE@l
376 #if defined(CONFIG_SYS_INIT_DBCR)
379 mtspr DBSR,r1 /* Clear all status bits */
380 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
381 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
385 #ifdef CONFIG_MPC8569
386 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
387 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
389 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
390 * use address space which is more than 12bits, and it must be done in
391 * the 4K boot page. So we set this bit here.
394 /* create a temp mapping TLB0[0] for LBCR */
395 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
396 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
398 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
399 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
401 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
402 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
404 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
405 (MAS3_SX|MAS3_SW|MAS3_SR))@h
406 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
407 (MAS3_SX|MAS3_SW|MAS3_SR))@l
417 /* Set LBCR register */
418 lis r4,CONFIG_SYS_LBCR_ADDR@h
419 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
421 lis r5,CONFIG_SYS_LBC_LBCR@h
422 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
426 /* invalidate this temp TLB */
427 lis r4,CONFIG_SYS_LBC_ADDR@h
428 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
432 #endif /* CONFIG_MPC8569 */
435 * Search for the TLB that covers the code we're executing, and shrink it
436 * so that it covers only this 4K page. That will ensure that any other
437 * TLB we create won't interfere with it. We assume that the TLB exists,
438 * which is why we don't check the Valid bit of MAS1. We also assume
441 * This is necessary, for example, when booting from the on-chip ROM,
442 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
444 bl nexti /* Find our address */
445 nexti: mflr r1 /* R1 = our PC */
447 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
450 tlbsx 0, r1 /* This must succeed */
452 mfspr r14, MAS0 /* Save ESEL for later */
453 rlwinm r14, r14, 16, 0xfff
455 /* Set the size of the TLB to 4KB */
458 andc r3, r3, r2 /* Clear the TSIZE bits */
459 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
460 oris r3, r3, MAS1_IPROT@h
464 * Set the base address of the TLB to our PC. We assume that
465 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
468 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
470 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
475 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
478 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
479 rlwinm r2, r2, 0, ~MAS2_I
483 mtspr MAS2, r2 /* Set the EPN to our PC base address */
488 mtspr MAS3, r2 /* Set the RPN to our PC base address */
495 * Clear out any other TLB entries that may exist, to avoid conflicts.
496 * Our TLB entry is in r14.
498 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
502 mfspr r4, SPRN_TLB1CFG
503 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
508 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
509 cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
510 cror cr0*4+eq, cr0*4+eq, cr1*4+eq
512 rlwinm r5, r3, 16, MAS0_ESEL_MSK
514 beq 2f /* skip the entry we're executing from */
516 oris r5, r5, MAS0_TLBSEL(1)@h
528 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
529 * location is not where we want it. This typically happens on a 36-bit
530 * system, where we want to move CCSR to near the top of 36-bit address space.
532 * To move CCSR, we create two temporary TLBs, one for the old location, and
533 * another for the new location. On CoreNet systems, we also need to create
534 * a special, temporary LAW.
536 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
537 * long-term TLBs, so we use TLB0 here.
539 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
541 #if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
542 #error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
547 * Create a TLB for the new location of CCSR. Register R8 is reserved
548 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
550 lis r8, CONFIG_SYS_CCSRBAR@h
551 ori r8, r8, CONFIG_SYS_CCSRBAR@l
552 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
553 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
554 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
555 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
556 lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
557 ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
558 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
559 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
560 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
561 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
562 #ifdef CONFIG_ENABLE_36BIT_PHYS
563 lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
564 ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
576 * Create a TLB for the current location of CCSR. Register R9 is reserved
577 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
580 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
581 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
582 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
583 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
584 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
585 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
586 #ifdef CONFIG_ENABLE_36BIT_PHYS
587 li r7, 0 /* The default CCSR address is always a 32-bit number */
591 /* MAS1 is the same as above */
599 * We have a TLB for what we think is the current (old) CCSR. Let's
600 * verify that, otherwise we won't be able to move it.
601 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
602 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
605 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
606 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
607 #ifdef CONFIG_FSL_CORENET
608 lwz r1, 4(r9) /* CCSRBARL */
610 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
617 * If the value we read from CCSRBARL is not what we expect, then
618 * enter an infinite loop. This will at least allow a debugger to
619 * halt execution and examine TLBs, etc. There's no point in going
623 bne infinite_debug_loop
625 #ifdef CONFIG_FSL_CORENET
627 #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
628 #define LAW_EN 0x80000000
629 #define LAW_SIZE_4K 0xb
630 #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
631 #define CCSRAR_C 0x80000000 /* Commit */
635 * On CoreNet systems, we create the temporary LAW using a special LAW
636 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
638 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
639 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
640 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
641 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
642 lis r2, CCSRBAR_LAWAR@h
643 ori r2, r2, CCSRBAR_LAWAR@l
645 stw r0, 0xc00(r9) /* LAWBARH0 */
646 stw r1, 0xc04(r9) /* LAWBARL0 */
648 stw r2, 0xc08(r9) /* LAWAR0 */
651 * Read back from LAWAR to ensure the update is complete. e500mc
652 * cores also require an isync.
654 lwz r0, 0xc08(r9) /* LAWAR0 */
658 * Read the current CCSRBARH and CCSRBARL using load word instructions.
659 * Follow this with an isync instruction. This forces any outstanding
660 * accesses to configuration space to completion.
663 lwz r0, 0(r9) /* CCSRBARH */
664 lwz r0, 4(r9) /* CCSRBARL */
668 * Write the new values for CCSRBARH and CCSRBARL to their old
669 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
670 * has a new value written it loads a CCSRBARH shadow register. When
671 * the CCSRBARL is written, the CCSRBARH shadow register contents
672 * along with the CCSRBARL value are loaded into the CCSRBARH and
673 * CCSRBARL registers, respectively. Follow this with a sync
677 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
678 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
679 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
680 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
682 ori r2, r2, CCSRAR_C@l
684 stw r0, 0(r9) /* Write to CCSRBARH */
685 sync /* Make sure we write to CCSRBARH first */
686 stw r1, 4(r9) /* Write to CCSRBARL */
690 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
691 * Follow this with a sync instruction.
696 /* Delete the temporary LAW */
705 #else /* #ifdef CONFIG_FSL_CORENET */
709 * Read the current value of CCSRBAR using a load word instruction
710 * followed by an isync. This forces all accesses to configuration
717 /* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
718 #define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
719 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
721 /* Write the new value to CCSRBAR. */
722 lis r0, CCSRBAR_PHYS_RS12@h
723 ori r0, r0, CCSRBAR_PHYS_RS12@l
728 * The manual says to perform a load of an address that does not
729 * access configuration space or the on-chip SRAM using an existing TLB,
730 * but that doesn't appear to be necessary. We will do the isync,
736 * Read the contents of CCSRBAR from its new location, followed by
742 #endif /* #ifdef CONFIG_FSL_CORENET */
744 /* Delete the temporary TLBs */
746 lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
747 ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
749 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
750 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
758 lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
759 ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
760 lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
761 ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
767 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
769 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
770 #define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
771 #define LAW_SIZE_1M 0x13
772 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
778 * Create a TLB entry for CCSR
780 * We're executing out of TLB1 entry in r14, and that's the only
781 * TLB entry that exists. To allocate some TLB entries for our
782 * own use, flip a bit high enough that we won't flip it again
787 lis r0, MAS0_TLBSEL(1)@h
788 rlwimi r0, r8, 16, MAS0_ESEL_MSK
789 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
790 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
791 lis r7, CONFIG_SYS_CCSRBAR@h
792 ori r7, r7, CONFIG_SYS_CCSRBAR@l
793 ori r2, r7, MAS2_I|MAS2_G
794 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
795 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
796 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
797 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
808 /* Map DCSR temporarily to physical address zero */
810 lis r3, DCSRBAR_LAWAR@h
811 ori r3, r3, DCSRBAR_LAWAR@l
813 stw r0, 0xc00(r7) /* LAWBARH0 */
814 stw r0, 0xc04(r7) /* LAWBARL0 */
816 stw r3, 0xc08(r7) /* LAWAR0 */
818 /* Read back from LAWAR to ensure the update is complete. */
819 lwz r3, 0xc08(r7) /* LAWAR0 */
822 /* Create a TLB entry for DCSR at zero */
825 lis r0, MAS0_TLBSEL(1)@h
826 rlwimi r0, r9, 16, MAS0_ESEL_MSK
827 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
828 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
829 li r6, 0 /* DCSR effective address */
830 ori r2, r6, MAS2_I|MAS2_G
831 li r3, MAS3_SW|MAS3_SR
843 /* enable the timebase */
844 #define CTBENR 0xe2084
846 addis r4, r7, CTBENR@ha
852 .macro erratum_set_ccsr offset value
853 addis r3, r7, \offset@ha
855 addi r3, r3, \offset@l
860 .macro erratum_set_dcsr offset value
861 addis r3, r6, \offset@ha
863 addi r3, r3, \offset@l
868 erratum_set_dcsr 0xb0e08 0xe0201800
869 erratum_set_dcsr 0xb0e18 0xe0201800
870 erratum_set_dcsr 0xb0e38 0xe0400000
871 erratum_set_dcsr 0xb0008 0x00900000
872 erratum_set_dcsr 0xb0e40 0xe00a0000
873 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
874 erratum_set_ccsr 0x10f00 0x415e5000
875 erratum_set_ccsr 0x11f00 0x415e5000
877 /* Make temp mapping uncacheable again, if it was initially */
882 rlwimi r4, r15, 0, MAS2_I
883 rlwimi r4, r15, 0, MAS2_G
890 /* Clear the cache */
891 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
892 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
902 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
903 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
913 /* Remove temporary mappings */
914 lis r0, MAS0_TLBSEL(1)@h
915 rlwimi r0, r9, 16, MAS0_ESEL_MSK
925 stw r3, 0xc08(r7) /* LAWAR0 */
929 lis r0, MAS0_TLBSEL(1)@h
930 rlwimi r0, r8, 16, MAS0_ESEL_MSK
941 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
943 /* Lock two cache lines into I-Cache */
945 mfspr r11, SPRN_L1CSR1
946 rlwinm r11, r11, 0, ~L1CSR1_ICUL
949 mtspr SPRN_L1CSR1, r11
960 mfspr r11, SPRN_L1CSR1
961 3: andi. r11, r11, L1CSR1_ICUL
968 mfspr r11, SPRN_L1CSR1
969 3: andi. r11, r11, L1CSR1_ICUL
974 /* Inside a locked cacheline, wait a while, write, then wait a while */
978 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
979 4: mfspr r5, SPRN_TBRL
986 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
987 4: mfspr r5, SPRN_TBRL
994 * Fill out the rest of this cache line and the next with nops,
995 * to ensure that nothing outside the locked area will be
996 * fetched due to a branch.
1003 mfspr r11, SPRN_L1CSR1
1004 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1007 mtspr SPRN_L1CSR1, r11
1016 create_init_ram_area:
1017 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1018 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1020 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
1021 /* create a temp mapping in AS=1 to the 4M boot window */
1022 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
1023 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
1025 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
1026 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
1028 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
1029 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
1030 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
1031 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1032 /* create a temp mapping in AS = 1 for Flash mapping
1033 * created by PBL for ISBC code
1035 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
1036 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
1038 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
1039 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
1041 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
1042 (MAS3_SX|MAS3_SW|MAS3_SR))@h
1043 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
1044 (MAS3_SX|MAS3_SW|MAS3_SR))@l
1047 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1048 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
1050 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
1051 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
1053 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
1054 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
1056 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
1057 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
1068 /* create a temp mapping in AS=1 to the stack */
1069 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
1070 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
1072 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
1073 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
1075 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
1076 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
1078 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1079 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
1080 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
1081 (MAS3_SX|MAS3_SW|MAS3_SR))@h
1082 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
1083 (MAS3_SX|MAS3_SW|MAS3_SR))@l
1084 li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
1087 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
1088 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
1099 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1100 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
1102 ori r7,r7,switch_as@l
1109 /* L1 DCache is used for initial RAM */
1111 /* Allocate Initial RAM in data cache.
1113 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1114 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1117 /* cache size * 1024 / (2 * L1 line size) */
1118 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
1124 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1127 /* Jump out the last 4K page and continue to 'normal' start */
1128 #ifdef CONFIG_SYS_RAMBOOT
1131 /* Calculate absolute address in FLASH and jump there */
1132 /*--------------------------------------------------------------*/
1133 lis r3,CONFIG_SYS_MONITOR_BASE@h
1134 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1135 addi r3,r3,_start_cont - _start + _START_OFFSET
1143 .long 0x27051956 /* U-BOOT Magic Number */
1144 .globl version_string
1146 .ascii U_BOOT_VERSION_STRING, "\0"
1151 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
1152 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1153 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1155 stw r0,0(r3) /* Terminate Back Chain */
1156 stw r0,+4(r3) /* NULL return address. */
1157 mr r1,r3 /* Transfer to SP(r1) */
1162 /* switch back to AS = 0 */
1163 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1164 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1172 /* NOTREACHED - board_init_f() does not return */
1174 #ifndef CONFIG_NAND_SPL
1175 . = EXC_OFF_SYS_RESET
1176 .globl _start_of_vectors
1179 /* Critical input. */
1180 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1183 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
1185 /* Data Storage exception. */
1186 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1188 /* Instruction Storage exception. */
1189 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1191 /* External Interrupt exception. */
1192 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
1194 /* Alignment exception. */
1197 EXCEPTION_PROLOG(SRR0, SRR1)
1202 addi r3,r1,STACK_FRAME_OVERHEAD
1203 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
1205 /* Program check exception */
1208 EXCEPTION_PROLOG(SRR0, SRR1)
1209 addi r3,r1,STACK_FRAME_OVERHEAD
1210 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
1211 MSR_KERNEL, COPY_EE)
1213 /* No FPU on MPC85xx. This exception is not supposed to happen.
1215 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
1219 * r0 - SYSCALL number
1223 addis r11,r0,0 /* get functions table addr */
1224 ori r11,r11,0 /* Note: this code is patched in trap_init */
1225 addis r12,r0,0 /* get number of functions */
1231 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
1235 li r20,0xd00-4 /* Get stack pointer */
1237 subi r12,r12,12 /* Adjust stack pointer */
1238 li r0,0xc00+_end_back-SystemCall
1239 cmplw 0,r0,r12 /* Check stack overflow */
1250 li r12,0xc00+_back-SystemCall
1258 mfmsr r11 /* Disable interrupts */
1262 SYNC /* Some chip revs need this... */
1266 li r12,0xd00-4 /* restore regs */
1276 addi r12,r12,12 /* Adjust stack pointer */
1284 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1285 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1286 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
1288 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1289 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
1291 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
1293 .globl _end_of_vectors
1297 . = . + (0x100 - ( . & 0xff )) /* align for debug */
1300 * This code finishes saving the registers to the exception frame
1301 * and jumps to the appropriate handler for the exception.
1302 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1304 .globl transfer_to_handler
1305 transfer_to_handler:
1316 andi. r24,r23,0x3f00 /* get vector offset */
1320 mtspr SPRG2,r22 /* r1 is now kernel sp */
1322 lwz r24,0(r23) /* virtual address of handler */
1323 lwz r23,4(r23) /* where to go when done */
1328 rfi /* jump to handler, enable MMU */
1331 mfmsr r28 /* Disable interrupts */
1335 SYNC /* Some chip revs need this... */
1350 lwz r2,_NIP(r1) /* Restore environment */
1361 mfmsr r28 /* Disable interrupts */
1365 SYNC /* Some chip revs need this... */
1380 lwz r2,_NIP(r1) /* Restore environment */
1391 mfmsr r28 /* Disable interrupts */
1395 SYNC /* Some chip revs need this... */
1410 lwz r2,_NIP(r1) /* Restore environment */
1412 mtspr SPRN_MCSRR0,r2
1413 mtspr SPRN_MCSRR1,r0
1424 .globl invalidate_icache
1427 ori r0,r0,L1CSR1_ICFI
1432 blr /* entire I cache */
1434 .globl invalidate_dcache
1437 ori r0,r0,L1CSR0_DCFI
1444 .globl icache_enable
1447 bl invalidate_icache
1457 .globl icache_disable
1461 ori r3,r3,L1CSR1_ICE
1467 .globl icache_status
1470 andi. r3,r3,L1CSR1_ICE
1473 .globl dcache_enable
1476 bl invalidate_dcache
1488 .globl dcache_disable
1492 ori r4,r4,L1CSR0_DCE
1498 .globl dcache_status
1501 andi. r3,r3,L1CSR0_DCE
1524 /*------------------------------------------------------------------------------- */
1526 /* Description: Input 8 bits */
1527 /*------------------------------------------------------------------------------- */
1533 /*------------------------------------------------------------------------------- */
1534 /* Function: out8 */
1535 /* Description: Output 8 bits */
1536 /*------------------------------------------------------------------------------- */
1543 /*------------------------------------------------------------------------------- */
1544 /* Function: out16 */
1545 /* Description: Output 16 bits */
1546 /*------------------------------------------------------------------------------- */
1553 /*------------------------------------------------------------------------------- */
1554 /* Function: out16r */
1555 /* Description: Byte reverse and output 16 bits */
1556 /*------------------------------------------------------------------------------- */
1563 /*------------------------------------------------------------------------------- */
1564 /* Function: out32 */
1565 /* Description: Output 32 bits */
1566 /*------------------------------------------------------------------------------- */
1573 /*------------------------------------------------------------------------------- */
1574 /* Function: out32r */
1575 /* Description: Byte reverse and output 32 bits */
1576 /*------------------------------------------------------------------------------- */
1583 /*------------------------------------------------------------------------------- */
1584 /* Function: in16 */
1585 /* Description: Input 16 bits */
1586 /*------------------------------------------------------------------------------- */
1592 /*------------------------------------------------------------------------------- */
1593 /* Function: in16r */
1594 /* Description: Input 16 bits and byte reverse */
1595 /*------------------------------------------------------------------------------- */
1601 /*------------------------------------------------------------------------------- */
1602 /* Function: in32 */
1603 /* Description: Input 32 bits */
1604 /*------------------------------------------------------------------------------- */
1610 /*------------------------------------------------------------------------------- */
1611 /* Function: in32r */
1612 /* Description: Input 32 bits and byte reverse */
1613 /*------------------------------------------------------------------------------- */
1618 #endif /* !CONFIG_NAND_SPL */
1620 /*------------------------------------------------------------------------------*/
1623 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1631 #ifdef CONFIG_ENABLE_36BIT_PHYS
1635 #ifdef CONFIG_SYS_BOOK3E_HV
1645 * void relocate_code (addr_sp, gd, addr_moni)
1647 * This "function" does not return, instead it continues in RAM
1648 * after relocating the monitor code.
1652 * r5 = length in bytes
1653 * r6 = cachelinesize
1655 .globl relocate_code
1657 mr r1,r3 /* Set new stack pointer */
1658 mr r9,r4 /* Save copy of Init Data pointer */
1659 mr r10,r5 /* Save copy of Destination Address */
1662 mr r3,r5 /* Destination Address */
1663 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1664 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
1665 lwz r5,GOT(__init_end)
1667 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
1672 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1678 /* First our own GOT */
1680 /* the the one used by the C code */
1690 beq cr1,4f /* In place copy is not necessary */
1691 beq 7f /* Protect against 0 count */
1710 * Now flush the cache: note that we must start from a cache aligned
1711 * address. Otherwise we might miss one cache line.
1715 beq 7f /* Always flush prefetch queue in any case */
1723 sync /* Wait for all dcbst to complete on bus */
1729 7: sync /* Wait for all icbi to complete on bus */
1733 * We are done. Do not return, instead branch to second part of board
1734 * initialization, now running from RAM.
1737 addi r0,r10,in_ram - _start + _START_OFFSET
1740 * As IVPR is going to point RAM address,
1741 * Make sure IVOR15 has valid opcode to support debugger
1746 * Re-point the IVPR at RAM
1751 blr /* NEVER RETURNS! */
1756 * Relocation Function, r12 point to got2+0x8000
1758 * Adjust got2 pointers, no need to check for 0, this code
1759 * already puts a few entries in the table.
1761 li r0,__got2_entries@sectoff@l
1762 la r3,GOT(_GOT2_TABLE_)
1763 lwz r11,GOT(_GOT2_TABLE_)
1775 * Now adjust the fixups and the pointers to the fixups
1776 * in case we need to move ourselves again.
1778 li r0,__fixup_entries@sectoff@l
1779 lwz r3,GOT(_FIXUP_TABLE_)
1795 * Now clear BSS segment
1797 lwz r3,GOT(__bss_start)
1798 lwz r4,GOT(__bss_end__)
1811 mr r3,r9 /* Init Data pointer */
1812 mr r4,r10 /* Destination Address */
1815 #ifndef CONFIG_NAND_SPL
1817 * Copy exception vector code to low memory
1820 * r7: source address, r8: end address, r9: target address
1824 mflr r4 /* save link register */
1826 lwz r7,GOT(_start_of_vectors)
1827 lwz r8,GOT(_end_of_vectors)
1829 li r9,0x100 /* reset vector always at 0x100 */
1832 bgelr /* return if r7>=r8 - just in case */
1842 * relocate `hdlr' and `int_return' entries
1844 li r7,.L_CriticalInput - _start + _START_OFFSET
1846 li r7,.L_MachineCheck - _start + _START_OFFSET
1848 li r7,.L_DataStorage - _start + _START_OFFSET
1850 li r7,.L_InstStorage - _start + _START_OFFSET
1852 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1854 li r7,.L_Alignment - _start + _START_OFFSET
1856 li r7,.L_ProgramCheck - _start + _START_OFFSET
1858 li r7,.L_FPUnavailable - _start + _START_OFFSET
1860 li r7,.L_Decrementer - _start + _START_OFFSET
1862 li r7,.L_IntervalTimer - _start + _START_OFFSET
1863 li r8,_end_of_vectors - _start + _START_OFFSET
1866 addi r7,r7,0x100 /* next exception vector */
1870 /* Update IVORs as per relocated vector table address */
1872 mtspr IVOR0,r7 /* 0: Critical input */
1874 mtspr IVOR1,r7 /* 1: Machine check */
1876 mtspr IVOR2,r7 /* 2: Data storage */
1878 mtspr IVOR3,r7 /* 3: Instruction storage */
1880 mtspr IVOR4,r7 /* 4: External interrupt */
1882 mtspr IVOR5,r7 /* 5: Alignment */
1884 mtspr IVOR6,r7 /* 6: Program check */
1886 mtspr IVOR7,r7 /* 7: floating point unavailable */
1888 mtspr IVOR8,r7 /* 8: System call */
1889 /* 9: Auxiliary processor unavailable(unsupported) */
1891 mtspr IVOR10,r7 /* 10: Decrementer */
1893 mtspr IVOR11,r7 /* 11: Interval timer */
1895 mtspr IVOR12,r7 /* 12: Watchdog timer */
1897 mtspr IVOR13,r7 /* 13: Data TLB error */
1899 mtspr IVOR14,r7 /* 14: Instruction TLB error */
1901 mtspr IVOR15,r7 /* 15: Debug */
1906 mtlr r4 /* restore link register */
1909 .globl unlock_ram_in_cache
1910 unlock_ram_in_cache:
1911 /* invalidate the INIT_RAM section */
1912 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1913 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1916 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1919 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1923 /* Invalidate the TLB entries for the cache */
1924 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1925 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1938 mfspr r3,SPRN_L1CFG0
1940 rlwinm r5,r3,9,3 /* Extract cache block size */
1941 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1942 * are currently defined.
1945 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1946 * log2(number of ways)
1948 slw r5,r4,r5 /* r5 = cache block size */
1950 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1951 mulli r7,r7,13 /* An 8-way cache will require 13
1956 /* save off HID0 and set DCFA */
1958 ori r9,r8,HID0_DCFA@l
1965 1: lwz r3,0(r4) /* Load... */
1973 1: dcbf 0,r4 /* ...and flush. */
1986 #include "fixed_ivor.S"
1988 #endif /* !CONFIG_NAND_SPL */