arch/powerpc/cpu/mpc85xx/speed.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2003 Motorola Inc.
   6  * Xianghua Xiao, (X.Xiao@motorola.com)
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  */
  11
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <ppc_asm.tmpl>
  15 #include <asm/global_data.h>
  16 #include <linux/compiler.h>
  17 #include <asm/processor.h>
  18 #include <asm/io.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22
  23 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
  24 #define CONFIG_SYS_FSL_NUM_CC_PLLS      6
  25 #endif
  26 /* --------------------------------------------------------------- */
  27
  28 void get_sys_info(sys_info_t *sys_info)
  29 {
  30         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  31 #ifdef CONFIG_FSL_CORENET
  32         volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  33         unsigned int cpu;
  34 #ifdef CONFIG_HETROGENOUS_CLUSTERS
  35         unsigned int dsp_cpu;
  36         uint rcw_tmp1, rcw_tmp2;
  37 #endif
  38 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  39         int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  40 #endif
  41         __maybe_unused u32 svr;
  42
  43         const u8 core_cplx_PLL[16] = {
  44                 [ 0] = 0,       /* CC1 PPL / 1 */
  45                 [ 1] = 0,       /* CC1 PPL / 2 */
  46                 [ 2] = 0,       /* CC1 PPL / 4 */
  47                 [ 4] = 1,       /* CC2 PPL / 1 */
  48                 [ 5] = 1,       /* CC2 PPL / 2 */
  49                 [ 6] = 1,       /* CC2 PPL / 4 */
  50                 [ 8] = 2,       /* CC3 PPL / 1 */
  51                 [ 9] = 2,       /* CC3 PPL / 2 */
  52                 [10] = 2,       /* CC3 PPL / 4 */
  53                 [12] = 3,       /* CC4 PPL / 1 */
  54                 [13] = 3,       /* CC4 PPL / 2 */
  55                 [14] = 3,       /* CC4 PPL / 4 */
  56         };
  57
  58         const u8 core_cplx_pll_div[16] = {
  59                 [ 0] = 1,       /* CC1 PPL / 1 */
  60                 [ 1] = 2,       /* CC1 PPL / 2 */
  61                 [ 2] = 4,       /* CC1 PPL / 4 */
  62                 [ 4] = 1,       /* CC2 PPL / 1 */
  63                 [ 5] = 2,       /* CC2 PPL / 2 */
  64                 [ 6] = 4,       /* CC2 PPL / 4 */
  65                 [ 8] = 1,       /* CC3 PPL / 1 */
  66                 [ 9] = 2,       /* CC3 PPL / 2 */
  67                 [10] = 4,       /* CC3 PPL / 4 */
  68                 [12] = 1,       /* CC4 PPL / 1 */
  69                 [13] = 2,       /* CC4 PPL / 2 */
  70                 [14] = 4,       /* CC4 PPL / 4 */
  71         };
  72         uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  73 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  74         uint rcw_tmp;
  75 #endif
  76         uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  77         unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  78         uint mem_pll_rat;
  79
  80         sys_info->freq_systembus = sysclk;
  81 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  82         uint ddr_refclk_sel;
  83         unsigned int porsr1_sys_clk;
  84         porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
  85                                                 & FSL_DCFG_PORSR1_SYSCLK_MASK;
  86         if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
  87                 sys_info->diff_sysclk = 1;
  88         else
  89                 sys_info->diff_sysclk = 0;
  90
  91         /*
  92          * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
  93          * are driven by separate DDR Refclock or single source
  94          * differential clock.
  95          */
  96         ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
  97                       FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
  98                       FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
  99         /*
 100          * For single source clocking, both ddrclock and sysclock
 101          * are driven by differential sysclock.
 102          */
 103         if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
 104                 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
 105         else
 106 #endif
 107 #ifdef CONFIG_DDR_CLK_FREQ
 108                 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 109 #else
 110                 sys_info->freq_ddrbus = sysclk;
 111 #endif
 112
 113         sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 114         mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
 115                         FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
 116                         & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 117 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 118         if (mem_pll_rat == 0) {
 119                 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
 120                         FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
 121                         FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 122         }
 123 #endif
 124         /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
 125          * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
 126          * it uses 6.
 127          * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
 128          */
 129 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
 130         defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 131         svr = get_svr();
 132         switch (SVR_SOC_VER(svr)) {
 133         case SVR_T4240:
 134         case SVR_T4160:
 135         case SVR_T4120:
 136         case SVR_T4080:
 137                 if (SVR_MAJ(svr) >= 2)
 138                         mem_pll_rat *= 2;
 139                 break;
 140         case SVR_T2080:
 141         case SVR_T2081:
 142                 if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
 143                         mem_pll_rat *= 2;
 144                 break;
 145         default:
 146                 break;
 147         }
 148 #endif
 149         if (mem_pll_rat > 2)
 150                 sys_info->freq_ddrbus *= mem_pll_rat;
 151         else
 152                 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
 153
 154         for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 155                 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
 156                 if (ratio[i] > 4)
 157                         freq_c_pll[i] = sysclk * ratio[i];
 158                 else
 159                         freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 160         }
 161
 162 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 163         /*
 164          * As per CHASSIS2 architeture total 12 clusters are posible and
 165          * Each cluster has up to 4 cores, sharing the same PLL selection.
 166          * The cluster clock assignment is SoC defined.
 167          *
 168          * Total 4 clock groups are possible with 3 PLLs each.
 169          * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
 170          * clock group B has 3, 4, 6 and so on.
 171          *
 172          * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
 173          * depends upon the SoC architeture. Same applies to other
 174          * clock groups and clusters.
 175          *
 176          */
 177         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 178                 int cluster = fsl_qoriq_core_to_cluster(cpu);
 179                 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 180                                 & 0xf;
 181                 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 182                 cplx_pll += cc_group[cluster] - 1;
 183                 sys_info->freq_processor[cpu] =
 184                          freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 185         }
 186
 187 #ifdef CONFIG_HETROGENOUS_CLUSTERS
 188         for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
 189                 int dsp_cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
 190                 u32 c_pll_sel = (in_be32
 191                                 (&clk->clkcsr[dsp_cluster].clkcncsr) >> 27)
 192                                 & 0xf;
 193                 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 194                 cplx_pll += cc_group[dsp_cluster] - 1;
 195                 sys_info->freq_processor_dsp[dsp_cpu] =
 196                          freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 197         }
 198 #endif
 199
 200 #if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
 201         defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 202 #define FM1_CLK_SEL     0xe0000000
 203 #define FM1_CLK_SHIFT   29
 204 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 205 #define FM1_CLK_SEL     0x00000007
 206 #define FM1_CLK_SHIFT   0
 207 #else
 208 #define PME_CLK_SEL     0xe0000000
 209 #define PME_CLK_SHIFT   29
 210 #define FM1_CLK_SEL     0x1c000000
 211 #define FM1_CLK_SHIFT   26
 212 #endif
 213 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
 214 #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 215         rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
 216 #else
 217         rcw_tmp = in_be32(&gur->rcwsr[7]);
 218 #endif
 219 #endif
 220
 221 #ifdef CONFIG_SYS_DPAA_PME
 222 #ifndef CONFIG_PME_PLAT_CLK_DIV
 223         switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
 224         case 1:
 225                 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
 226                 break;
 227         case 2:
 228                 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
 229                 break;
 230         case 3:
 231                 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
 232                 break;
 233         case 4:
 234                 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
 235                 break;
 236         case 6:
 237                 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
 238                 break;
 239         case 7:
 240                 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
 241                 break;
 242         default:
 243                 printf("Error: Unknown PME clock select!\n");
 244         case 0:
 245                 sys_info->freq_pme = sys_info->freq_systembus / 2;
 246                 break;
 247
 248         }
 249 #else
 250         sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
 251
 252 #endif
 253 #endif
 254
 255 #ifdef CONFIG_SYS_DPAA_QBMAN
 256 #ifndef CONFIG_QBMAN_CLK_DIV
 257 #define CONFIG_QBMAN_CLK_DIV    2
 258 #endif
 259         sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
 260 #endif
 261
 262 #if defined(CONFIG_SYS_MAPLE)
 263 #define CPRI_CLK_SEL            0x1C000000
 264 #define CPRI_CLK_SHIFT          26
 265 #define CPRI_ALT_CLK_SEL        0x00007000
 266 #define CPRI_ALT_CLK_SHIFT      12
 267
 268         rcw_tmp1 = in_be32(&gur->rcwsr[7]);     /* Reading RCW bits: 224-255*/
 269         rcw_tmp2 = in_be32(&gur->rcwsr[15]);    /* Reading RCW bits: 480-511*/
 270         /* For MAPLE and CPRI frequency */
 271         switch ((rcw_tmp1 & CPRI_CLK_SEL) >> CPRI_CLK_SHIFT) {
 272         case 1:
 273                 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK];
 274                 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK];
 275                 break;
 276         case 2:
 277                 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
 278                 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 2;
 279                 break;
 280         case 3:
 281                 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
 282                 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 3;
 283                 break;
 284         case 4:
 285                 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
 286                 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK] / 4;
 287                 break;
 288         case 5:
 289                 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
 290                                         >> CPRI_ALT_CLK_SHIFT) == 6) {
 291                         sys_info->freq_maple =
 292                                 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
 293                         sys_info->freq_cpri =
 294                                 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 2;
 295                 }
 296                 if (((rcw_tmp2 & CPRI_ALT_CLK_SEL)
 297                                         >> CPRI_ALT_CLK_SHIFT) == 7) {
 298                         sys_info->freq_maple =
 299                                 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
 300                         sys_info->freq_cpri =
 301                                 freq_c_pll[CONFIG_SYS_CPRI_CLK - 2] / 3;
 302                 }
 303                 break;
 304         case 6:
 305                 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
 306                 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 2;
 307                 break;
 308         case 7:
 309                 sys_info->freq_maple = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
 310                 sys_info->freq_cpri = freq_c_pll[CONFIG_SYS_CPRI_CLK + 1] / 3;
 311                 break;
 312         default:
 313                 printf("Error: Unknown MAPLE/CPRI clock select!\n");
 314         }
 315
 316         /* For MAPLE ULB and eTVPE frequencies */
 317 #define ULB_CLK_SEL             0x00000038
 318 #define ULB_CLK_SHIFT           3
 319 #define ETVPE_CLK_SEL           0x00000007
 320 #define ETVPE_CLK_SHIFT         0
 321
 322         switch ((rcw_tmp2 & ULB_CLK_SEL) >> ULB_CLK_SHIFT) {
 323         case 1:
 324                 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK];
 325                 break;
 326         case 2:
 327                 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 2;
 328                 break;
 329         case 3:
 330                 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 3;
 331                 break;
 332         case 4:
 333                 sys_info->freq_maple_ulb = freq_c_pll[CONFIG_SYS_ULB_CLK] / 4;
 334                 break;
 335         case 5:
 336                 sys_info->freq_maple_ulb = sys_info->freq_systembus;
 337                 break;
 338         case 6:
 339                 sys_info->freq_maple_ulb =
 340                         freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 2;
 341                 break;
 342         case 7:
 343                 sys_info->freq_maple_ulb =
 344                         freq_c_pll[CONFIG_SYS_ULB_CLK - 1] / 3;
 345                 break;
 346         default:
 347                 printf("Error: Unknown MAPLE ULB clock select!\n");
 348         }
 349
 350         switch ((rcw_tmp2 & ETVPE_CLK_SEL) >> ETVPE_CLK_SHIFT) {
 351         case 1:
 352                 sys_info->freq_maple_etvpe = freq_c_pll[CONFIG_SYS_ETVPE_CLK];
 353                 break;
 354         case 2:
 355                 sys_info->freq_maple_etvpe =
 356                         freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 2;
 357                 break;
 358         case 3:
 359                 sys_info->freq_maple_etvpe =
 360                         freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 3;
 361                 break;
 362         case 4:
 363                 sys_info->freq_maple_etvpe =
 364                         freq_c_pll[CONFIG_SYS_ETVPE_CLK] / 4;
 365                 break;
 366         case 5:
 367                 sys_info->freq_maple_etvpe = sys_info->freq_systembus;
 368                 break;
 369         case 6:
 370                 sys_info->freq_maple_etvpe =
 371                         freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 2;
 372                 break;
 373         case 7:
 374                 sys_info->freq_maple_etvpe =
 375                         freq_c_pll[CONFIG_SYS_ETVPE_CLK - 1] / 3;
 376                 break;
 377         default:
 378                 printf("Error: Unknown MAPLE eTVPE clock select!\n");
 379         }
 380
 381 #endif
 382
 383 #ifdef CONFIG_SYS_DPAA_FMAN
 384 #ifndef CONFIG_FM_PLAT_CLK_DIV
 385         switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
 386         case 1:
 387                 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
 388                 break;
 389         case 2:
 390                 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
 391                 break;
 392         case 3:
 393                 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
 394                 break;
 395         case 4:
 396                 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
 397                 break;
 398         case 5:
 399                 sys_info->freq_fman[0] = sys_info->freq_systembus;
 400                 break;
 401         case 6:
 402                 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
 403                 break;
 404         case 7:
 405                 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
 406                 break;
 407         default:
 408                 printf("Error: Unknown FMan1 clock select!\n");
 409         case 0:
 410                 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 411                 break;
 412         }
 413 #if (CONFIG_SYS_NUM_FMAN) == 2
 414 #ifdef CONFIG_SYS_FM2_CLK
 415 #define FM2_CLK_SEL     0x00000038
 416 #define FM2_CLK_SHIFT   3
 417         rcw_tmp = in_be32(&gur->rcwsr[15]);
 418         switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
 419         case 1:
 420                 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
 421                 break;
 422         case 2:
 423                 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
 424                 break;
 425         case 3:
 426                 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
 427                 break;
 428         case 4:
 429                 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
 430                 break;
 431         case 5:
 432                 sys_info->freq_fman[1] = sys_info->freq_systembus;
 433                 break;
 434         case 6:
 435                 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
 436                 break;
 437         case 7:
 438                 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
 439                 break;
 440         default:
 441                 printf("Error: Unknown FMan2 clock select!\n");
 442         case 0:
 443                 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 444                 break;
 445         }
 446 #endif
 447 #endif  /* CONFIG_SYS_NUM_FMAN == 2 */
 448 #else
 449         sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
 450 #endif
 451 #endif
 452
 453 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 454
 455         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 456                 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
 457                                 & 0xf;
 458                 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
 459
 460                 sys_info->freq_processor[cpu] =
 461                          freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 462         }
 463 #define PME_CLK_SEL     0x80000000
 464 #define FM1_CLK_SEL     0x40000000
 465 #define FM2_CLK_SEL     0x20000000
 466 #define HWA_ASYNC_DIV   0x04000000
 467 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 468 #define HWA_CC_PLL      1
 469 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
 470 #define HWA_CC_PLL      2
 471 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 472 #define HWA_CC_PLL      2
 473 #else
 474 #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
 475 #endif
 476         rcw_tmp = in_be32(&gur->rcwsr[7]);
 477
 478 #ifdef CONFIG_SYS_DPAA_PME
 479         if (rcw_tmp & PME_CLK_SEL) {
 480                 if (rcw_tmp & HWA_ASYNC_DIV)
 481                         sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
 482                 else
 483                         sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
 484         } else {
 485                 sys_info->freq_pme = sys_info->freq_systembus / 2;
 486         }
 487 #endif
 488
 489 #ifdef CONFIG_SYS_DPAA_FMAN
 490         if (rcw_tmp & FM1_CLK_SEL) {
 491                 if (rcw_tmp & HWA_ASYNC_DIV)
 492                         sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
 493                 else
 494                         sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
 495         } else {
 496                 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
 497         }
 498 #if (CONFIG_SYS_NUM_FMAN) == 2
 499         if (rcw_tmp & FM2_CLK_SEL) {
 500                 if (rcw_tmp & HWA_ASYNC_DIV)
 501                         sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
 502                 else
 503                         sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
 504         } else {
 505                 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
 506         }
 507 #endif
 508 #endif
 509
 510 #ifdef CONFIG_SYS_DPAA_QBMAN
 511         sys_info->freq_qman = sys_info->freq_systembus / 2;
 512 #endif
 513
 514 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 515
 516 #ifdef CONFIG_U_QE
 517         sys_info->freq_qe =  sys_info->freq_systembus / 2;
 518 #endif
 519
 520 #else /* CONFIG_FSL_CORENET */
 521         uint plat_ratio, e500_ratio, half_freq_systembus;
 522         int i;
 523 #ifdef CONFIG_QE
 524         __maybe_unused u32 qe_ratio;
 525 #endif
 526
 527         plat_ratio = (gur->porpllsr) & 0x0000003e;
 528         plat_ratio >>= 1;
 529         sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
 530
 531         /* Divide before multiply to avoid integer
 532          * overflow for processor speeds above 2GHz */
 533         half_freq_systembus = sys_info->freq_systembus/2;
 534         for (i = 0; i < cpu_numcores(); i++) {
 535                 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
 536                 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
 537         }
 538
 539         /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
 540         sys_info->freq_ddrbus = sys_info->freq_systembus;
 541
 542 #ifdef CONFIG_DDR_CLK_FREQ
 543         {
 544                 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 545                         >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 546                 if (ddr_ratio != 0x7)
 547                         sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
 548         }
 549 #endif
 550
 551 #ifdef CONFIG_QE
 552 #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 553         sys_info->freq_qe =  sys_info->freq_systembus;
 554 #else
 555         qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 556                         >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 557         sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
 558 #endif
 559 #endif
 560
 561 #ifdef CONFIG_SYS_DPAA_FMAN
 562                 sys_info->freq_fman[0] = sys_info->freq_systembus;
 563 #endif
 564
 565 #endif /* CONFIG_FSL_CORENET */
 566
 567 #if defined(CONFIG_FSL_LBC)
 568         sys_info->freq_localbus = sys_info->freq_systembus /
 569                                                 CONFIG_SYS_FSL_LBC_CLK_DIV;
 570 #endif
 571
 572 #if defined(CONFIG_FSL_IFC)
 573         sys_info->freq_localbus = sys_info->freq_systembus /
 574                                                 CONFIG_SYS_FSL_IFC_CLK_DIV;
 575 #endif
 576 }
 577
 578 int get_clocks(void)
 579 {
 580         sys_info_t sys_info;
 581 #ifdef CONFIG_ARCH_MPC8544
 582         volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 583 #endif
 584 #if defined(CONFIG_CPM2)
 585         volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
 586         uint sccr, dfbrg;
 587
 588         /* set VCO = 4 * BRG */
 589         cpm->im_cpm_intctl.sccr &= 0xfffffffc;
 590         sccr = cpm->im_cpm_intctl.sccr;
 591         dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 592 #endif
 593         get_sys_info (&sys_info);
 594         gd->cpu_clk = sys_info.freq_processor[0];
 595         gd->bus_clk = sys_info.freq_systembus;
 596         gd->mem_clk = sys_info.freq_ddrbus;
 597         gd->arch.lbc_clk = sys_info.freq_localbus;
 598
 599 #ifdef CONFIG_QE
 600         gd->arch.qe_clk = sys_info.freq_qe;
 601         gd->arch.brg_clk = gd->arch.qe_clk / 2;
 602 #endif
 603         /*
 604          * The base clock for I2C depends on the actual SOC.  Unfortunately,
 605          * there is no pattern that can be used to determine the frequency, so
 606          * the only choice is to look up the actual SOC number and use the value
 607          * for that SOC. This information is taken from application note
 608          * AN2919.
 609          */
 610 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
 611         defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
 612         defined(CONFIG_ARCH_P1022)
 613         gd->arch.i2c1_clk = sys_info.freq_systembus;
 614 #elif defined(CONFIG_ARCH_MPC8544)
 615         /*
 616          * On the 8544, the I2C clock is the same as the SEC clock.  This can be
 617          * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
 618          * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
 619          * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
 620          * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 621          */
 622         if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
 623                 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
 624         else
 625                 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
 626 #else
 627         /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 628         gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
 629 #endif
 630         gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 631
 632 #if defined(CONFIG_FSL_ESDHC)
 633 #if defined(CONFIG_ARCH_P1010)
 634         gd->arch.sdhc_clk = gd->bus_clk;
 635 #else
 636         gd->arch.sdhc_clk = gd->bus_clk / 2;
 637 #endif
 638 #endif /* defined(CONFIG_FSL_ESDHC) */
 639
 640 #if defined(CONFIG_CPM2)
 641         gd->arch.vco_out = 2*sys_info.freq_systembus;
 642         gd->arch.cpm_clk = gd->arch.vco_out / 2;
 643         gd->arch.scc_clk = gd->arch.vco_out / 4;
 644         gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 645 #endif
 646
 647         if(gd->cpu_clk != 0) return (0);
 648         else return (1);
 649 }
 650
 651
 652 /********************************************
 653  * get_bus_freq
 654  * return system bus freq in Hz
 655  *********************************************/
 656 ulong get_bus_freq(ulong dummy)
 657 {
 658         return gd->bus_clk;
 659 }
 660
 661 /********************************************
 662  * get_ddr_freq
 663  * return ddr bus freq in Hz
 664  *********************************************/
 665 ulong get_ddr_freq (ulong dummy)
 666 {
 667         return gd->mem_clk;
 668 }