2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
13 #include <ppc_asm.tmpl>
16 #include <asm/cache.h>
19 /* To boot secondary cpus, we need a place for them to start up.
20 * Normally, they start at 0xfffffffc, but that's usually the
21 * firmware, and we don't want to have to run the firmware again.
22 * Instead, the primary cpu will set the BPTR to point here to
23 * this page. We then set up the core, and head to
24 * start_secondary. Note that this means that the code below
25 * must never exceed 1023 instructions (the branch at the end
26 * would then be the 1024th).
28 .globl __secondary_start_page
30 __secondary_start_page:
31 /* First do some preliminary setup */
32 lis r3, HID0_EMCP@h /* enable machine check */
34 ori r3,r3,HID0_TBEN@l /* enable Timebase */
36 #ifdef CONFIG_PHYS_64BIT
37 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
42 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
45 cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */
47 /* Set MBDD bit also */
48 ori r3, r3, HID1_MBDD@l
53 #ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
59 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
62 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
66 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
67 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
72 /* Not a supported revision affected by erratum */
75 1: /* Erratum says set bits 55:60 to 001001 */
86 /* Enable branch prediction */
88 ori r3,r3,BUCSR_ENABLE@l
96 /* Enable/invalidate the I-Cache */
97 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
98 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
105 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
106 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
111 andi. r1,r3,L1CSR1_ICE@l
114 /* Enable/invalidate the D-Cache */
115 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
116 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
123 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
124 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
129 andi. r1,r3,L1CSR0_DCE@l
132 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
134 /* get our PIR to figure out our table entry */
135 lis r3,toreset(__spin_table_addr)@h
136 ori r3,r3,toreset(__spin_table_addr)@l
140 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
142 * PIR definition for Chassis 2
143 * 0-17 Reserved (logic 0s)
144 * 18-19 CHIP_ID, 2'b00 - SoC 1
145 * all others - reserved
146 * 20-24 CLUSTER_ID 5'b00000 - CCM 1
147 * all others - reserved
148 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
152 * 27-28 CORE_ID 2'b00 - core 0
156 * 29-31 THREAD_ID 3'b000 - thread 0
159 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
160 * and clusters by 0x20.
162 * We renumber PIR so that all threads in the system are consecutive.
165 rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
166 srwi r10,r0,5 /* r10 = cluster */
168 mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
169 add r5,r5,r8 /* for spin table index */
170 mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
171 #elif defined(CONFIG_E500MC)
172 rlwinm r4,r0,27,27,31
180 * r10 has the base address for the entry.
181 * we cannot access it yet before setting up a new TLB
183 slwi r8,r5,6 /* spin table is padded to 64 byte */
186 mtspr SPRN_PIR,r4 /* write to PIR register */
188 #ifdef CONFIG_SYS_CACHE_STASHING
189 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
195 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
196 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
198 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
199 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
200 * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
203 rlwinm r6,r3,24,~0x800 /* clear E bit */
206 ori r5,r5,SVR_P4080@l
215 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
216 lis r3,toreset(enable_cpu_a011_workaround)@ha
217 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
222 oris r3,r3,(L1CSR2_DCWS)@h
227 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
229 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
230 * write shadow mode. This code should run after other code setting
234 andis. r3,r3,(L1CSR2_DCWS)@h
236 mfspr r3, SPRN_HDBCR0
238 mtspr SPRN_HDBCR0, r3
242 #ifdef CONFIG_BACKSIDE_L2_CACHE
243 /* skip L2 setup on P2040/P2040E as they have no L2 */
245 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
248 ori r3,r3,SVR_P2040@l
252 /* Enable/invalidate the L2 cache */
254 lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
255 ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
262 #ifdef CONFIG_SYS_CACHE_STASHING
263 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
268 lis r3,CONFIG_SYS_INIT_L2CSR0@h
269 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
274 andis. r1,r3,L2CSR0_L2E@h
278 /* setup mapping for the spin table, WIMGE=0b00100 */
279 lis r13,toreset(__spin_table_addr)@h
280 ori r13,r13,toreset(__spin_table_addr)@l
283 rlwinm r13,r13,0,0,19
285 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
287 lis r11,(MAS1_VALID|MAS1_IPROT)@h
288 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
290 oris r11,r13,(MAS2_M|MAS2_G)@h
291 ori r11,r13,(MAS2_M|MAS2_G)@l
293 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
294 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
301 * __bootpg_addr has the address of __second_half_boot_page
302 * jump there in AS=1 space with cache enabled
304 lis r13,toreset(__bootpg_addr)@h
305 ori r13,r13,toreset(__bootpg_addr)@l
309 ori r12,r13,MSR_IS|MSR_DS@l
314 * Allocate some space for the SDRAM address of the bootpg.
315 * This variable has to be in the boot page so that it can
316 * be accessed by secondary cores when they come out of reset.
318 .align L1_CACHE_SHIFT
323 .global __spin_table_addr
328 * This variable is set by cpu_init_r() after parsing hwconfig
329 * to enable workaround for erratum NMG_CPU_A011.
331 .align L1_CACHE_SHIFT
332 .global enable_cpu_a011_workaround
333 enable_cpu_a011_workaround:
336 /* Fill in the empty space. The actual reset vector is
337 * the last word of the page */
338 __secondary_start_code_end:
339 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
340 __secondary_reset_vector:
341 b __secondary_start_page
344 /* this is a separated page for the spin table and cacheable boot code */
345 .align L1_CACHE_SHIFT
346 .global __second_half_boot_page
347 __second_half_boot_page:
348 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
349 lis r3,(spin_table_compat - __second_half_boot_page)@h
350 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
351 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
355 #define ENTRY_ADDR_UPPER 0
356 #define ENTRY_ADDR_LOWER 4
357 #define ENTRY_R3_UPPER 8
358 #define ENTRY_R3_LOWER 12
359 #define ENTRY_RESV 16
361 #define ENTRY_SIZE 64
364 * r10 has the base address of the spin table.
365 * spin table is defined as
367 * uint64_t entry_addr;
372 * we pad this struct to 64 bytes so each entry is in its own cacheline
377 stw r3,ENTRY_ADDR_UPPER(r10)
378 stw r3,ENTRY_R3_UPPER(r10)
379 stw r4,ENTRY_R3_LOWER(r10)
380 stw r3,ENTRY_RESV(r10)
381 stw r4,ENTRY_PIR(r10)
383 stw r8,ENTRY_ADDR_LOWER(r10)
385 /* spin waiting for addr */
388 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
389 * memory. Old OS may not work with this change. A patch is waiting to be
390 * accepted for Linux kernel. Other OS needs similar fix to spin table.
391 * For OSes with old spin table code, we can enable this temporary fix by
392 * setting environmental variable "spin_table_compat". For new OSes, set
393 * "spin_table_compat=no". After Linux is fixed, we can remove this macro
394 * and related code. For now, it is enabled by default.
396 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
403 lwz r4,ENTRY_ADDR_LOWER(r10)
408 /* get the upper bits of the addr */
409 lwz r11,ENTRY_ADDR_UPPER(r10)
411 /* setup branch addr */
414 /* mark the entry as released */
416 stw r8,ENTRY_ADDR_LOWER(r10)
418 /* mask by ~64M to setup our tlb we will jump to */
422 * setup r3, r4, r5, r6, r7, r8, r9
423 * r3 contains the value to put in the r3 register at secondary cpu
424 * entry. The high 32-bits are ignored on 32-bit chip implementations.
425 * 64-bit chip implementations however shall load all 64-bits
427 #ifdef CONFIG_SYS_PPC64
428 ld r3,ENTRY_R3_UPPER(r10)
430 lwz r3,ENTRY_R3_LOWER(r10)
435 lis r7,(64*1024*1024)@h
439 /* load up the pir */
440 lwz r0,ENTRY_PIR(r10)
443 stw r0,ENTRY_PIR(r10)
447 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
448 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
449 * second mapping that maps addr 1:1 for 64M, and then we jump to
452 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
454 lis r10,(MAS1_VALID|MAS1_IPROT)@h
455 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
457 /* WIMGE = 0b00000 for now */
459 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
461 #ifdef CONFIG_ENABLE_36BIT_PHYS
466 /* Now we have another mapping for this page, so we jump to that
476 .space CONFIG_MAX_CPUS*ENTRY_SIZE
478 #ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
479 .align L1_CACHE_SHIFT
480 .global spin_table_compat
487 .space 4096 - (__spin_table_end - __spin_table)