2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/fsl_serdes.h>
9 #include <asm/processor.h>
11 #include "fsl_corenet_serdes.h"
13 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14 [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
15 NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
16 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
17 [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
18 NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
19 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
20 [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
21 PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
22 SATA2, NONE, NONE, NONE, NONE, },
23 [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
24 PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
25 XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
26 [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
27 PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
28 PCIE3, NONE, NONE, NONE, NONE, },
29 [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
30 SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
31 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
32 [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
33 PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
34 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
36 [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
37 SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
39 [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
40 SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
41 XAUI_FM1, NONE, NONE, NONE, NONE, },
42 [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
43 PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
44 NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
45 [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
46 SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
47 NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
48 [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
49 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
50 SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
53 enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
55 enum srds_prtcl prtcl;
57 u32 ver = SVR_SOC_VER(svr);
59 if (!serdes_lane_enabled(lane))
62 prtcl = serdes_cfg_tbl[cfg][lane];
64 /* P2040[e] does not support XAUI */
65 if (ver == SVR_P2040 && prtcl == XAUI_FM1)
71 int is_serdes_prtcl_valid(u32 prtcl)
75 u32 ver = SVR_SOC_VER(svr);
77 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
80 /* P2040[e] does not support XAUI */
81 if (ver == SVR_P2040 && prtcl == XAUI_FM1)
84 for (i = 0; i < SRDS_MAX_LANES; i++) {
85 if (serdes_cfg_tbl[prtcl][i] != NONE)