2 * Copyright 2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/immap_85xx.h>
27 #include <asm/fsl_serdes.h>
29 #define SRDS1_MAX_LANES 8
30 #define SRDS2_MAX_LANES 4
32 static u32 serdes1_prtcl_map, serdes2_prtcl_map;
34 static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
35 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
36 [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
37 [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
38 [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
39 [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
40 [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
43 static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
44 [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
45 [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
46 [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
47 [0x6] = {PCIE3, NONE, NONE, NONE},
48 [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
51 int is_serdes_configured(enum srds_prtcl device)
53 int ret = (1 << device) & serdes1_prtcl_map;
58 return (1 << device) & serdes2_prtcl_map;
61 void fsl_serdes_init(void)
63 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
64 u32 pordevsr = in_be32(&gur->pordevsr);
65 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
66 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
69 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
71 if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
72 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
75 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
76 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
77 serdes1_prtcl_map |= (1 << lane_prtcl);
80 if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
81 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
85 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
86 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
87 serdes2_prtcl_map |= (1 << lane_prtcl);
90 if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
91 serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
93 if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
94 serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);