2 * Copyright 2008-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
29 #include <asm/fsl_law.h>
32 DECLARE_GLOBAL_DATA_PTR;
36 return mfspr(SPRN_PIR);
40 * Determine if U-Boot should keep secondary cores in reset, or let them out
41 * of reset and hold them in a spinloop
43 int hold_cores_in_reset(int verbose)
45 const char *s = getenv("mp_holdoff");
47 /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
48 if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
50 puts("Secondary cores are being held in reset.\n");
51 puts("See 'mp_holdoff' environment variable\n");
62 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
63 out_be32(&pic->pir, 1 << nr);
64 /* the dummy read works around an errata on early 85xx MP PICs */
65 (void)in_be32(&pic->pir);
66 out_be32(&pic->pir, 0x0);
71 int cpu_status(int nr)
73 u32 *table, id = get_my_id();
75 if (hold_cores_in_reset(1))
79 table = (u32 *)get_spin_virt_addr();
80 printf("table base @ 0x%p\n", table);
82 table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
83 printf("Running on cpu %d\n", id);
85 printf("table @ 0x%p\n", table);
86 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
87 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
88 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
89 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
95 #ifdef CONFIG_FSL_CORENET
96 int cpu_disable(int nr)
98 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 setbits_be32(&gur->coredisrl, 1 << nr);
105 int is_core_disabled(int nr) {
106 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
107 u32 coredisrl = in_be32(&gur->coredisrl);
109 return (coredisrl & (1 << nr));
112 int cpu_disable(int nr)
114 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
118 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
121 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
124 printf("Invalid cpu number for disable %d\n", nr);
131 int is_core_disabled(int nr) {
132 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
133 u32 devdisr = in_be32(&gur->devdisr);
137 return (devdisr & MPC85xx_DEVDISR_CPU0);
139 return (devdisr & MPC85xx_DEVDISR_CPU1);
141 printf("Invalid cpu number for disable %d\n", nr);
148 static u8 boot_entry_map[4] = {
155 int cpu_release(int nr, int argc, char * const argv[])
157 u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
160 if (hold_cores_in_reset(1))
163 if (nr == get_my_id()) {
164 printf("Invalid to release the boot core.\n\n");
169 printf("Invalid number of arguments to release.\n\n");
173 boot_addr = simple_strtoull(argv[0], NULL, 16);
175 /* handle pir, r3, r6 */
176 for (i = 1; i < 4; i++) {
177 if (argv[i][0] != '-') {
178 u8 entry = boot_entry_map[i];
179 val = simple_strtoul(argv[i], NULL, 16);
184 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
186 /* ensure all table updates complete before final address write */
189 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
194 u32 determine_mp_bootpg(void)
196 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
197 if ((u64)gd->ram_size > 0xfffff000)
200 return (gd->ram_size - 4096);
203 ulong get_spin_phys_addr(void)
205 extern ulong __secondary_start_page;
206 extern ulong __spin_table;
208 return (determine_mp_bootpg() +
209 (ulong)&__spin_table - (ulong)&__secondary_start_page);
212 ulong get_spin_virt_addr(void)
214 extern ulong __secondary_start_page;
215 extern ulong __spin_table;
217 return (CONFIG_BPTR_VIRT_ADDR +
218 (ulong)&__spin_table - (ulong)&__secondary_start_page);
221 #ifdef CONFIG_FSL_CORENET
222 static void plat_mp_up(unsigned long bootpg)
224 u32 up, cpu_up_mask, whoami;
225 u32 *table = (u32 *)get_spin_virt_addr();
226 volatile ccsr_gur_t *gur;
227 volatile ccsr_local_t *ccm;
228 volatile ccsr_rcpm_t *rcpm;
229 volatile ccsr_pic_t *pic;
234 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
235 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
236 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
237 pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
239 nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
241 whoami = in_be32(&pic->whoami);
242 cpu_up_mask = 1 << whoami;
243 out_be32(&ccm->bstrl, bootpg);
245 e = find_law(bootpg);
246 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
248 /* readback to sync write */
249 in_be32(&ccm->bstrar);
251 /* disable time base at the platform */
252 out_be32(&rcpm->ctbenrl, cpu_up_mask);
254 /* release the hounds */
255 up = ((1 << nr_cpus) - 1);
256 out_be32(&gur->brrl, up);
258 /* wait for everyone */
261 for (i = 0; i < nr_cpus; i++) {
262 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
263 cpu_up_mask |= (1 << i);
266 if ((cpu_up_mask & up) == up)
274 printf("CPU up timeout. CPU up mask is %x should be %x\n",
277 /* enable time base at the platform */
278 out_be32(&rcpm->ctbenrl, 0);
281 out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
283 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
285 * Disabling Boot Page Translation allows the memory region 0xfffff000
286 * to 0xffffffff to be used normally. Leaving Boot Page Translation
287 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
288 * unusable for normal operation but it does allow OSes to easily
289 * reset a processor core to put it back into U-Boot's spinloop.
291 clrbits_be32(&ecm->bptr, 0x80000000);
295 static void plat_mp_up(unsigned long bootpg)
297 u32 up, cpu_up_mask, whoami;
298 u32 *table = (u32 *)get_spin_virt_addr();
300 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
301 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
302 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
306 whoami = in_be32(&pic->whoami);
307 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
309 /* disable time base at the platform */
310 devdisr = in_be32(&gur->devdisr);
312 devdisr |= MPC85xx_DEVDISR_TB0;
314 devdisr |= MPC85xx_DEVDISR_TB1;
315 out_be32(&gur->devdisr, devdisr);
317 /* release the hounds */
318 up = ((1 << cpu_numcores()) - 1);
319 bpcr = in_be32(&ecm->eebpcr);
321 out_be32(&ecm->eebpcr, bpcr);
322 asm("sync; isync; msync");
324 cpu_up_mask = 1 << whoami;
325 /* wait for everyone */
328 for (i = 0; i < cpu_numcores(); i++) {
329 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
330 cpu_up_mask |= (1 << i);
333 if ((cpu_up_mask & up) == up)
341 printf("CPU up timeout. CPU up mask is %x should be %x\n",
344 /* enable time base at the platform */
346 devdisr |= MPC85xx_DEVDISR_TB1;
348 devdisr |= MPC85xx_DEVDISR_TB0;
349 out_be32(&gur->devdisr, devdisr);
353 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
354 out_be32(&gur->devdisr, devdisr);
356 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
358 * Disabling Boot Page Translation allows the memory region 0xfffff000
359 * to 0xffffffff to be used normally. Leaving Boot Page Translation
360 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
361 * unusable for normal operation but it does allow OSes to easily
362 * reset a processor core to put it back into U-Boot's spinloop.
364 clrbits_be32(&ecm->bptr, 0x80000000);
369 void cpu_mp_lmb_reserve(struct lmb *lmb)
371 u32 bootpg = determine_mp_bootpg();
373 lmb_reserve(lmb, bootpg, 4096);
378 extern ulong __secondary_start_page;
379 extern ulong __bootpg_addr;
380 ulong fixup = (ulong)&__secondary_start_page;
381 u32 bootpg = determine_mp_bootpg();
383 /* Some OSes expect secondary cores to be held in reset */
384 if (hold_cores_in_reset(0))
387 /* Store the bootpg's SDRAM address for use by secondary CPU cores */
388 __bootpg_addr = bootpg;
390 /* look for the tlb covering the reset page, there better be one */
391 int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
393 /* we found a match */
395 /* map reset page to bootpg so we can copy code there */
398 set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
399 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
400 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
402 memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
406 puts("WARNING: No reset page TLB. "
407 "Skipping secondary core setup\n");