1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
10 #include <asm/global_data.h>
11 #include <asm/processor.h>
17 #include <asm/fsl_law.h>
18 #include <fsl_ddr_sdram.h>
19 #include <linux/delay.h>
22 DECLARE_GLOBAL_DATA_PTR;
23 u32 fsl_ddr_get_intl3r(void);
25 extern u32 __spin_table[];
29 return mfspr(SPRN_PIR);
33 * Determine if U-Boot should keep secondary cores in reset, or let them out
34 * of reset and hold them in a spinloop
36 int hold_cores_in_reset(int verbose)
38 /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
39 if (env_get_yesno("mp_holdoff") == 1) {
41 puts("Secondary cores are being held in reset.\n");
42 puts("See 'mp_holdoff' environment variable\n");
53 volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
54 out_be32(&pic->pir, 1 << nr);
55 /* the dummy read works around an errata on early 85xx MP PICs */
56 (void)in_be32(&pic->pir);
57 out_be32(&pic->pir, 0x0);
62 int cpu_status(u32 nr)
64 u32 *table, id = get_my_id();
66 if (hold_cores_in_reset(1))
70 table = (u32 *)&__spin_table;
71 printf("table base @ 0x%p\n", table);
72 } else if (is_core_disabled(nr)) {
75 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
76 printf("Running on cpu %d\n", id);
78 printf("table @ 0x%p\n", table);
79 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
80 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
81 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
87 #ifdef CONFIG_FSL_CORENET
88 int cpu_disable(u32 nr)
90 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
92 setbits_be32(&gur->coredisrl, 1 << nr);
97 int is_core_disabled(int nr) {
98 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
99 u32 coredisrl = in_be32(&gur->coredisrl);
101 return (coredisrl & (1 << nr));
104 int cpu_disable(u32 nr)
106 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
110 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
113 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
116 printf("Invalid cpu number for disable %d\n", nr);
123 int is_core_disabled(int nr) {
124 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
125 u32 devdisr = in_be32(&gur->devdisr);
129 return (devdisr & MPC85xx_DEVDISR_CPU0);
131 return (devdisr & MPC85xx_DEVDISR_CPU1);
133 printf("Invalid cpu number for disable %d\n", nr);
140 static u8 boot_entry_map[4] = {
146 int cpu_release(u32 nr, int argc, char *const argv[])
148 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
151 if (hold_cores_in_reset(1))
154 if (nr == get_my_id()) {
155 printf("Invalid to release the boot core.\n\n");
160 printf("Invalid number of arguments to release.\n\n");
164 boot_addr = simple_strtoull(argv[0], NULL, 16);
167 for (i = 1; i < 3; i++) {
168 if (argv[i][0] != '-') {
169 u8 entry = boot_entry_map[i];
170 val = hextoul(argv[i], NULL);
175 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
177 /* ensure all table updates complete before final address write */
180 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
185 u32 determine_mp_bootpg(unsigned int *pagesize)
188 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
190 u32 granule_size, check;
195 /* use last 4K of mapped memory */
196 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
197 CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
198 CFG_SYS_SDRAM_BASE - 4096;
202 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
204 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
205 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
206 * the way boot page chosen in u-boot avoids hitting this erratum. So only
207 * thw workaround for 3-way interleaving is needed.
209 * To make sure boot page translation works with 3-Way DDR interleaving
210 * enforce a check for the following constrains
211 * 8K granule size requires BRSIZE=8K and
212 * bootpg >> log2(BRSIZE) %3 == 1
213 * 4K and 1K granule size requires BRSIZE=4K and
214 * bootpg >> log2(BRSIZE) %3 == 0
216 if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
217 e = find_law(bootpg);
219 case LAW_TRGT_IF_DDR_INTLV_123:
220 granule_size = fsl_ddr_get_intl3r() & 0x1f;
221 if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
224 bootpg &= 0xffffe000; /* align to 8KB */
225 check = bootpg >> 13;
226 while ((check % 3) != 1)
228 bootpg = check << 13;
229 debug("Boot page (8K) at 0x%08x\n", bootpg);
232 bootpg &= 0xfffff000; /* align to 4KB */
233 check = bootpg >> 12;
234 while ((check % 3) != 0)
236 bootpg = check << 12;
237 debug("Boot page (4K) at 0x%08x\n", bootpg);
244 #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
249 phys_addr_t get_spin_phys_addr(void)
251 return virt_to_phys(&__spin_table);
254 #ifdef CONFIG_FSL_CORENET
255 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
257 u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
258 u32 *table = (u32 *)&__spin_table;
259 volatile ccsr_gur_t *gur;
260 volatile ccsr_local_t *ccm;
261 volatile ccsr_rcpm_t *rcpm;
262 volatile ccsr_pic_t *pic;
264 u32 mask = cpu_mask();
267 gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
268 ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
269 rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
270 pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
272 whoami = in_be32(&pic->whoami);
273 cpu_up_mask = 1 << whoami;
274 out_be32(&ccm->bstrl, bootpg);
276 e = find_law(bootpg);
277 /* pagesize is only 4K or 8K */
278 if (pagesize == 8192)
279 brsize = LAW_SIZE_8K;
280 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
281 debug("BRSIZE is 0x%x\n", brsize);
283 /* readback to sync write */
284 in_be32(&ccm->bstrar);
286 /* disable time base at the platform */
287 out_be32(&rcpm->ctbenrl, cpu_up_mask);
289 out_be32(&gur->brrl, mask);
291 /* wait for everyone */
293 unsigned int i, cpu, nr_cpus = cpu_numcores();
295 for_each_cpu(i, cpu, nr_cpus, mask) {
296 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
297 cpu_up_mask |= (1 << cpu);
300 if ((cpu_up_mask & mask) == mask)
308 printf("CPU up timeout. CPU up mask is %x should be %x\n",
311 /* enable time base at the platform */
312 out_be32(&rcpm->ctbenrl, 0);
314 /* readback to sync write */
315 in_be32(&rcpm->ctbenrl);
320 out_be32(&rcpm->ctbenrl, mask);
322 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
324 * Disabling Boot Page Translation allows the memory region 0xfffff000
325 * to 0xffffffff to be used normally. Leaving Boot Page Translation
326 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
327 * unusable for normal operation but it does allow OSes to easily
328 * reset a processor core to put it back into U-Boot's spinloop.
330 clrbits_be32(&ccm->bstrar, LAW_EN);
334 static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
336 u32 up, cpu_up_mask, whoami;
337 u32 *table = (u32 *)&__spin_table;
339 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
340 volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
341 volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
345 whoami = in_be32(&pic->whoami);
346 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
348 /* disable time base at the platform */
349 devdisr = in_be32(&gur->devdisr);
351 devdisr |= MPC85xx_DEVDISR_TB0;
353 devdisr |= MPC85xx_DEVDISR_TB1;
354 out_be32(&gur->devdisr, devdisr);
356 /* release the hounds */
357 up = ((1 << cpu_numcores()) - 1);
358 bpcr = in_be32(&ecm->eebpcr);
360 out_be32(&ecm->eebpcr, bpcr);
361 asm("sync; isync; msync");
363 cpu_up_mask = 1 << whoami;
364 /* wait for everyone */
367 for (i = 0; i < cpu_numcores(); i++) {
368 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
369 cpu_up_mask |= (1 << i);
372 if ((cpu_up_mask & up) == up)
380 printf("CPU up timeout. CPU up mask is %x should be %x\n",
383 /* enable time base at the platform */
385 devdisr |= MPC85xx_DEVDISR_TB1;
387 devdisr |= MPC85xx_DEVDISR_TB0;
388 out_be32(&gur->devdisr, devdisr);
390 /* readback to sync write */
391 in_be32(&gur->devdisr);
396 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
397 out_be32(&gur->devdisr, devdisr);
399 #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
401 * Disabling Boot Page Translation allows the memory region 0xfffff000
402 * to 0xffffffff to be used normally. Leaving Boot Page Translation
403 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
404 * unusable for normal operation but it does allow OSes to easily
405 * reset a processor core to put it back into U-Boot's spinloop.
407 clrbits_be32(&ecm->bptr, 0x80000000);
412 void cpu_mp_lmb_reserve(struct lmb *lmb)
414 u32 bootpg = determine_mp_bootpg(NULL);
416 lmb_reserve(lmb, bootpg, 4096);
421 extern u32 __secondary_start_page;
422 extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
425 ulong fixup = (u32)&__secondary_start_page;
426 u32 bootpg, bootpg_map, pagesize;
428 bootpg = determine_mp_bootpg(&pagesize);
431 * pagesize is only 4K or 8K
432 * we only use the last 4K of boot page
433 * bootpg_map saves the address for the boot page
434 * 8K is used for the workaround of 3-way DDR interleaving
439 if (pagesize == 8192)
440 bootpg += 4096; /* use 2nd half */
442 /* Some OSes expect secondary cores to be held in reset */
443 if (hold_cores_in_reset(0))
447 * Store the bootpg's cache-able half address for use by secondary
448 * CPU cores to continue to boot
450 __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
452 /* Store spin table's physical address for use by secondary cores */
453 __spin_table_addr = (u32)get_spin_phys_addr();
455 /* flush bootpg it before copying invalidate any staled cacheline */
456 flush_cache(bootpg, 4096);
458 /* look for the tlb covering the reset page, there better be one */
459 i = find_tlb_idx((void *)BPTR_VIRT_ADDR, 1);
461 /* we found a match */
463 /* map reset page to bootpg so we can copy code there */
466 set_tlb(1, BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
467 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
468 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
470 memcpy((void *)BPTR_VIRT_ADDR, (void *)fixup, 4096);
472 plat_mp_up(bootpg_map, pagesize);
474 puts("WARNING: No reset page TLB. "
475 "Skipping secondary core setup\n");