arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  25 #include <hwconfig.h>
  26 #endif
  27 #include <asm/fsl_serdes.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/io.h>
  30 #include <asm/processor.h>
  31 #include <asm/fsl_law.h>
  32 #include "fsl_corenet_serdes.h"
  33
  34 static u32 serdes_prtcl_map;
  35
  36 #define HWCONFIG_BUFFER_SIZE    128
  37
  38 #ifdef DEBUG
  39 static const char *serdes_prtcl_str[] = {
  40         [NONE] = "NA",
  41         [PCIE1] = "PCIE1",
  42         [PCIE2] = "PCIE2",
  43         [PCIE3] = "PCIE3",
  44         [PCIE4] = "PCIE4",
  45         [SATA1] = "SATA1",
  46         [SATA2] = "SATA2",
  47         [SRIO1] = "SRIO1",
  48         [SRIO2] = "SRIO2",
  49         [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  50         [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  51         [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  52         [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  53         [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  54         [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  55         [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  56         [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  57         [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  58         [XAUI_FM1] = "XAUI_FM1",
  59         [XAUI_FM2] = "XAUI_FM2",
  60         [AURORA] = "DEBUG",
  61 };
  62 #endif
  63
  64 static const struct {
  65         int idx;
  66         unsigned int lpd; /* RCW lane powerdown bit */
  67         int bank;
  68 } lanes[SRDS_MAX_LANES] = {
  69         { 0, 152, FSL_SRDS_BANK_1 },
  70         { 1, 153, FSL_SRDS_BANK_1 },
  71         { 2, 154, FSL_SRDS_BANK_1 },
  72         { 3, 155, FSL_SRDS_BANK_1 },
  73         { 4, 156, FSL_SRDS_BANK_1 },
  74         { 5, 157, FSL_SRDS_BANK_1 },
  75         { 6, 158, FSL_SRDS_BANK_1 },
  76         { 7, 159, FSL_SRDS_BANK_1 },
  77         { 8, 160, FSL_SRDS_BANK_1 },
  78         { 9, 161, FSL_SRDS_BANK_1 },
  79         { 16, 162, FSL_SRDS_BANK_2 },
  80         { 17, 163, FSL_SRDS_BANK_2 },
  81         { 18, 164, FSL_SRDS_BANK_2 },
  82         { 19, 165, FSL_SRDS_BANK_2 },
  83         { 20, 170, FSL_SRDS_BANK_3 },
  84         { 21, 171, FSL_SRDS_BANK_3 },
  85         { 22, 172, FSL_SRDS_BANK_3 },
  86         { 23, 173, FSL_SRDS_BANK_3 },
  87 };
  88
  89 int serdes_get_lane_idx(int lane)
  90 {
  91         return lanes[lane].idx;
  92 }
  93
  94 int serdes_get_bank(int lane)
  95 {
  96         return lanes[lane].bank;
  97 }
  98
  99 int serdes_lane_enabled(int lane)
 100 {
 101         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 102         serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 103
 104         int bank = lanes[lane].bank;
 105         int word = lanes[lane].lpd / 32;
 106         int bit = lanes[lane].lpd % 32;
 107
 108         if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
 109                 return 0;
 110
 111 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 112         if (!IS_SVR_REV(get_svr(), 1, 0))
 113                 if (bank > 0)
 114                         return !(srds_lpd_b[bank] &
 115                                         (8 >> (lane - (6 + 4 * bank))));
 116 #endif
 117
 118         return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
 119 }
 120
 121 int is_serdes_configured(enum srds_prtcl device)
 122 {
 123         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 124
 125         /* Is serdes enabled at all? */
 126         if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 127                 return 0;
 128
 129         return (1 << device) & serdes_prtcl_map;
 130 }
 131
 132 #ifndef CONFIG_SYS_DCSRBAR_PHYS
 133 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
 134 #define CONFIG_SYS_DCSRBAR      0x80000000
 135 #define __DCSR_NOT_DEFINED_BY_CONFIG
 136 #endif
 137
 138 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 139 static void enable_bank(ccsr_gur_t *gur, int bank)
 140 {
 141         u32 rcw5;
 142
 143         /*
 144          * Enable the lanes SRDS_LPD_Bn.  The RCW bits are read-only in
 145          * CCSR, and read/write in DSCR.
 146          */
 147         rcw5 = in_be32(gur->rcwsr + 5);
 148         if (bank == FSL_SRDS_BANK_2) {
 149                 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
 150                 rcw5 |= srds_lpd_b[bank] << 26;
 151         } else if (bank == FSL_SRDS_BANK_3) {
 152                 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
 153                 rcw5 |= srds_lpd_b[bank] << 18;
 154         } else {
 155                 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
 156                 return;
 157         }
 158
 159         /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
 160          * of the DCSR mapping.
 161          */
 162         {
 163 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 164                 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
 165                 int law_index;
 166                 if (law.index == -1)
 167                         law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
 168                                                  LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
 169                 else
 170                         set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
 171                                 LAW_TRGT_IF_DCSR);
 172 #endif
 173                 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
 174                 out_be32(p, rcw5);
 175 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 176                 if (law.index == -1)
 177                         disable_law(law_index);
 178                 else
 179                         set_law(law.index, law.addr, law.size, law.trgt_id);
 180 #endif
 181         }
 182 }
 183
 184 /*
 185  * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
 186  * bank 3 to clock banks 2 and 3, as well as a limited selection of
 187  * protocol configurations.  This requires that banks 2 and 3's lanes be
 188  * disabled in the RCW, and enabled with some fixup here to re-enable
 189  * them, and to configure bank 2's clock parameters in bank 3's pll in
 190  * cases where they differ.
 191  */
 192 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
 193                                   u32 devdisr, u32 devdisr2, int cfg)
 194 {
 195         int srds_ratio_b2;
 196         int rfck_sel;
 197
 198         /*
 199          * The disabled lanes of bank 2 will cause the associated
 200          * logic blocks to be disabled in DEVDISR.  We reverse that here.
 201          *
 202          * Note that normally it is not permitted to clear DEVDISR bits
 203          * once the device has been disabled, but the hardware people
 204          * say that this special case is OK.
 205          */
 206         clrbits_be32(&gur->devdisr, devdisr);
 207         clrbits_be32(&gur->devdisr2, devdisr2);
 208
 209         /*
 210          * Some protocols require special handling.  There are a few
 211          * additional protocol configurations that can be used, which are
 212          * not listed here.  See app note 4065 for supported protocol
 213          * configurations.
 214          */
 215         switch (cfg) {
 216         case 0x19:
 217                 /*
 218                  * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
 219                  * SGMII on bank 3 should still be usable.
 220                  */
 221                 setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
 222                              SRDS_PLLCR1_PLL_BWSEL);
 223
 224                 enable_bank(gur, FSL_SRDS_BANK_3);
 225                 break;
 226
 227         case 0x0f:
 228         case 0x10:
 229                 /*
 230                  * Banks 2 (XAUI) and 3 (SGMII) have different clocking
 231                  * requirements in these configurations.  Bank 3 cannot
 232                  * be used and should have its lanes (but not the bank
 233                  * itself) disabled in the RCW.  We set up bank 3's pll
 234                  * for bank 2's needs here.
 235                  */
 236                 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
 237
 238                 /* Determine refclock from XAUI ratio */
 239                 switch (srds_ratio_b2) {
 240                 case 1: /* 20:1 */
 241                         rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
 242                         break;
 243                 case 2: /* 25:1 */
 244                         rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
 245                         break;
 246                 default:
 247                         printf("SERDES: bad SRDS_RATIO_B2 %d\n",
 248                                srds_ratio_b2);
 249                         return;
 250                 }
 251
 252                 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
 253                                 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
 254
 255                 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
 256                                 SRDS_PLLCR0_FRATE_SEL_MASK,
 257                                 SRDS_PLLCR0_FRATE_SEL_6_25);
 258                 break;
 259         default:
 260                 enable_bank(gur, FSL_SRDS_BANK_3);
 261         }
 262
 263 }
 264 #endif
 265
 266 void fsl_serdes_init(void)
 267 {
 268         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 269         int cfg;
 270         serdes_corenet_t *srds_regs;
 271         int lane, bank, idx;
 272         enum srds_prtcl lane_prtcl;
 273         long long end_tick;
 274         int have_bank[SRDS_MAX_BANK] = {};
 275 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 276         u32 serdes8_devdisr = 0;
 277         u32 serdes8_devdisr2 = 0;
 278         char srds_lpd_opt[16];
 279         const char *srds_lpd_arg;
 280         size_t arglen;
 281 #endif
 282         char buffer[HWCONFIG_BUFFER_SIZE];
 283         char *buf = NULL;
 284
 285         /*
 286          * Extract hwconfig from environment since we have not properly setup
 287          * the environment but need it for ddr config params
 288          */
 289         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 290                 buf = buffer;
 291
 292         /* Is serdes enabled at all? */
 293         if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 294                 return;
 295
 296         srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
 297         cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 298         debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
 299
 300         if (!is_serdes_prtcl_valid(cfg)) {
 301                 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
 302                 return;
 303         }
 304
 305 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 306         if (!IS_SVR_REV(get_svr(), 1, 0))
 307                 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
 308                         sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
 309                         srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt,
 310                                                        &arglen, buf);
 311                         if (srds_lpd_arg)
 312                                 srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg,
 313                                                                   NULL, 0);
 314                 }
 315 #endif
 316
 317         /* Look for banks with all lanes disabled, and power down the bank. */
 318         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 319                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
 320                 if (serdes_lane_enabled(lane)) {
 321                         have_bank[serdes_get_bank(lane)] = 1;
 322                         serdes_prtcl_map |= (1 << lane_prtcl);
 323                 }
 324         }
 325
 326 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 327         if (IS_SVR_REV(get_svr(), 1, 0)) {
 328                 /* At least one bank must be disabled due to SERDES8.  If
 329                  * no bank is found to be disabled based on lane
 330                  * disables, disable bank 3 because we can't turn off its
 331                  * lanes in the RCW without disabling MDIO due to erratum
 332                  * GEN8.
 333                  *
 334                  * This means that if you are relying on bank 3 being
 335                  * disabled to avoid SERDES8, in some cases you cannot
 336                  * also disable all lanes of another bank, or else bank
 337                  * 3 won't be disabled, leaving you with a configuration
 338                  * that isn't valid according to SERDES8 (e.g. if banks
 339                  * 2 and 3 have the same clock, and bank 1 is disabled
 340                  * instead of 3).
 341                  */
 342                 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
 343                         if (!have_bank[bank])
 344                                 break;
 345                 }
 346
 347                 if (bank == SRDS_MAX_BANK)
 348                         have_bank[FSL_SRDS_BANK_3] = 0;
 349         } else {
 350                 if (have_bank[FSL_SRDS_BANK_2])
 351                         have_bank[FSL_SRDS_BANK_3] = 1;
 352         }
 353 #endif
 354
 355         for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
 356                 if (!have_bank[bank]) {
 357                         printf("SERDES: bank %d disabled\n", bank + 1);
 358                         setbits_be32(&srds_regs->bank[bank].rstctl,
 359                                      SRDS_RSTCTL_SDPD);
 360                 }
 361         }
 362
 363         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 364                 idx = serdes_get_lane_idx(lane);
 365                 lane_prtcl = serdes_get_prtcl(cfg, lane);
 366
 367 #ifdef DEBUG
 368                 switch (lane) {
 369                 case 0:
 370                         puts("Bank1: ");
 371                         break;
 372                 case 10:
 373                         puts("\nBank2: ");
 374                         break;
 375                 case 14:
 376                         puts("\nBank3: ");
 377                         break;
 378                 default:
 379                         break;
 380                 }
 381
 382                 printf("%s ", serdes_prtcl_str[lane_prtcl]);
 383 #endif
 384
 385 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 386                 switch (lane_prtcl) {
 387                 case PCIE1:
 388                 case PCIE2:
 389                 case PCIE3:
 390                         serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
 391                                            (lane_prtcl - PCIE1);
 392                         break;
 393                 case SRIO1:
 394                 case SRIO2:
 395                         serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
 396                                            (lane_prtcl - SRIO1);
 397                         break;
 398                 case SGMII_FM1_DTSEC1:
 399                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 400                                             FSL_CORENET_DEVDISR2_DTSEC1_1;
 401                         break;
 402                 case SGMII_FM1_DTSEC2:
 403                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 404                                             FSL_CORENET_DEVDISR2_DTSEC1_2;
 405                         break;
 406                 case SGMII_FM1_DTSEC3:
 407                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 408                                             FSL_CORENET_DEVDISR2_DTSEC1_3;
 409                         break;
 410                 case SGMII_FM1_DTSEC4:
 411                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 412                                             FSL_CORENET_DEVDISR2_DTSEC1_4;
 413                         break;
 414                 case SGMII_FM2_DTSEC1:
 415                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 416                                             FSL_CORENET_DEVDISR2_DTSEC2_1;
 417                         break;
 418                 case SGMII_FM2_DTSEC2:
 419                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 420                                             FSL_CORENET_DEVDISR2_DTSEC2_2;
 421                         break;
 422                 case SGMII_FM2_DTSEC3:
 423                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 424                                             FSL_CORENET_DEVDISR2_DTSEC2_3;
 425                         break;
 426                 case SGMII_FM2_DTSEC4:
 427                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 428                                             FSL_CORENET_DEVDISR2_DTSEC2_4;
 429                         break;
 430                 case XAUI_FM1:
 431                 case XAUI_FM2:
 432                         if (lane_prtcl == XAUI_FM1)
 433                                 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1    |
 434                                                     FSL_CORENET_DEVDISR2_10GEC1;
 435                         else
 436                                 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2    |
 437                                                     FSL_CORENET_DEVDISR2_10GEC2;
 438                         break;
 439                 case AURORA:
 440                         break;
 441                 default:
 442                         break;
 443                 }
 444
 445 #endif
 446         }
 447
 448 #ifdef DEBUG
 449         puts("\n");
 450 #endif
 451
 452         for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
 453                 u32 rstctl;
 454
 455                 bank = idx;
 456
 457 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 458                 if (!IS_SVR_REV(get_svr(), 1, 0)) {
 459                         /*
 460                          * Change bank init order to 0, 2, 1, so that the
 461                          * third bank's PLL is established before we
 462                          * start the second bank which shares the third
 463                          * bank's PLL.
 464                          */
 465
 466                         if (idx == 1)
 467                                 bank = FSL_SRDS_BANK_3;
 468                         else if (idx == 2)
 469                                 bank = FSL_SRDS_BANK_2;
 470                 }
 471 #endif
 472
 473                 /* Skip disabled banks */
 474                 if (!have_bank[bank])
 475                         continue;
 476
 477 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 478                 if (!IS_SVR_REV(get_svr(), 1, 0)) {
 479                         if (idx == 1) {
 480                                 p4080_erratum_serdes8(srds_regs, gur,
 481                                                       serdes8_devdisr,
 482                                                       serdes8_devdisr2, cfg);
 483                         } else if (idx == 2) {
 484                                 enable_bank(gur, FSL_SRDS_BANK_2);
 485                         }
 486                 }
 487 #endif
 488
 489                 /* reset banks for errata */
 490                 setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
 491
 492                 /* wait for reset complete or 1-second timeout */
 493                 end_tick = usec2ticks(1000000) + get_ticks();
 494                 do {
 495                         rstctl = in_be32(&srds_regs->bank[bank].rstctl);
 496                         if (rstctl & SRDS_RSTCTL_RSTDONE)
 497                                 break;
 498                 } while (end_tick > get_ticks());
 499
 500                 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) {
 501                         printf("SERDES: timeout resetting bank %d\n",
 502                                bank + 1);
 503                         continue;
 504                 }
 505         }
 506 }