arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
  25 #include <hwconfig.h>
  26 #endif
  27 #include <asm/fsl_serdes.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/io.h>
  30 #include <asm/processor.h>
  31 #include <asm/fsl_law.h>
  32 #include <asm/errno.h>
  33 #include "fsl_corenet_serdes.h"
  34
  35 static u32 serdes_prtcl_map;
  36
  37 #define HWCONFIG_BUFFER_SIZE    128
  38
  39 #ifdef DEBUG
  40 static const char *serdes_prtcl_str[] = {
  41         [NONE] = "NA",
  42         [PCIE1] = "PCIE1",
  43         [PCIE2] = "PCIE2",
  44         [PCIE3] = "PCIE3",
  45         [PCIE4] = "PCIE4",
  46         [SATA1] = "SATA1",
  47         [SATA2] = "SATA2",
  48         [SRIO1] = "SRIO1",
  49         [SRIO2] = "SRIO2",
  50         [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
  51         [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
  52         [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
  53         [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
  54         [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
  55         [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
  56         [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
  57         [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
  58         [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
  59         [XAUI_FM1] = "XAUI_FM1",
  60         [XAUI_FM2] = "XAUI_FM2",
  61         [AURORA] = "DEBUG",
  62 };
  63 #endif
  64
  65 static const struct {
  66         int idx;
  67         unsigned int lpd; /* RCW lane powerdown bit */
  68         int bank;
  69 } lanes[SRDS_MAX_LANES] = {
  70         { 0, 152, FSL_SRDS_BANK_1 },
  71         { 1, 153, FSL_SRDS_BANK_1 },
  72         { 2, 154, FSL_SRDS_BANK_1 },
  73         { 3, 155, FSL_SRDS_BANK_1 },
  74         { 4, 156, FSL_SRDS_BANK_1 },
  75         { 5, 157, FSL_SRDS_BANK_1 },
  76         { 6, 158, FSL_SRDS_BANK_1 },
  77         { 7, 159, FSL_SRDS_BANK_1 },
  78         { 8, 160, FSL_SRDS_BANK_1 },
  79         { 9, 161, FSL_SRDS_BANK_1 },
  80         { 16, 162, FSL_SRDS_BANK_2 },
  81         { 17, 163, FSL_SRDS_BANK_2 },
  82         { 18, 164, FSL_SRDS_BANK_2 },
  83         { 19, 165, FSL_SRDS_BANK_2 },
  84         { 20, 170, FSL_SRDS_BANK_3 },
  85         { 21, 171, FSL_SRDS_BANK_3 },
  86         { 22, 172, FSL_SRDS_BANK_3 },
  87         { 23, 173, FSL_SRDS_BANK_3 },
  88 };
  89
  90 int serdes_get_lane_idx(int lane)
  91 {
  92         return lanes[lane].idx;
  93 }
  94
  95 int serdes_get_bank_by_lane(int lane)
  96 {
  97         return lanes[lane].bank;
  98 }
  99
 100 int serdes_lane_enabled(int lane)
 101 {
 102         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 103         serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 104
 105         int bank = lanes[lane].bank;
 106         int word = lanes[lane].lpd / 32;
 107         int bit = lanes[lane].lpd % 32;
 108
 109         if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
 110                 return 0;
 111
 112 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 113         /*
 114          * For banks two and three, use the srds_lpd_b[] array instead of the
 115          * RCW, because this array contains the real values of SRDS_LPD_B2 and
 116          * SRDS_LPD_B3.
 117          */
 118         if (bank > 0)
 119                 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
 120 #endif
 121
 122         return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
 123 }
 124
 125 int is_serdes_configured(enum srds_prtcl device)
 126 {
 127         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 128
 129         /* Is serdes enabled at all? */
 130         if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 131                 return 0;
 132
 133         return (1 << device) & serdes_prtcl_map;
 134 }
 135
 136 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
 137 {
 138         int i;
 139
 140         for (i = 0; i < SRDS_MAX_LANES; i++) {
 141                 if (serdes_get_prtcl(prtcl, i) == device)
 142                         return i;
 143         }
 144
 145         return -ENODEV;
 146 }
 147
 148 /*
 149  * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
 150  * device. This depends on the current SERDES protocol, as defined in the RCW.
 151  *
 152  * Returns a negative error code if SERDES is disabled or the given device is
 153  * not supported in the current SERDES protocol.
 154  */
 155 int serdes_get_first_lane(enum srds_prtcl device)
 156 {
 157         u32 prtcl;
 158         const ccsr_gur_t *gur;
 159
 160         gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
 161
 162         /* Is serdes enabled at all? */
 163         if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
 164                 return -ENODEV;
 165
 166         prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 167
 168         return __serdes_get_first_lane(prtcl, device);
 169 }
 170
 171 #ifndef CONFIG_SYS_DCSRBAR_PHYS
 172 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
 173 #define CONFIG_SYS_DCSRBAR      0x80000000
 174 #define __DCSR_NOT_DEFINED_BY_CONFIG
 175 #endif
 176
 177 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 178 static void enable_bank(ccsr_gur_t *gur, int bank)
 179 {
 180         u32 rcw5;
 181
 182         /*
 183          * Enable the lanes SRDS_LPD_Bn.  The RCW bits are read-only in
 184          * CCSR, and read/write in DSCR.
 185          */
 186         rcw5 = in_be32(gur->rcwsr + 5);
 187         if (bank == FSL_SRDS_BANK_2) {
 188                 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
 189                 rcw5 |= srds_lpd_b[bank] << 26;
 190         } else if (bank == FSL_SRDS_BANK_3) {
 191                 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
 192                 rcw5 |= srds_lpd_b[bank] << 18;
 193         } else {
 194                 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
 195                 return;
 196         }
 197
 198         /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
 199          * of the DCSR mapping.
 200          */
 201         {
 202 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 203                 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
 204                 int law_index;
 205                 if (law.index == -1)
 206                         law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
 207                                                  LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
 208                 else
 209                         set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
 210                                 LAW_TRGT_IF_DCSR);
 211 #endif
 212                 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
 213                 out_be32(p, rcw5);
 214 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
 215                 if (law.index == -1)
 216                         disable_law(law_index);
 217                 else
 218                         set_law(law.index, law.addr, law.size, law.trgt_id);
 219 #endif
 220         }
 221 }
 222
 223 /*
 224  * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
 225  * bank 3 to clock banks 2 and 3, as well as a limited selection of
 226  * protocol configurations.  This requires that banks 2 and 3's lanes be
 227  * disabled in the RCW, and enabled with some fixup here to re-enable
 228  * them, and to configure bank 2's clock parameters in bank 3's pll in
 229  * cases where they differ.
 230  */
 231 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
 232                                   u32 devdisr, u32 devdisr2, int cfg)
 233 {
 234         int srds_ratio_b2;
 235         int rfck_sel;
 236
 237         /*
 238          * The disabled lanes of bank 2 will cause the associated
 239          * logic blocks to be disabled in DEVDISR.  We reverse that here.
 240          *
 241          * Note that normally it is not permitted to clear DEVDISR bits
 242          * once the device has been disabled, but the hardware people
 243          * say that this special case is OK.
 244          */
 245         clrbits_be32(&gur->devdisr, devdisr);
 246         clrbits_be32(&gur->devdisr2, devdisr2);
 247
 248         /*
 249          * Some protocols require special handling.  There are a few
 250          * additional protocol configurations that can be used, which are
 251          * not listed here.  See app note 4065 for supported protocol
 252          * configurations.
 253          */
 254         switch (cfg) {
 255         case 0x19:
 256                 /*
 257                  * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
 258                  * SGMII on bank 3 should still be usable.
 259                  */
 260                 setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1,
 261                              SRDS_PLLCR1_PLL_BWSEL);
 262
 263                 enable_bank(gur, FSL_SRDS_BANK_3);
 264                 break;
 265
 266         case 0x0f:
 267         case 0x10:
 268                 /*
 269                  * Banks 2 (XAUI) and 3 (SGMII) have different clocking
 270                  * requirements in these configurations.  Bank 3 cannot
 271                  * be used and should have its lanes (but not the bank
 272                  * itself) disabled in the RCW.  We set up bank 3's pll
 273                  * for bank 2's needs here.
 274                  */
 275                 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
 276
 277                 /* Determine refclock from XAUI ratio */
 278                 switch (srds_ratio_b2) {
 279                 case 1: /* 20:1 */
 280                         rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
 281                         break;
 282                 case 2: /* 25:1 */
 283                         rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
 284                         break;
 285                 default:
 286                         printf("SERDES: bad SRDS_RATIO_B2 %d\n",
 287                                srds_ratio_b2);
 288                         return;
 289                 }
 290
 291                 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
 292                                 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
 293
 294                 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0,
 295                                 SRDS_PLLCR0_FRATE_SEL_MASK,
 296                                 SRDS_PLLCR0_FRATE_SEL_6_25);
 297                 break;
 298         default:
 299                 enable_bank(gur, FSL_SRDS_BANK_3);
 300         }
 301
 302 }
 303 #endif
 304
 305 void fsl_serdes_init(void)
 306 {
 307         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 308         int cfg;
 309         serdes_corenet_t *srds_regs;
 310         int lane, bank, idx;
 311         enum srds_prtcl lane_prtcl;
 312         long long end_tick;
 313         int have_bank[SRDS_MAX_BANK] = {};
 314 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 315         u32 serdes8_devdisr = 0;
 316         u32 serdes8_devdisr2 = 0;
 317         char srds_lpd_opt[16];
 318         const char *srds_lpd_arg;
 319         size_t arglen;
 320 #endif
 321         char buffer[HWCONFIG_BUFFER_SIZE];
 322         char *buf = NULL;
 323
 324         /*
 325          * Extract hwconfig from environment since we have not properly setup
 326          * the environment but need it for ddr config params
 327          */
 328         if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 329                 buf = buffer;
 330
 331         /* Is serdes enabled at all? */
 332         if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
 333                 return;
 334
 335         srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
 336         cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
 337         debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
 338
 339         if (!is_serdes_prtcl_valid(cfg)) {
 340                 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
 341                 return;
 342         }
 343
 344 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 345         /*
 346          * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
 347          * hwconfig options into the srds_lpd_b[] array.  See README.p4080ds
 348          * for a description of these options.
 349          */
 350         for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
 351                 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
 352                 srds_lpd_arg =
 353                         hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
 354                 if (srds_lpd_arg)
 355                         srds_lpd_b[bank] =
 356                                 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
 357         }
 358 #endif
 359
 360         /* Look for banks with all lanes disabled, and power down the bank. */
 361         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 362                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
 363                 if (serdes_lane_enabled(lane)) {
 364                         have_bank[serdes_get_bank_by_lane(lane)] = 1;
 365                         serdes_prtcl_map |= (1 << lane_prtcl);
 366                 }
 367         }
 368
 369 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 370         /*
 371          * Bank two uses the clock from bank three, so if bank two is enabled,
 372          * then bank three must also be enabled.
 373          */
 374         if (have_bank[FSL_SRDS_BANK_2])
 375                 have_bank[FSL_SRDS_BANK_3] = 1;
 376 #endif
 377
 378         for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
 379                 if (!have_bank[bank]) {
 380                         printf("SERDES: bank %d disabled\n", bank + 1);
 381                         setbits_be32(&srds_regs->bank[bank].rstctl,
 382                                      SRDS_RSTCTL_SDPD);
 383                 }
 384         }
 385
 386         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 387                 idx = serdes_get_lane_idx(lane);
 388                 lane_prtcl = serdes_get_prtcl(cfg, lane);
 389
 390 #ifdef DEBUG
 391                 switch (lane) {
 392                 case 0:
 393                         puts("Bank1: ");
 394                         break;
 395                 case 10:
 396                         puts("\nBank2: ");
 397                         break;
 398                 case 14:
 399                         puts("\nBank3: ");
 400                         break;
 401                 default:
 402                         break;
 403                 }
 404
 405                 printf("%s ", serdes_prtcl_str[lane_prtcl]);
 406 #endif
 407
 408 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 409                 switch (lane_prtcl) {
 410                 case PCIE1:
 411                 case PCIE2:
 412                 case PCIE3:
 413                         serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
 414                                            (lane_prtcl - PCIE1);
 415                         break;
 416                 case SRIO1:
 417                 case SRIO2:
 418                         serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
 419                                            (lane_prtcl - SRIO1);
 420                         break;
 421                 case SGMII_FM1_DTSEC1:
 422                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 423                                             FSL_CORENET_DEVDISR2_DTSEC1_1;
 424                         break;
 425                 case SGMII_FM1_DTSEC2:
 426                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 427                                             FSL_CORENET_DEVDISR2_DTSEC1_2;
 428                         break;
 429                 case SGMII_FM1_DTSEC3:
 430                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 431                                             FSL_CORENET_DEVDISR2_DTSEC1_3;
 432                         break;
 433                 case SGMII_FM1_DTSEC4:
 434                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
 435                                             FSL_CORENET_DEVDISR2_DTSEC1_4;
 436                         break;
 437                 case SGMII_FM2_DTSEC1:
 438                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 439                                             FSL_CORENET_DEVDISR2_DTSEC2_1;
 440                         break;
 441                 case SGMII_FM2_DTSEC2:
 442                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 443                                             FSL_CORENET_DEVDISR2_DTSEC2_2;
 444                         break;
 445                 case SGMII_FM2_DTSEC3:
 446                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 447                                             FSL_CORENET_DEVDISR2_DTSEC2_3;
 448                         break;
 449                 case SGMII_FM2_DTSEC4:
 450                         serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
 451                                             FSL_CORENET_DEVDISR2_DTSEC2_4;
 452                         break;
 453                 case XAUI_FM1:
 454                 case XAUI_FM2:
 455                         if (lane_prtcl == XAUI_FM1)
 456                                 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1    |
 457                                                     FSL_CORENET_DEVDISR2_10GEC1;
 458                         else
 459                                 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2    |
 460                                                     FSL_CORENET_DEVDISR2_10GEC2;
 461                         break;
 462                 case AURORA:
 463                         break;
 464                 default:
 465                         break;
 466                 }
 467
 468 #endif
 469         }
 470
 471 #ifdef DEBUG
 472         puts("\n");
 473 #endif
 474
 475         for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
 476                 u32 rstctl;
 477
 478                 bank = idx;
 479
 480 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 481                 /*
 482                  * Change bank init order to 0, 2, 1, so that the third bank's
 483                  * PLL is established before we start the second bank.  The
 484                  * second bank uses the third bank's PLL.
 485                  */
 486
 487                 if (idx == 1)
 488                         bank = FSL_SRDS_BANK_3;
 489                 else if (idx == 2)
 490                         bank = FSL_SRDS_BANK_2;
 491 #endif
 492
 493                 /* Skip disabled banks */
 494                 if (!have_bank[bank])
 495                         continue;
 496
 497 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 498                 if (idx == 1) {
 499                         /*
 500                          * Re-enable devices on banks two and three that were
 501                          * disabled by the RCW, and then enable bank three. The
 502                          * devices need to be enabled before either bank is
 503                          * powered up.
 504                          */
 505                         p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
 506                                               serdes8_devdisr2, cfg);
 507                 } else if (idx == 2) {
 508                         /* Eable bank two now that bank three is enabled. */
 509                         enable_bank(gur, FSL_SRDS_BANK_2);
 510                 }
 511 #endif
 512
 513                 /* reset banks for errata */
 514                 setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
 515
 516                 /* wait for reset complete or 1-second timeout */
 517                 end_tick = usec2ticks(1000000) + get_ticks();
 518                 do {
 519                         rstctl = in_be32(&srds_regs->bank[bank].rstctl);
 520                         if (rstctl & SRDS_RSTCTL_RSTDONE)
 521                                 break;
 522                 } while (end_tick > get_ticks());
 523
 524                 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) {
 525                         printf("SERDES: timeout resetting bank %d\n",
 526                                bank + 1);
 527                         continue;
 528                 }
 529         }
 530 }