2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
30 #include <linux/ctype.h>
32 #include <asm/fsl_portals.h>
33 #ifdef CONFIG_FSL_ESDHC
34 #include <fsl_esdhc.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 extern void ft_qe_setup(void *blob);
40 extern void ft_fixup_num_cores(void *blob);
45 void ft_fixup_cpu(void *blob, u64 memory_limit)
48 ulong spin_tbl_addr = get_spin_phys_addr();
49 u32 bootpg = determine_mp_bootpg();
52 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
53 while (off != -FDT_ERR_NOTFOUND) {
54 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
57 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
58 val = cpu_to_fdt32(val);
60 fdt_setprop_string(blob, off, "status",
63 fdt_setprop_string(blob, off, "status",
66 fdt_setprop_string(blob, off, "enable-method",
68 fdt_setprop(blob, off, "cpu-release-addr",
71 printf ("cpu NULL\n");
73 off = fdt_node_offset_by_prop_value(blob, off,
74 "device_type", "cpu", 4);
77 /* Reserve the boot page so OSes dont use it */
78 if ((u64)bootpg < memory_limit) {
79 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
81 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
86 #ifdef CONFIG_SYS_FSL_CPC
87 static inline void ft_fixup_l3cache(void *blob, int off)
89 u32 line_size, num_ways, size, num_sets;
90 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
91 u32 cfg0 = in_be32(&cpc->cpccfg0);
93 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
94 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
95 line_size = CPC_CFG0_LINE_SZ(cfg0);
96 num_sets = size / (line_size * num_ways);
98 fdt_setprop(blob, off, "cache-unified", NULL, 0);
99 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
100 fdt_setprop_cell(blob, off, "cache-size", size);
101 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
102 fdt_setprop_cell(blob, off, "cache-level", 3);
103 #ifdef CONFIG_SYS_CACHE_STASHING
104 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
108 #define ft_fixup_l3cache(x, y)
111 #if defined(CONFIG_L2_CACHE)
112 /* return size in kilobytes */
113 static inline u32 l2cache_size(void)
115 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
116 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
117 u32 ver = SVR_SOC_VER(get_svr());
119 switch (l2siz_field) {
123 if (ver == SVR_8540 || ver == SVR_8560 ||
124 ver == SVR_8541 || ver == SVR_8541_E ||
125 ver == SVR_8555 || ver == SVR_8555_E)
131 if (ver == SVR_8540 || ver == SVR_8560 ||
132 ver == SVR_8541 || ver == SVR_8541_E ||
133 ver == SVR_8555 || ver == SVR_8555_E)
146 static inline void ft_fixup_l2cache(void *blob)
150 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
153 const u32 line_size = 32;
154 const u32 num_ways = 8;
155 const u32 size = l2cache_size() * 1024;
156 const u32 num_sets = size / (line_size * num_ways);
158 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
160 debug("no cpu node fount\n");
164 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
167 debug("no next-level-cache property\n");
171 off = fdt_node_offset_by_phandle(blob, *ph);
173 printf("%s: %s\n", __func__, fdt_strerror(off));
178 if (isdigit(cpu->name[0]))
179 len = sprintf(compat_buf,
180 "fsl,mpc%s-l2-cache-controller", cpu->name);
182 len = sprintf(compat_buf,
183 "fsl,%c%s-l2-cache-controller",
184 tolower(cpu->name[0]), cpu->name + 1);
186 sprintf(&compat_buf[len + 1], "cache");
188 fdt_setprop(blob, off, "cache-unified", NULL, 0);
189 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
190 fdt_setprop_cell(blob, off, "cache-size", size);
191 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
192 fdt_setprop_cell(blob, off, "cache-level", 2);
193 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
195 /* we dont bother w/L3 since no platform of this type has one */
197 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
198 static inline void ft_fixup_l2cache(void *blob)
200 int off, l2_off, l3_off = -1;
202 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
203 u32 size, line_size, num_ways, num_sets;
205 size = (l2cfg0 & 0x3fff) * 64 * 1024;
206 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
207 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
208 num_sets = size / (line_size * num_ways);
210 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
212 while (off != -FDT_ERR_NOTFOUND) {
213 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
216 debug("no next-level-cache property\n");
220 l2_off = fdt_node_offset_by_phandle(blob, *ph);
222 printf("%s: %s\n", __func__, fdt_strerror(off));
226 #ifdef CONFIG_SYS_CACHE_STASHING
228 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
230 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
231 (*reg * 2) + 32 + 1);
235 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
236 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
237 fdt_setprop_cell(blob, l2_off, "cache-size", size);
238 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
239 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
240 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
243 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
246 debug("no next-level-cache property\n");
252 off = fdt_node_offset_by_prop_value(blob, off,
253 "device_type", "cpu", 4);
256 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
258 printf("%s: %s\n", __func__, fdt_strerror(off));
261 ft_fixup_l3cache(blob, l3_off);
265 #define ft_fixup_l2cache(x)
268 static inline void ft_fixup_cache(void *blob)
272 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
274 while (off != -FDT_ERR_NOTFOUND) {
275 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
276 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
277 u32 isize, iline_size, inum_sets, inum_ways;
278 u32 dsize, dline_size, dnum_sets, dnum_ways;
281 dsize = (l1cfg0 & 0x7ff) * 1024;
282 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
283 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
284 dnum_sets = dsize / (dline_size * dnum_ways);
286 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
287 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
288 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
290 #ifdef CONFIG_SYS_CACHE_STASHING
292 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
294 fdt_setprop_cell(blob, off, "cache-stash-id",
295 (*reg * 2) + 32 + 0);
300 isize = (l1cfg1 & 0x7ff) * 1024;
301 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
302 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
303 inum_sets = isize / (iline_size * inum_ways);
305 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
306 fdt_setprop_cell(blob, off, "i-cache-size", isize);
307 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
309 off = fdt_node_offset_by_prop_value(blob, off,
310 "device_type", "cpu", 4);
313 ft_fixup_l2cache(blob);
317 void fdt_add_enet_stashing(void *fdt)
319 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
321 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
323 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
326 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
327 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
330 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
331 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
334 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
336 printf("WARNING enable to set clock-frequency "
337 "for %s: %s\n", compat, fdt_strerror(off));
341 static void ft_fixup_dpaa_clks(void *blob)
345 get_sys_info(&sysinfo);
346 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
347 sysinfo.freqFMan[0]);
349 #if (CONFIG_SYS_NUM_FMAN == 2)
350 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
351 sysinfo.freqFMan[1]);
354 #ifdef CONFIG_SYS_DPAA_PME
355 do_fixup_by_compat_u32(blob, "fsl,pme",
356 "clock-frequency", sysinfo.freqPME, 1);
360 #define ft_fixup_dpaa_clks(x)
364 static void ft_fixup_qe_snum(void *blob)
368 svr = mfspr(SPRN_SVR);
369 if (SVR_SOC_VER(svr) == SVR_8569_E) {
370 if(IS_SVR_REV(svr, 1, 0))
371 do_fixup_by_compat_u32(blob, "fsl,qe",
372 "fsl,qe-num-snums", 46, 1);
374 do_fixup_by_compat_u32(blob, "fsl,qe",
375 "fsl,qe-num-snums", 76, 1);
380 void ft_cpu_setup(void *blob, bd_t *bd)
386 /* delete crypto node if not on an E-processor */
387 if (!IS_E_PROCESSOR(get_svr()))
388 fdt_fixup_crypto_node(blob, 0);
390 fdt_fixup_ethernet(blob);
392 fdt_add_enet_stashing(blob);
394 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
395 "timebase-frequency", get_tbclk(), 1);
396 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
397 "bus-frequency", bd->bi_busfreq, 1);
398 get_sys_info(&sysinfo);
399 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
400 while (off != -FDT_ERR_NOTFOUND) {
401 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
402 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
403 fdt_setprop(blob, off, "clock-frequency", &val, 4);
404 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
407 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
408 "bus-frequency", bd->bi_busfreq, 1);
410 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
411 "bus-frequency", gd->lbc_clk, 1);
412 do_fixup_by_compat_u32(blob, "fsl,elbc",
413 "bus-frequency", gd->lbc_clk, 1);
416 ft_fixup_qe_snum(blob);
419 #ifdef CONFIG_SYS_NS16550
420 do_fixup_by_compat_u32(blob, "ns16550",
421 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
425 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
426 "current-speed", bd->bi_baudrate, 1);
428 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
429 "clock-frequency", bd->bi_brgfreq, 1);
432 #ifdef CONFIG_FSL_CORENET
433 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
434 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
437 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
440 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
441 ft_fixup_num_cores(blob);
444 ft_fixup_cache(blob);
446 #if defined(CONFIG_FSL_ESDHC)
447 fdt_fixup_esdhc(blob, bd);
450 ft_fixup_dpaa_clks(blob);
452 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
453 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
454 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
455 CONFIG_SYS_BMAN_MEM_SIZE);
458 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
459 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
460 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
461 CONFIG_SYS_QMAN_MEM_SIZE);
463 fdt_fixup_qportals(blob);