arch/powerpc/cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <libfdt.h>
  12 #include <fdt_support.h>
  13 #include <asm/processor.h>
  14 #include <linux/ctype.h>
  15 #include <asm/io.h>
  16 #include <asm/fsl_fdt.h>
  17 #include <asm/fsl_portals.h>
  18 #include <hwconfig.h>
  19 #ifdef CONFIG_FSL_ESDHC
  20 #include <fsl_esdhc.h>
  21 #endif
  22 #ifdef CONFIG_SYS_DPAA_FMAN
  23 #include <fsl_fman.h>
  24 #endif
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 extern void ft_qe_setup(void *blob);
  29 extern void ft_fixup_num_cores(void *blob);
  30 extern void ft_srio_setup(void *blob);
  31
  32 #ifdef CONFIG_MP
  33 #include "mp.h"
  34
  35 void ft_fixup_cpu(void *blob, u64 memory_limit)
  36 {
  37         int off;
  38         phys_addr_t spin_tbl_addr = get_spin_phys_addr();
  39         u32 bootpg = determine_mp_bootpg(NULL);
  40         u32 id = get_my_id();
  41         const char *enable_method;
  42 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  43         int ret;
  44         int tdm_hwconfig_enabled = 0;
  45         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  46 #endif
  47
  48         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  49         while (off != -FDT_ERR_NOTFOUND) {
  50                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  51
  52                 if (reg) {
  53                         u32 phys_cpu_id = thread_to_core(*reg);
  54                         u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
  55                         val = cpu_to_fdt64(val);
  56                         if (*reg == id) {
  57                                 fdt_setprop_string(blob, off, "status",
  58                                                                 "okay");
  59                         } else {
  60                                 fdt_setprop_string(blob, off, "status",
  61                                                                 "disabled");
  62                         }
  63
  64                         if (hold_cores_in_reset(0)) {
  65 #ifdef CONFIG_FSL_CORENET
  66                                 /* Cores held in reset, use BRR to release */
  67                                 enable_method = "fsl,brr-holdoff";
  68 #else
  69                                 /* Cores held in reset, use EEBPCR to release */
  70                                 enable_method = "fsl,eebpcr-holdoff";
  71 #endif
  72                         } else {
  73                                 /* Cores out of reset and in a spin-loop */
  74                                 enable_method = "spin-table";
  75
  76                                 fdt_setprop(blob, off, "cpu-release-addr",
  77                                                 &val, sizeof(val));
  78                         }
  79
  80                         fdt_setprop_string(blob, off, "enable-method",
  81                                                         enable_method);
  82                 } else {
  83                         printf ("cpu NULL\n");
  84                 }
  85                 off = fdt_node_offset_by_prop_value(blob, off,
  86                                 "device_type", "cpu", 4);
  87         }
  88
  89 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  90 #define CONFIG_MEM_HOLE_16M     0x1000000
  91         /*
  92          * Extract hwconfig from environment.
  93          * Search for tdm entry in hwconfig.
  94          */
  95         ret = getenv_f("hwconfig", buffer, sizeof(buffer));
  96         if (ret > 0)
  97                 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  98
  99         /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
 100         if (tdm_hwconfig_enabled) {
 101                 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
 102                                       CONFIG_MEM_HOLE_16M);
 103                 if (off < 0)
 104                         printf("Failed  to reserve memory for tdm: %s\n",
 105                                fdt_strerror(off));
 106         }
 107 #endif
 108
 109         /* Reserve the boot page so OSes dont use it */
 110         if ((u64)bootpg < memory_limit) {
 111                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 112                 if (off < 0)
 113                         printf("Failed to reserve memory for bootpg: %s\n",
 114                                 fdt_strerror(off));
 115         }
 116
 117 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
 118         /*
 119          * Reserve the default boot page so OSes dont use it.
 120          * The default boot page is always mapped to bootpg above using
 121          * boot page translation.
 122          */
 123         if (0xfffff000ull < memory_limit) {
 124                 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
 125                 if (off < 0) {
 126                         printf("Failed to reserve memory for 0xfffff000: %s\n",
 127                                 fdt_strerror(off));
 128                 }
 129         }
 130 #endif
 131
 132         /* Reserve spin table page */
 133         if (spin_tbl_addr < memory_limit) {
 134                 off = fdt_add_mem_rsv(blob,
 135                         (spin_tbl_addr & ~0xffful), 4096);
 136                 if (off < 0)
 137                         printf("Failed to reserve memory for spin table: %s\n",
 138                                 fdt_strerror(off));
 139         }
 140 #ifdef CONFIG_DEEP_SLEEP
 141 #ifdef CONFIG_SPL_MMC_BOOT
 142         off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
 143                 CONFIG_SYS_MMC_U_BOOT_SIZE);
 144         if (off < 0)
 145                 printf("Failed to reserve memory for SD deep sleep: %s\n",
 146                        fdt_strerror(off));
 147 #elif defined(CONFIG_SPL_SPI_BOOT)
 148         off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
 149                 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
 150         if (off < 0)
 151                 printf("Failed to reserve memory for SPI deep sleep: %s\n",
 152                        fdt_strerror(off));
 153 #endif
 154 #endif
 155 }
 156 #endif
 157
 158 #ifdef CONFIG_SYS_FSL_CPC
 159 static inline void ft_fixup_l3cache(void *blob, int off)
 160 {
 161         u32 line_size, num_ways, size, num_sets;
 162         cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
 163         u32 cfg0 = in_be32(&cpc->cpccfg0);
 164
 165         size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
 166         num_ways = CPC_CFG0_NUM_WAYS(cfg0);
 167         line_size = CPC_CFG0_LINE_SZ(cfg0);
 168         num_sets = size / (line_size * num_ways);
 169
 170         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 171         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 172         fdt_setprop_cell(blob, off, "cache-size", size);
 173         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 174         fdt_setprop_cell(blob, off, "cache-level", 3);
 175 #ifdef CONFIG_SYS_CACHE_STASHING
 176         fdt_setprop_cell(blob, off, "cache-stash-id", 1);
 177 #endif
 178 }
 179 #else
 180 #define ft_fixup_l3cache(x, y)
 181 #endif
 182
 183 #if defined(CONFIG_L2_CACHE)
 184 /* return size in kilobytes */
 185 static inline u32 l2cache_size(void)
 186 {
 187         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 188         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
 189         u32 ver = SVR_SOC_VER(get_svr());
 190
 191         switch (l2siz_field) {
 192         case 0x0:
 193                 break;
 194         case 0x1:
 195                 if (ver == SVR_8540 || ver == SVR_8560   ||
 196                     ver == SVR_8541 || ver == SVR_8555)
 197                         return 128;
 198                 else
 199                         return 256;
 200                 break;
 201         case 0x2:
 202                 if (ver == SVR_8540 || ver == SVR_8560   ||
 203                     ver == SVR_8541 || ver == SVR_8555)
 204                         return 256;
 205                 else
 206                         return 512;
 207                 break;
 208         case 0x3:
 209                 return 1024;
 210                 break;
 211         }
 212
 213         return 0;
 214 }
 215
 216 static inline void ft_fixup_l2cache(void *blob)
 217 {
 218         int len, off;
 219         u32 *ph;
 220         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 221
 222         const u32 line_size = 32;
 223         const u32 num_ways = 8;
 224         const u32 size = l2cache_size() * 1024;
 225         const u32 num_sets = size / (line_size * num_ways);
 226
 227         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 228         if (off < 0) {
 229                 debug("no cpu node fount\n");
 230                 return;
 231         }
 232
 233         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 234
 235         if (ph == NULL) {
 236                 debug("no next-level-cache property\n");
 237                 return ;
 238         }
 239
 240         off = fdt_node_offset_by_phandle(blob, *ph);
 241         if (off < 0) {
 242                 printf("%s: %s\n", __func__, fdt_strerror(off));
 243                 return ;
 244         }
 245
 246         if (cpu) {
 247                 char buf[40];
 248
 249                 if (isdigit(cpu->name[0])) {
 250                         /* MPCxxxx, where xxxx == 4-digit number */
 251                         len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
 252                                 cpu->name) + 1;
 253                 } else {
 254                         /* Pxxxx or Txxxx, where xxxx == 4-digit number */
 255                         len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
 256                                 tolower(cpu->name[0]), cpu->name + 1) + 1;
 257                 }
 258
 259                 /*
 260                  * append "cache" after the NULL character that the previous
 261                  * sprintf wrote.  This is how a device tree stores multiple
 262                  * strings in a property.
 263                  */
 264                 len += sprintf(buf + len, "cache") + 1;
 265
 266                 fdt_setprop(blob, off, "compatible", buf, len);
 267         }
 268         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 269         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 270         fdt_setprop_cell(blob, off, "cache-size", size);
 271         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 272         fdt_setprop_cell(blob, off, "cache-level", 2);
 273
 274         /* we dont bother w/L3 since no platform of this type has one */
 275 }
 276 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
 277         defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 278 static inline void ft_fixup_l2cache(void *blob)
 279 {
 280         int off, l2_off, l3_off = -1;
 281         u32 *ph;
 282 #ifdef  CONFIG_BACKSIDE_L2_CACHE
 283         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 284 #else
 285         struct ccsr_cluster_l2 *l2cache =
 286                 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
 287         u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
 288 #endif
 289         u32 size, line_size, num_ways, num_sets;
 290         int has_l2 = 1;
 291
 292         /* P2040/P2040E has no L2, so dont set any L2 props */
 293         if (SVR_SOC_VER(get_svr()) == SVR_P2040)
 294                 has_l2 = 0;
 295
 296         size = (l2cfg0 & 0x3fff) * 64 * 1024;
 297         num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 298         line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 299         num_sets = size / (line_size * num_ways);
 300
 301         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 302
 303         while (off != -FDT_ERR_NOTFOUND) {
 304                 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 305
 306                 if (ph == NULL) {
 307                         debug("no next-level-cache property\n");
 308                         goto next;
 309                 }
 310
 311                 l2_off = fdt_node_offset_by_phandle(blob, *ph);
 312                 if (l2_off < 0) {
 313                         printf("%s: %s\n", __func__, fdt_strerror(off));
 314                         goto next;
 315                 }
 316
 317                 if (has_l2) {
 318 #ifdef CONFIG_SYS_CACHE_STASHING
 319                         u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 320 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 321                         /* Only initialize every eighth thread */
 322                         if (reg && !((*reg) % 8)) {
 323                                 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 324                                                  (*reg / 4) + 32 + 1);
 325                         }
 326 #else
 327                         if (reg) {
 328                                 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 329                                                  (*reg * 2) + 32 + 1);
 330                         }
 331 #endif
 332 #endif
 333
 334                         fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 335                         fdt_setprop_cell(blob, l2_off, "cache-block-size",
 336                                                 line_size);
 337                         fdt_setprop_cell(blob, l2_off, "cache-size", size);
 338                         fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 339                         fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 340                         fdt_setprop(blob, l2_off, "compatible", "cache", 6);
 341                 }
 342
 343                 if (l3_off < 0) {
 344                         ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 345
 346                         if (ph == NULL) {
 347                                 debug("no next-level-cache property\n");
 348                                 goto next;
 349                         }
 350                         l3_off = *ph;
 351                 }
 352 next:
 353                 off = fdt_node_offset_by_prop_value(blob, off,
 354                                 "device_type", "cpu", 4);
 355         }
 356         if (l3_off > 0) {
 357                 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 358                 if (l3_off < 0) {
 359                         printf("%s: %s\n", __func__, fdt_strerror(off));
 360                         return ;
 361                 }
 362                 ft_fixup_l3cache(blob, l3_off);
 363         }
 364 }
 365 #else
 366 #define ft_fixup_l2cache(x)
 367 #endif
 368
 369 static inline void ft_fixup_cache(void *blob)
 370 {
 371         int off;
 372
 373         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 374
 375         while (off != -FDT_ERR_NOTFOUND) {
 376                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 377                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 378                 u32 isize, iline_size, inum_sets, inum_ways;
 379                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 380
 381                 /* d-side config */
 382                 dsize = (l1cfg0 & 0x7ff) * 1024;
 383                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 384                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 385                 dnum_sets = dsize / (dline_size * dnum_ways);
 386
 387                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 388                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 389                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 390
 391 #ifdef CONFIG_SYS_CACHE_STASHING
 392                 {
 393                         u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 394                         if (reg)
 395                                 fdt_setprop_cell(blob, off, "cache-stash-id",
 396                                          (*reg * 2) + 32 + 0);
 397                 }
 398 #endif
 399
 400                 /* i-side config */
 401                 isize = (l1cfg1 & 0x7ff) * 1024;
 402                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 403                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 404                 inum_sets = isize / (iline_size * inum_ways);
 405
 406                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 407                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 408                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 409
 410                 off = fdt_node_offset_by_prop_value(blob, off,
 411                                 "device_type", "cpu", 4);
 412         }
 413
 414         ft_fixup_l2cache(blob);
 415 }
 416
 417
 418 void fdt_add_enet_stashing(void *fdt)
 419 {
 420         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 421
 422         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 423
 424         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 425         do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
 426         do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
 427         do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
 428 }
 429
 430 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
 431 #ifdef CONFIG_SYS_DPAA_FMAN
 432 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 433                           unsigned long freq)
 434 {
 435         phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
 436         int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 437
 438         if (off >= 0) {
 439                 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
 440                 if (off > 0)
 441                         printf("WARNING enable to set clock-frequency "
 442                                 "for %s: %s\n", compat, fdt_strerror(off));
 443         }
 444 }
 445 #endif
 446
 447 static void ft_fixup_dpaa_clks(void *blob)
 448 {
 449         sys_info_t sysinfo;
 450
 451         get_sys_info(&sysinfo);
 452 #ifdef CONFIG_SYS_DPAA_FMAN
 453         ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
 454                         sysinfo.freq_fman[0]);
 455
 456 #if (CONFIG_SYS_NUM_FMAN == 2)
 457         ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
 458                         sysinfo.freq_fman[1]);
 459 #endif
 460 #endif
 461
 462 #ifdef CONFIG_SYS_DPAA_QBMAN
 463         do_fixup_by_compat_u32(blob, "fsl,qman",
 464                         "clock-frequency", sysinfo.freq_qman, 1);
 465 #endif
 466
 467 #ifdef CONFIG_SYS_DPAA_PME
 468         do_fixup_by_compat_u32(blob, "fsl,pme",
 469                 "clock-frequency", sysinfo.freq_pme, 1);
 470 #endif
 471 }
 472 #else
 473 #define ft_fixup_dpaa_clks(x)
 474 #endif
 475
 476 #ifdef CONFIG_QE
 477 static void ft_fixup_qe_snum(void *blob)
 478 {
 479         unsigned int svr;
 480
 481         svr = mfspr(SPRN_SVR);
 482         if (SVR_SOC_VER(svr) == SVR_8569) {
 483                 if(IS_SVR_REV(svr, 1, 0))
 484                         do_fixup_by_compat_u32(blob, "fsl,qe",
 485                                 "fsl,qe-num-snums", 46, 1);
 486                 else
 487                         do_fixup_by_compat_u32(blob, "fsl,qe",
 488                                 "fsl,qe-num-snums", 76, 1);
 489         }
 490 }
 491 #endif
 492
 493 #if defined(CONFIG_PPC_P4080)
 494 static void fdt_fixup_usb(void *fdt)
 495 {
 496         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 497         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 498         int off;
 499
 500         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
 501         if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
 502                                 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
 503                 fdt_status_disabled(fdt, off);
 504
 505         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
 506         if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
 507                                 FSL_CORENET_RCWSR11_EC2_USB2)
 508                 fdt_status_disabled(fdt, off);
 509 }
 510 #else
 511 #define fdt_fixup_usb(x)
 512 #endif
 513
 514 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
 515         defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 516 void fdt_fixup_dma3(void *blob)
 517 {
 518         /* the 3rd DMA is not functional if SRIO2 is chosen */
 519         int nodeoff;
 520         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 521
 522 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 523 #if defined(CONFIG_PPC_T2080)
 524         u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 525                                     FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 526         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 527
 528         switch (srds_prtcl_s2) {
 529         case 0x29:
 530         case 0x2d:
 531         case 0x2e:
 532 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
 533         defined(CONFIG_PPC_T4080)
 534         u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
 535                                     FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 536         srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
 537
 538         switch (srds_prtcl_s4) {
 539         case 6:
 540         case 8:
 541         case 14:
 542         case 16:
 543 #endif
 544                 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
 545                                                         CONFIG_SYS_ELO3_DMA3);
 546                 if (nodeoff > 0)
 547                         fdt_status_disabled(blob, nodeoff);
 548                 else
 549                         printf("WARNING: unable to disable dma3\n");
 550                 break;
 551         default:
 552                 break;
 553         }
 554 }
 555 #else
 556 #define fdt_fixup_dma3(x)
 557 #endif
 558
 559 #if defined(CONFIG_PPC_T1040)
 560 static void fdt_fixup_l2_switch(void *blob)
 561 {
 562         uchar l2swaddr[6];
 563         int node;
 564
 565         /* The l2switch node from device-tree has
 566          * compatible string "vitesse-9953" */
 567         node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
 568         if (node == -FDT_ERR_NOTFOUND)
 569                 /* no l2switch node has been found */
 570                 return;
 571
 572         /* Get MAC address for the l2switch from "l2switchaddr"*/
 573         if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) {
 574                 printf("Warning: MAC address for l2switch not found\n");
 575                 memset(l2swaddr, 0, sizeof(l2swaddr));
 576         }
 577
 578         /* Add MAC address to l2switch node */
 579         fdt_setprop(blob, node, "local-mac-address", l2swaddr,
 580                     sizeof(l2swaddr));
 581 }
 582 #else
 583 #define fdt_fixup_l2_switch(x)
 584 #endif
 585
 586 void ft_cpu_setup(void *blob, bd_t *bd)
 587 {
 588         int off;
 589         int val;
 590         int len;
 591         sys_info_t sysinfo;
 592
 593         /* delete crypto node if not on an E-processor */
 594         if (!IS_E_PROCESSOR(get_svr()))
 595                 fdt_fixup_crypto_node(blob, 0);
 596 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 597         else {
 598                 ccsr_sec_t __iomem *sec;
 599
 600                 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 601                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 602         }
 603 #endif
 604
 605         fdt_fixup_ethernet(blob);
 606
 607         fdt_add_enet_stashing(blob);
 608
 609 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
 610 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
 611 #endif
 612         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 613                 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
 614                 1);
 615         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 616                 "bus-frequency", bd->bi_busfreq, 1);
 617         get_sys_info(&sysinfo);
 618         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 619         while (off != -FDT_ERR_NOTFOUND) {
 620                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
 621                 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
 622                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 623                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 624                                                         "cpu", 4);
 625         }
 626         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 627                 "bus-frequency", bd->bi_busfreq, 1);
 628
 629         do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
 630                 "bus-frequency", gd->arch.lbc_clk, 1);
 631         do_fixup_by_compat_u32(blob, "fsl,elbc",
 632                 "bus-frequency", gd->arch.lbc_clk, 1);
 633 #ifdef CONFIG_QE
 634         ft_qe_setup(blob);
 635         ft_fixup_qe_snum(blob);
 636 #endif
 637
 638 #ifdef CONFIG_SYS_DPAA_FMAN
 639         fdt_fixup_fman_firmware(blob);
 640 #endif
 641
 642 #ifdef CONFIG_SYS_NS16550
 643         do_fixup_by_compat_u32(blob, "ns16550",
 644                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 645 #endif
 646
 647 #ifdef CONFIG_CPM2
 648         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 649                 "current-speed", gd->baudrate, 1);
 650
 651         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 652                 "clock-frequency", bd->bi_brgfreq, 1);
 653 #endif
 654
 655 #ifdef CONFIG_FSL_CORENET
 656         do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 657                 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 658         do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
 659                 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 660         do_fixup_by_compat_u32(blob, "fsl,mpic",
 661                 "clock-frequency", get_bus_freq(0)/2, 1);
 662 #else
 663         do_fixup_by_compat_u32(blob, "fsl,mpic",
 664                 "clock-frequency", get_bus_freq(0), 1);
 665 #endif
 666
 667         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 668
 669 #ifdef CONFIG_MP
 670         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 671         ft_fixup_num_cores(blob);
 672 #endif
 673
 674         ft_fixup_cache(blob);
 675
 676 #if defined(CONFIG_FSL_ESDHC)
 677         fdt_fixup_esdhc(blob, bd);
 678 #endif
 679
 680         ft_fixup_dpaa_clks(blob);
 681
 682 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
 683         fdt_portal(blob, "fsl,bman-portal", "bman-portals",
 684                         (u64)CONFIG_SYS_BMAN_MEM_PHYS,
 685                         CONFIG_SYS_BMAN_MEM_SIZE);
 686         fdt_fixup_bportals(blob);
 687 #endif
 688
 689 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
 690         fdt_portal(blob, "fsl,qman-portal", "qman-portals",
 691                         (u64)CONFIG_SYS_QMAN_MEM_PHYS,
 692                         CONFIG_SYS_QMAN_MEM_SIZE);
 693
 694         fdt_fixup_qportals(blob);
 695 #endif
 696
 697 #ifdef CONFIG_SYS_SRIO
 698         ft_srio_setup(blob);
 699 #endif
 700
 701         /*
 702          * system-clock = CCB clock/2
 703          * Here gd->bus_clk = CCB clock
 704          * We are using the system clock as 1588 Timer reference
 705          * clock source select
 706          */
 707         do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
 708                         "timer-frequency", gd->bus_clk/2, 1);
 709
 710         /*
 711          * clock-freq should change to clock-frequency and
 712          * flexcan-v1.0 should change to p1010-flexcan respectively
 713          * in the future.
 714          */
 715         do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
 716                         "clock_freq", gd->bus_clk/2, 1);
 717
 718         do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
 719                         "clock-frequency", gd->bus_clk/2, 1);
 720
 721         do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
 722                         "clock-frequency", gd->bus_clk/2, 1);
 723
 724         fdt_fixup_usb(blob);
 725
 726         fdt_fixup_l2_switch(blob);
 727
 728         fdt_fixup_dma3(blob);
 729 }
 730
 731 /*
 732  * For some CCSR devices, we only have the virtual address, not the physical
 733  * address.  This is because we map CCSR as a whole, so we typically don't need
 734  * a macro for the physical address of any device within CCSR.  In this case,
 735  * we calculate the physical address of that device using it's the difference
 736  * between the virtual address of the device and the virtual address of the
 737  * beginning of CCSR.
 738  */
 739 #define CCSR_VIRT_TO_PHYS(x) \
 740         (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
 741
 742 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
 743 {
 744         printf("Warning: U-Boot configured %s at address %llx,\n"
 745                "but the device tree has it at %llx\n", name, uaddr, daddr);
 746 }
 747
 748 /*
 749  * Verify the device tree
 750  *
 751  * This function compares several CONFIG_xxx macros that contain physical
 752  * addresses with the corresponding nodes in the device tree, to see if
 753  * the physical addresses are all correct.  For example, if
 754  * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
 755  * of the first UART.  We convert this to a physical address and compare
 756  * that with the physical address of the first ns16550-compatible node
 757  * in the device tree.  If they don't match, then we display a warning.
 758  *
 759  * Returns 1 on success, 0 on failure
 760  */
 761 int ft_verify_fdt(void *fdt)
 762 {
 763         uint64_t addr = 0;
 764         int aliases;
 765         int off;
 766
 767         /* First check the CCSR base address */
 768         off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
 769         if (off > 0)
 770                 addr = fdt_get_base_address(fdt, off);
 771
 772         if (!addr) {
 773                 printf("Warning: could not determine base CCSR address in "
 774                        "device tree\n");
 775                 /* No point in checking anything else */
 776                 return 0;
 777         }
 778
 779         if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
 780                 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
 781                 /* No point in checking anything else */
 782                 return 0;
 783         }
 784
 785         /*
 786          * Check some nodes via aliases.  We assume that U-Boot and the device
 787          * tree enumerate the devices equally.  E.g. the first serial port in
 788          * U-Boot is the same as "serial0" in the device tree.
 789          */
 790         aliases = fdt_path_offset(fdt, "/aliases");
 791         if (aliases > 0) {
 792 #ifdef CONFIG_SYS_NS16550_COM1
 793                 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
 794                         CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
 795                         return 0;
 796 #endif
 797
 798 #ifdef CONFIG_SYS_NS16550_COM2
 799                 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
 800                         CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
 801                         return 0;
 802 #endif
 803         }
 804
 805         /*
 806          * The localbus node is typically a root node, even though the lbc
 807          * controller is part of CCSR.  If we were to put the lbc node under
 808          * the SOC node, then the 'ranges' property in the lbc node would
 809          * translate through the 'ranges' property of the parent SOC node, and
 810          * we don't want that.  Since it's a separate node, it's possible for
 811          * the 'reg' property to be wrong, so check it here.  For now, we
 812          * only check for "fsl,elbc" nodes.
 813          */
 814 #ifdef CONFIG_SYS_LBC_ADDR
 815         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 816         if (off > 0) {
 817                 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 818                 if (reg) {
 819                         uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
 820
 821                         addr = fdt_translate_address(fdt, off, reg);
 822                         if (uaddr != addr) {
 823                                 msg("the localbus", uaddr, addr);
 824                                 return 0;
 825                         }
 826                 }
 827         }
 828 #endif
 829
 830         return 1;
 831 }
 832
 833 void fdt_del_diu(void *blob)
 834 {
 835         int nodeoff = 0;
 836
 837         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 838                                 "fsl,diu")) >= 0) {
 839                 fdt_del_node(blob, nodeoff);
 840         }
 841 }