2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <environment.h>
12 #include <linux/libfdt.h>
13 #include <fdt_support.h>
14 #include <asm/processor.h>
15 #include <linux/ctype.h>
17 #include <asm/fsl_fdt.h>
18 #include <asm/fsl_portals.h>
19 #include <fsl_qbman.h>
21 #ifdef CONFIG_FSL_ESDHC
22 #include <fsl_esdhc.h>
24 #ifdef CONFIG_SYS_DPAA_FMAN
28 DECLARE_GLOBAL_DATA_PTR;
30 extern void ft_qe_setup(void *blob);
31 extern void ft_fixup_num_cores(void *blob);
32 extern void ft_srio_setup(void *blob);
37 void ft_fixup_cpu(void *blob, u64 memory_limit)
40 phys_addr_t spin_tbl_addr = get_spin_phys_addr();
41 u32 bootpg = determine_mp_bootpg(NULL);
43 const char *enable_method;
44 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
46 int tdm_hwconfig_enabled = 0;
47 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
50 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
51 while (off != -FDT_ERR_NOTFOUND) {
52 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
55 u32 phys_cpu_id = thread_to_core(*reg);
56 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
57 val = cpu_to_fdt64(val);
59 fdt_setprop_string(blob, off, "status",
62 fdt_setprop_string(blob, off, "status",
66 if (hold_cores_in_reset(0)) {
67 #ifdef CONFIG_FSL_CORENET
68 /* Cores held in reset, use BRR to release */
69 enable_method = "fsl,brr-holdoff";
71 /* Cores held in reset, use EEBPCR to release */
72 enable_method = "fsl,eebpcr-holdoff";
75 /* Cores out of reset and in a spin-loop */
76 enable_method = "spin-table";
78 fdt_setprop(blob, off, "cpu-release-addr",
82 fdt_setprop_string(blob, off, "enable-method",
85 printf ("cpu NULL\n");
87 off = fdt_node_offset_by_prop_value(blob, off,
88 "device_type", "cpu", 4);
91 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
92 #define CONFIG_MEM_HOLE_16M 0x1000000
94 * Extract hwconfig from environment.
95 * Search for tdm entry in hwconfig.
97 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
99 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
101 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
102 if (tdm_hwconfig_enabled) {
103 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
104 CONFIG_MEM_HOLE_16M);
106 printf("Failed to reserve memory for tdm: %s\n",
111 /* Reserve the boot page so OSes dont use it */
112 if ((u64)bootpg < memory_limit) {
113 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
115 printf("Failed to reserve memory for bootpg: %s\n",
119 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
121 * Reserve the default boot page so OSes dont use it.
122 * The default boot page is always mapped to bootpg above using
123 * boot page translation.
125 if (0xfffff000ull < memory_limit) {
126 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
128 printf("Failed to reserve memory for 0xfffff000: %s\n",
134 /* Reserve spin table page */
135 if (spin_tbl_addr < memory_limit) {
136 off = fdt_add_mem_rsv(blob,
137 (spin_tbl_addr & ~0xffful), 4096);
139 printf("Failed to reserve memory for spin table: %s\n",
142 #ifdef CONFIG_DEEP_SLEEP
143 #ifdef CONFIG_SPL_MMC_BOOT
144 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
145 CONFIG_SYS_MMC_U_BOOT_SIZE);
147 printf("Failed to reserve memory for SD deep sleep: %s\n",
149 #elif defined(CONFIG_SPL_SPI_BOOT)
150 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
151 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
153 printf("Failed to reserve memory for SPI deep sleep: %s\n",
160 #ifdef CONFIG_SYS_FSL_CPC
161 static inline void ft_fixup_l3cache(void *blob, int off)
163 u32 line_size, num_ways, size, num_sets;
164 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
165 u32 cfg0 = in_be32(&cpc->cpccfg0);
167 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
168 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
169 line_size = CPC_CFG0_LINE_SZ(cfg0);
170 num_sets = size / (line_size * num_ways);
172 fdt_setprop(blob, off, "cache-unified", NULL, 0);
173 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
174 fdt_setprop_cell(blob, off, "cache-size", size);
175 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
176 fdt_setprop_cell(blob, off, "cache-level", 3);
177 #ifdef CONFIG_SYS_CACHE_STASHING
178 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
182 #define ft_fixup_l3cache(x, y)
185 #if defined(CONFIG_L2_CACHE) || \
186 defined(CONFIG_BACKSIDE_L2_CACHE) || \
187 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
188 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
191 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
196 if (isdigit(cpu->name[0])) {
197 /* MPCxxxx, where xxxx == 4-digit number */
198 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
201 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
202 len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
203 tolower(cpu->name[0]), cpu->name + 1) + 1;
207 * append "cache" after the NULL character that the previous
208 * sprintf wrote. This is how a device tree stores multiple
209 * strings in a property.
211 len += sprintf(buf + len, "cache") + 1;
213 fdt_setprop(blob, off, "compatible", buf, len);
218 #if defined(CONFIG_L2_CACHE)
219 /* return size in kilobytes */
220 static inline u32 l2cache_size(void)
222 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
223 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
224 u32 ver = SVR_SOC_VER(get_svr());
226 switch (l2siz_field) {
230 if (ver == SVR_8540 || ver == SVR_8560 ||
231 ver == SVR_8541 || ver == SVR_8555)
237 if (ver == SVR_8540 || ver == SVR_8560 ||
238 ver == SVR_8541 || ver == SVR_8555)
251 static inline void ft_fixup_l2cache(void *blob)
256 const u32 line_size = 32;
257 const u32 num_ways = 8;
258 const u32 size = l2cache_size() * 1024;
259 const u32 num_sets = size / (line_size * num_ways);
261 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
263 debug("no cpu node fount\n");
267 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
270 debug("no next-level-cache property\n");
274 off = fdt_node_offset_by_phandle(blob, *ph);
276 printf("%s: %s\n", __func__, fdt_strerror(off));
280 ft_fixup_l2cache_compatible(blob, off);
281 fdt_setprop(blob, off, "cache-unified", NULL, 0);
282 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
283 fdt_setprop_cell(blob, off, "cache-size", size);
284 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
285 fdt_setprop_cell(blob, off, "cache-level", 2);
287 /* we dont bother w/L3 since no platform of this type has one */
289 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
290 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
291 static inline void ft_fixup_l2cache(void *blob)
293 int off, l2_off, l3_off = -1;
295 #ifdef CONFIG_BACKSIDE_L2_CACHE
296 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
298 struct ccsr_cluster_l2 *l2cache =
299 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
300 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
302 u32 size, line_size, num_ways, num_sets;
305 /* P2040/P2040E has no L2, so dont set any L2 props */
306 if (SVR_SOC_VER(get_svr()) == SVR_P2040)
309 size = (l2cfg0 & 0x3fff) * 64 * 1024;
310 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
311 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
312 num_sets = size / (line_size * num_ways);
314 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
316 while (off != -FDT_ERR_NOTFOUND) {
317 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
320 debug("no next-level-cache property\n");
324 l2_off = fdt_node_offset_by_phandle(blob, *ph);
326 printf("%s: %s\n", __func__, fdt_strerror(off));
331 #ifdef CONFIG_SYS_CACHE_STASHING
332 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
333 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
334 /* Only initialize every eighth thread */
335 if (reg && !((*reg) % 8)) {
336 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
337 (*reg / 4) + 32 + 1);
341 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
342 (*reg * 2) + 32 + 1);
347 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
348 fdt_setprop_cell(blob, l2_off, "cache-block-size",
350 fdt_setprop_cell(blob, l2_off, "cache-size", size);
351 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
352 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
353 ft_fixup_l2cache_compatible(blob, l2_off);
357 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
360 debug("no next-level-cache property\n");
366 off = fdt_node_offset_by_prop_value(blob, off,
367 "device_type", "cpu", 4);
370 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
372 printf("%s: %s\n", __func__, fdt_strerror(off));
375 ft_fixup_l3cache(blob, l3_off);
379 #define ft_fixup_l2cache(x)
382 static inline void ft_fixup_cache(void *blob)
386 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
388 while (off != -FDT_ERR_NOTFOUND) {
389 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
390 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
391 u32 isize, iline_size, inum_sets, inum_ways;
392 u32 dsize, dline_size, dnum_sets, dnum_ways;
395 dsize = (l1cfg0 & 0x7ff) * 1024;
396 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
397 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
398 dnum_sets = dsize / (dline_size * dnum_ways);
400 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
401 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
402 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
404 #ifdef CONFIG_SYS_CACHE_STASHING
406 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
408 fdt_setprop_cell(blob, off, "cache-stash-id",
409 (*reg * 2) + 32 + 0);
414 isize = (l1cfg1 & 0x7ff) * 1024;
415 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
416 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
417 inum_sets = isize / (iline_size * inum_ways);
419 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
420 fdt_setprop_cell(blob, off, "i-cache-size", isize);
421 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
423 off = fdt_node_offset_by_prop_value(blob, off,
424 "device_type", "cpu", 4);
427 ft_fixup_l2cache(blob);
431 void fdt_add_enet_stashing(void *fdt)
433 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
435 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
437 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
438 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
439 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
440 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
443 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
444 #ifdef CONFIG_SYS_DPAA_FMAN
445 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
448 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
449 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
452 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
454 printf("WARNING enable to set clock-frequency "
455 "for %s: %s\n", compat, fdt_strerror(off));
460 static void ft_fixup_dpaa_clks(void *blob)
464 get_sys_info(&sysinfo);
465 #ifdef CONFIG_SYS_DPAA_FMAN
466 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
467 sysinfo.freq_fman[0]);
469 #if (CONFIG_SYS_NUM_FMAN == 2)
470 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
471 sysinfo.freq_fman[1]);
475 #ifdef CONFIG_SYS_DPAA_QBMAN
476 do_fixup_by_compat_u32(blob, "fsl,qman",
477 "clock-frequency", sysinfo.freq_qman, 1);
480 #ifdef CONFIG_SYS_DPAA_PME
481 do_fixup_by_compat_u32(blob, "fsl,pme",
482 "clock-frequency", sysinfo.freq_pme, 1);
486 #define ft_fixup_dpaa_clks(x)
490 static void ft_fixup_qe_snum(void *blob)
494 svr = mfspr(SPRN_SVR);
495 if (SVR_SOC_VER(svr) == SVR_8569) {
496 if(IS_SVR_REV(svr, 1, 0))
497 do_fixup_by_compat_u32(blob, "fsl,qe",
498 "fsl,qe-num-snums", 46, 1);
500 do_fixup_by_compat_u32(blob, "fsl,qe",
501 "fsl,qe-num-snums", 76, 1);
506 #if defined(CONFIG_ARCH_P4080)
507 static void fdt_fixup_usb(void *fdt)
509 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
510 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
513 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
514 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
515 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
516 fdt_status_disabled(fdt, off);
518 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
519 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
520 FSL_CORENET_RCWSR11_EC2_USB2)
521 fdt_status_disabled(fdt, off);
524 #define fdt_fixup_usb(x)
527 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
528 defined(CONFIG_ARCH_T4160)
529 void fdt_fixup_dma3(void *blob)
531 /* the 3rd DMA is not functional if SRIO2 is chosen */
533 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
535 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
536 #if defined(CONFIG_ARCH_T2080)
537 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
538 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
539 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
541 switch (srds_prtcl_s2) {
545 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
546 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
547 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
548 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
550 switch (srds_prtcl_s4) {
556 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
557 CONFIG_SYS_ELO3_DMA3);
559 fdt_status_disabled(blob, nodeoff);
561 printf("WARNING: unable to disable dma3\n");
568 #define fdt_fixup_dma3(x)
571 #if defined(CONFIG_ARCH_T1040)
572 static void fdt_fixup_l2_switch(void *blob)
577 /* The l2switch node from device-tree has
578 * compatible string "vitesse-9953" */
579 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
580 if (node == -FDT_ERR_NOTFOUND)
581 /* no l2switch node has been found */
584 /* Get MAC address for the l2switch from "l2switchaddr"*/
585 if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
586 printf("Warning: MAC address for l2switch not found\n");
587 memset(l2swaddr, 0, sizeof(l2swaddr));
590 /* Add MAC address to l2switch node */
591 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
595 #define fdt_fixup_l2_switch(x)
598 void ft_cpu_setup(void *blob, bd_t *bd)
605 /* delete crypto node if not on an E-processor */
606 if (!IS_E_PROCESSOR(get_svr()))
607 fdt_fixup_crypto_node(blob, 0);
608 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
610 ccsr_sec_t __iomem *sec;
612 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
613 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
617 fdt_add_enet_stashing(blob);
619 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
620 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
622 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
623 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
625 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
626 "bus-frequency", bd->bi_busfreq, 1);
627 get_sys_info(&sysinfo);
628 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
629 while (off != -FDT_ERR_NOTFOUND) {
630 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
631 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
632 fdt_setprop(blob, off, "clock-frequency", &val, 4);
633 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
636 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
637 "bus-frequency", bd->bi_busfreq, 1);
641 ft_fixup_qe_snum(blob);
644 #ifdef CONFIG_SYS_DPAA_FMAN
645 fdt_fixup_fman_firmware(blob);
648 #ifdef CONFIG_SYS_NS16550
649 do_fixup_by_compat_u32(blob, "ns16550",
650 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
654 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
655 "current-speed", gd->baudrate, 1);
657 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
658 "clock-frequency", bd->bi_brgfreq, 1);
661 #ifdef CONFIG_FSL_CORENET
662 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
663 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
664 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
665 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
666 do_fixup_by_compat_u32(blob, "fsl,mpic",
667 "clock-frequency", get_bus_freq(0)/2, 1);
669 do_fixup_by_compat_u32(blob, "fsl,mpic",
670 "clock-frequency", get_bus_freq(0), 1);
673 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
676 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
677 ft_fixup_num_cores(blob);
680 ft_fixup_cache(blob);
682 #if defined(CONFIG_FSL_ESDHC)
683 fdt_fixup_esdhc(blob, bd);
686 ft_fixup_dpaa_clks(blob);
688 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
689 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
690 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
691 CONFIG_SYS_BMAN_MEM_SIZE);
692 fdt_fixup_bportals(blob);
695 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
696 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
697 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
698 CONFIG_SYS_QMAN_MEM_SIZE);
700 fdt_fixup_qportals(blob);
703 #ifdef CONFIG_SYS_SRIO
708 * system-clock = CCB clock/2
709 * Here gd->bus_clk = CCB clock
710 * We are using the system clock as 1588 Timer reference
711 * clock source select
713 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
714 "timer-frequency", gd->bus_clk/2, 1);
717 * clock-freq should change to clock-frequency and
718 * flexcan-v1.0 should change to p1010-flexcan respectively
721 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
722 "clock_freq", gd->bus_clk/2, 1);
724 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
725 "clock-frequency", gd->bus_clk/2, 1);
727 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
728 "clock-frequency", gd->bus_clk/2, 1);
732 fdt_fixup_l2_switch(blob);
734 fdt_fixup_dma3(blob);
738 * For some CCSR devices, we only have the virtual address, not the physical
739 * address. This is because we map CCSR as a whole, so we typically don't need
740 * a macro for the physical address of any device within CCSR. In this case,
741 * we calculate the physical address of that device using it's the difference
742 * between the virtual address of the device and the virtual address of the
745 #define CCSR_VIRT_TO_PHYS(x) \
746 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
748 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
750 printf("Warning: U-Boot configured %s at address %llx,\n"
751 "but the device tree has it at %llx\n", name, uaddr, daddr);
755 * Verify the device tree
757 * This function compares several CONFIG_xxx macros that contain physical
758 * addresses with the corresponding nodes in the device tree, to see if
759 * the physical addresses are all correct. For example, if
760 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
761 * of the first UART. We convert this to a physical address and compare
762 * that with the physical address of the first ns16550-compatible node
763 * in the device tree. If they don't match, then we display a warning.
765 * Returns 1 on success, 0 on failure
767 int ft_verify_fdt(void *fdt)
773 /* First check the CCSR base address */
774 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
780 naddr = fdt_address_cells(fdt, off);
781 prop = fdt_getprop(fdt, off, "ranges", &size);
782 addr = fdt_translate_address(fdt, off, prop + naddr);
786 printf("Warning: could not determine base CCSR address in "
788 /* No point in checking anything else */
792 if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
793 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
794 /* No point in checking anything else */
799 * Check some nodes via aliases. We assume that U-Boot and the device
800 * tree enumerate the devices equally. E.g. the first serial port in
801 * U-Boot is the same as "serial0" in the device tree.
803 aliases = fdt_path_offset(fdt, "/aliases");
805 #ifdef CONFIG_SYS_NS16550_COM1
806 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
807 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
811 #ifdef CONFIG_SYS_NS16550_COM2
812 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
813 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
819 * The localbus node is typically a root node, even though the lbc
820 * controller is part of CCSR. If we were to put the lbc node under
821 * the SOC node, then the 'ranges' property in the lbc node would
822 * translate through the 'ranges' property of the parent SOC node, and
823 * we don't want that. Since it's a separate node, it's possible for
824 * the 'reg' property to be wrong, so check it here. For now, we
825 * only check for "fsl,elbc" nodes.
827 #ifdef CONFIG_SYS_LBC_ADDR
828 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
830 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
832 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
834 addr = fdt_translate_address(fdt, off, reg);
836 msg("the localbus", uaddr, addr);
846 void fdt_del_diu(void *blob)
850 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
852 fdt_del_node(blob, nodeoff);