2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <fdt_support.h>
13 #include <asm/processor.h>
14 #include <linux/ctype.h>
16 #include <asm/fsl_portals.h>
18 #ifdef CONFIG_FSL_ESDHC
19 #include <fsl_esdhc.h>
21 #include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */
23 DECLARE_GLOBAL_DATA_PTR;
25 extern void ft_qe_setup(void *blob);
26 extern void ft_fixup_num_cores(void *blob);
27 extern void ft_srio_setup(void *blob);
32 void ft_fixup_cpu(void *blob, u64 memory_limit)
35 phys_addr_t spin_tbl_addr = get_spin_phys_addr();
36 u32 bootpg = determine_mp_bootpg(NULL);
38 const char *enable_method;
39 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
41 int tdm_hwconfig_enabled = 0;
42 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
45 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
46 while (off != -FDT_ERR_NOTFOUND) {
47 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
50 u32 phys_cpu_id = thread_to_core(*reg);
51 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
52 val = cpu_to_fdt64(val);
54 fdt_setprop_string(blob, off, "status",
57 fdt_setprop_string(blob, off, "status",
61 if (hold_cores_in_reset(0)) {
62 #ifdef CONFIG_FSL_CORENET
63 /* Cores held in reset, use BRR to release */
64 enable_method = "fsl,brr-holdoff";
66 /* Cores held in reset, use EEBPCR to release */
67 enable_method = "fsl,eebpcr-holdoff";
70 /* Cores out of reset and in a spin-loop */
71 enable_method = "spin-table";
73 fdt_setprop(blob, off, "cpu-release-addr",
77 fdt_setprop_string(blob, off, "enable-method",
80 printf ("cpu NULL\n");
82 off = fdt_node_offset_by_prop_value(blob, off,
83 "device_type", "cpu", 4);
86 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
87 #define CONFIG_MEM_HOLE_16M 0x1000000
89 * Extract hwconfig from environment.
90 * Search for tdm entry in hwconfig.
92 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
94 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
96 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
97 if (tdm_hwconfig_enabled) {
98 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
101 printf("Failed to reserve memory for tdm: %s\n",
106 /* Reserve the boot page so OSes dont use it */
107 if ((u64)bootpg < memory_limit) {
108 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
110 printf("Failed to reserve memory for bootpg: %s\n",
114 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
116 * Reserve the default boot page so OSes dont use it.
117 * The default boot page is always mapped to bootpg above using
118 * boot page translation.
120 if (0xfffff000ull < memory_limit) {
121 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
123 printf("Failed to reserve memory for 0xfffff000: %s\n",
129 /* Reserve spin table page */
130 if (spin_tbl_addr < memory_limit) {
131 off = fdt_add_mem_rsv(blob,
132 (spin_tbl_addr & ~0xffful), 4096);
134 printf("Failed to reserve memory for spin table: %s\n",
140 #ifdef CONFIG_SYS_FSL_CPC
141 static inline void ft_fixup_l3cache(void *blob, int off)
143 u32 line_size, num_ways, size, num_sets;
144 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
145 u32 cfg0 = in_be32(&cpc->cpccfg0);
147 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
148 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
149 line_size = CPC_CFG0_LINE_SZ(cfg0);
150 num_sets = size / (line_size * num_ways);
152 fdt_setprop(blob, off, "cache-unified", NULL, 0);
153 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
154 fdt_setprop_cell(blob, off, "cache-size", size);
155 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
156 fdt_setprop_cell(blob, off, "cache-level", 3);
157 #ifdef CONFIG_SYS_CACHE_STASHING
158 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
162 #define ft_fixup_l3cache(x, y)
165 #if defined(CONFIG_L2_CACHE)
166 /* return size in kilobytes */
167 static inline u32 l2cache_size(void)
169 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
170 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
171 u32 ver = SVR_SOC_VER(get_svr());
173 switch (l2siz_field) {
177 if (ver == SVR_8540 || ver == SVR_8560 ||
178 ver == SVR_8541 || ver == SVR_8555)
184 if (ver == SVR_8540 || ver == SVR_8560 ||
185 ver == SVR_8541 || ver == SVR_8555)
198 static inline void ft_fixup_l2cache(void *blob)
202 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
204 const u32 line_size = 32;
205 const u32 num_ways = 8;
206 const u32 size = l2cache_size() * 1024;
207 const u32 num_sets = size / (line_size * num_ways);
209 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
211 debug("no cpu node fount\n");
215 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
218 debug("no next-level-cache property\n");
222 off = fdt_node_offset_by_phandle(blob, *ph);
224 printf("%s: %s\n", __func__, fdt_strerror(off));
231 if (isdigit(cpu->name[0])) {
232 /* MPCxxxx, where xxxx == 4-digit number */
233 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
236 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
237 len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
238 tolower(cpu->name[0]), cpu->name + 1) + 1;
242 * append "cache" after the NULL character that the previous
243 * sprintf wrote. This is how a device tree stores multiple
244 * strings in a property.
246 len += sprintf(buf + len, "cache") + 1;
248 fdt_setprop(blob, off, "compatible", buf, len);
250 fdt_setprop(blob, off, "cache-unified", NULL, 0);
251 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
252 fdt_setprop_cell(blob, off, "cache-size", size);
253 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
254 fdt_setprop_cell(blob, off, "cache-level", 2);
256 /* we dont bother w/L3 since no platform of this type has one */
258 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
259 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
260 static inline void ft_fixup_l2cache(void *blob)
262 int off, l2_off, l3_off = -1;
264 #ifdef CONFIG_BACKSIDE_L2_CACHE
265 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
267 struct ccsr_cluster_l2 *l2cache =
268 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
269 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
271 u32 size, line_size, num_ways, num_sets;
274 /* P2040/P2040E has no L2, so dont set any L2 props */
275 if (SVR_SOC_VER(get_svr()) == SVR_P2040)
278 size = (l2cfg0 & 0x3fff) * 64 * 1024;
279 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
280 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
281 num_sets = size / (line_size * num_ways);
283 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
285 while (off != -FDT_ERR_NOTFOUND) {
286 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
289 debug("no next-level-cache property\n");
293 l2_off = fdt_node_offset_by_phandle(blob, *ph);
295 printf("%s: %s\n", __func__, fdt_strerror(off));
300 #ifdef CONFIG_SYS_CACHE_STASHING
301 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
302 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
303 /* Only initialize every eighth thread */
304 if (reg && !((*reg) % 8)) {
305 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
306 (*reg / 4) + 32 + 1);
310 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
311 (*reg * 2) + 32 + 1);
316 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
317 fdt_setprop_cell(blob, l2_off, "cache-block-size",
319 fdt_setprop_cell(blob, l2_off, "cache-size", size);
320 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
321 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
322 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
326 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
329 debug("no next-level-cache property\n");
335 off = fdt_node_offset_by_prop_value(blob, off,
336 "device_type", "cpu", 4);
339 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
341 printf("%s: %s\n", __func__, fdt_strerror(off));
344 ft_fixup_l3cache(blob, l3_off);
348 #define ft_fixup_l2cache(x)
351 static inline void ft_fixup_cache(void *blob)
355 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
357 while (off != -FDT_ERR_NOTFOUND) {
358 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
359 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
360 u32 isize, iline_size, inum_sets, inum_ways;
361 u32 dsize, dline_size, dnum_sets, dnum_ways;
364 dsize = (l1cfg0 & 0x7ff) * 1024;
365 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
366 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
367 dnum_sets = dsize / (dline_size * dnum_ways);
369 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
370 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
371 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
373 #ifdef CONFIG_SYS_CACHE_STASHING
375 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
377 fdt_setprop_cell(blob, off, "cache-stash-id",
378 (*reg * 2) + 32 + 0);
383 isize = (l1cfg1 & 0x7ff) * 1024;
384 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
385 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
386 inum_sets = isize / (iline_size * inum_ways);
388 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
389 fdt_setprop_cell(blob, off, "i-cache-size", isize);
390 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
392 off = fdt_node_offset_by_prop_value(blob, off,
393 "device_type", "cpu", 4);
396 ft_fixup_l2cache(blob);
400 void fdt_add_enet_stashing(void *fdt)
402 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
404 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
406 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
407 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
408 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
409 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
412 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
413 #ifdef CONFIG_SYS_DPAA_FMAN
414 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
417 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
418 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
421 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
423 printf("WARNING enable to set clock-frequency "
424 "for %s: %s\n", compat, fdt_strerror(off));
429 static void ft_fixup_dpaa_clks(void *blob)
433 get_sys_info(&sysinfo);
434 #ifdef CONFIG_SYS_DPAA_FMAN
435 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
436 sysinfo.freq_fman[0]);
438 #if (CONFIG_SYS_NUM_FMAN == 2)
439 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
440 sysinfo.freq_fman[1]);
444 #ifdef CONFIG_SYS_DPAA_QBMAN
445 do_fixup_by_compat_u32(blob, "fsl,qman",
446 "clock-frequency", sysinfo.freq_qman, 1);
449 #ifdef CONFIG_SYS_DPAA_PME
450 do_fixup_by_compat_u32(blob, "fsl,pme",
451 "clock-frequency", sysinfo.freq_pme, 1);
455 #define ft_fixup_dpaa_clks(x)
459 static void ft_fixup_qe_snum(void *blob)
463 svr = mfspr(SPRN_SVR);
464 if (SVR_SOC_VER(svr) == SVR_8569) {
465 if(IS_SVR_REV(svr, 1, 0))
466 do_fixup_by_compat_u32(blob, "fsl,qe",
467 "fsl,qe-num-snums", 46, 1);
469 do_fixup_by_compat_u32(blob, "fsl,qe",
470 "fsl,qe-num-snums", 76, 1);
476 * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
478 * The binding for an Fman firmware node is documented in
479 * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
480 * the actual Fman firmware binary data. The operating system is expected to
481 * be able to parse the binary data to determine any attributes it needs.
483 #ifdef CONFIG_SYS_DPAA_FMAN
484 void fdt_fixup_fman_firmware(void *blob)
486 int rc, fmnode, fwnode = -1;
488 struct qe_firmware *fmanfw;
489 const struct qe_header *hdr;
494 /* The first Fman we find will contain the actual firmware. */
495 fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
497 /* Exit silently if there are no Fman devices */
500 /* If we already have a firmware node, then also exit silently. */
501 if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
504 /* If the environment variable is not set, then exit silently */
505 p = getenv("fman_ucode");
509 fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16);
513 hdr = &fmanfw->header;
514 length = be32_to_cpu(hdr->length);
516 /* Verify the firmware. */
517 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
518 (hdr->magic[2] != 'F')) {
519 printf("Data at %p is not an Fman firmware\n", fmanfw);
523 if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
524 printf("Fman firmware at %p is too large (size=%u)\n",
529 length -= sizeof(u32); /* Subtract the size of the CRC */
530 crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length));
531 if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
532 printf("Fman firmware at %p has invalid CRC\n", fmanfw);
536 /* Increase the size of the fdt to make room for the node. */
537 rc = fdt_increase_size(blob, fmanfw->header.length);
539 printf("Unable to make room for Fman firmware: %s\n",
544 /* Create the firmware node. */
545 fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
548 fdt_get_path(blob, fmnode, s, sizeof(s));
549 printf("Could not add firmware node to %s: %s\n", s,
550 fdt_strerror(fwnode));
553 rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware");
556 fdt_get_path(blob, fwnode, s, sizeof(s));
557 printf("Could not add compatible property to node %s: %s\n", s,
561 phandle = fdt_create_phandle(blob, fwnode);
564 fdt_get_path(blob, fwnode, s, sizeof(s));
565 printf("Could not add phandle property to node %s: %s\n", s,
569 rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length);
572 fdt_get_path(blob, fwnode, s, sizeof(s));
573 printf("Could not add firmware property to node %s: %s\n", s,
578 /* Find all other Fman nodes and point them to the firmware node. */
579 while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) {
580 rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle);
583 fdt_get_path(blob, fmnode, s, sizeof(s));
584 printf("Could not add pointer property to node %s: %s\n",
585 s, fdt_strerror(rc));
591 #define fdt_fixup_fman_firmware(x)
594 #if defined(CONFIG_PPC_P4080)
595 static void fdt_fixup_usb(void *fdt)
597 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
598 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
601 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
602 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
603 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
604 fdt_status_disabled(fdt, off);
606 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
607 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
608 FSL_CORENET_RCWSR11_EC2_USB2)
609 fdt_status_disabled(fdt, off);
612 #define fdt_fixup_usb(x)
615 #if defined(CONFIG_PPC_T1040)
616 static void fdt_fixup_l2_switch(void *blob)
621 /* The l2switch node from device-tree has
622 * compatible string "vitesse-9953" */
623 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
624 if (node == -FDT_ERR_NOTFOUND)
625 /* no l2switch node has been found */
628 /* Get MAC address for the l2switch from "l2switchaddr"*/
629 if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) {
630 printf("Warning: MAC address for l2switch not found\n");
631 memset(l2swaddr, 0, sizeof(l2swaddr));
634 /* Add MAC address to l2switch node */
635 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
639 #define fdt_fixup_l2_switch(x)
642 void ft_cpu_setup(void *blob, bd_t *bd)
649 /* delete crypto node if not on an E-processor */
650 if (!IS_E_PROCESSOR(get_svr()))
651 fdt_fixup_crypto_node(blob, 0);
652 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
654 ccsr_sec_t __iomem *sec;
656 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
657 fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
661 fdt_fixup_ethernet(blob);
663 fdt_add_enet_stashing(blob);
665 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
666 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
668 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
669 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
671 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
672 "bus-frequency", bd->bi_busfreq, 1);
673 get_sys_info(&sysinfo);
674 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
675 while (off != -FDT_ERR_NOTFOUND) {
676 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
677 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
678 fdt_setprop(blob, off, "clock-frequency", &val, 4);
679 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
682 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
683 "bus-frequency", bd->bi_busfreq, 1);
685 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
686 "bus-frequency", gd->arch.lbc_clk, 1);
687 do_fixup_by_compat_u32(blob, "fsl,elbc",
688 "bus-frequency", gd->arch.lbc_clk, 1);
691 ft_fixup_qe_snum(blob);
694 fdt_fixup_fman_firmware(blob);
696 #ifdef CONFIG_SYS_NS16550
697 do_fixup_by_compat_u32(blob, "ns16550",
698 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
702 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
703 "current-speed", gd->baudrate, 1);
705 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
706 "clock-frequency", bd->bi_brgfreq, 1);
709 #ifdef CONFIG_FSL_CORENET
710 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
711 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
712 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
713 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
714 do_fixup_by_compat_u32(blob, "fsl,mpic",
715 "clock-frequency", get_bus_freq(0)/2, 1);
717 do_fixup_by_compat_u32(blob, "fsl,mpic",
718 "clock-frequency", get_bus_freq(0), 1);
721 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
724 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
725 ft_fixup_num_cores(blob);
728 ft_fixup_cache(blob);
730 #if defined(CONFIG_FSL_ESDHC)
731 fdt_fixup_esdhc(blob, bd);
734 ft_fixup_dpaa_clks(blob);
736 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
737 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
738 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
739 CONFIG_SYS_BMAN_MEM_SIZE);
740 fdt_fixup_bportals(blob);
743 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
744 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
745 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
746 CONFIG_SYS_QMAN_MEM_SIZE);
748 fdt_fixup_qportals(blob);
751 #ifdef CONFIG_SYS_SRIO
756 * system-clock = CCB clock/2
757 * Here gd->bus_clk = CCB clock
758 * We are using the system clock as 1588 Timer reference
759 * clock source select
761 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
762 "timer-frequency", gd->bus_clk/2, 1);
765 * clock-freq should change to clock-frequency and
766 * flexcan-v1.0 should change to p1010-flexcan respectively
769 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
770 "clock_freq", gd->bus_clk/2, 1);
772 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
773 "clock-frequency", gd->bus_clk/2, 1);
775 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
776 "clock-frequency", gd->bus_clk/2, 1);
780 fdt_fixup_l2_switch(blob);
784 * For some CCSR devices, we only have the virtual address, not the physical
785 * address. This is because we map CCSR as a whole, so we typically don't need
786 * a macro for the physical address of any device within CCSR. In this case,
787 * we calculate the physical address of that device using it's the difference
788 * between the virtual address of the device and the virtual address of the
791 #define CCSR_VIRT_TO_PHYS(x) \
792 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
794 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
796 printf("Warning: U-Boot configured %s at address %llx,\n"
797 "but the device tree has it at %llx\n", name, uaddr, daddr);
801 * Verify the device tree
803 * This function compares several CONFIG_xxx macros that contain physical
804 * addresses with the corresponding nodes in the device tree, to see if
805 * the physical addresses are all correct. For example, if
806 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
807 * of the first UART. We convert this to a physical address and compare
808 * that with the physical address of the first ns16550-compatible node
809 * in the device tree. If they don't match, then we display a warning.
811 * Returns 1 on success, 0 on failure
813 int ft_verify_fdt(void *fdt)
819 /* First check the CCSR base address */
820 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
822 addr = fdt_get_base_address(fdt, off);
825 printf("Warning: could not determine base CCSR address in "
827 /* No point in checking anything else */
831 if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
832 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
833 /* No point in checking anything else */
838 * Check some nodes via aliases. We assume that U-Boot and the device
839 * tree enumerate the devices equally. E.g. the first serial port in
840 * U-Boot is the same as "serial0" in the device tree.
842 aliases = fdt_path_offset(fdt, "/aliases");
844 #ifdef CONFIG_SYS_NS16550_COM1
845 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
846 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
850 #ifdef CONFIG_SYS_NS16550_COM2
851 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
852 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
858 * The localbus node is typically a root node, even though the lbc
859 * controller is part of CCSR. If we were to put the lbc node under
860 * the SOC node, then the 'ranges' property in the lbc node would
861 * translate through the 'ranges' property of the parent SOC node, and
862 * we don't want that. Since it's a separate node, it's possible for
863 * the 'reg' property to be wrong, so check it here. For now, we
864 * only check for "fsl,elbc" nodes.
866 #ifdef CONFIG_SYS_LBC_ADDR
867 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
869 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
871 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
873 addr = fdt_translate_address(fdt, off, reg);
875 msg("the localbus", uaddr, addr);