1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 #include <clock_legacy.h>
14 #include <asm/global_data.h>
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
17 #include <asm/processor.h>
18 #include <linux/ctype.h>
20 #include <asm/fsl_fdt.h>
21 #include <asm/fsl_portals.h>
22 #include <fsl_qbman.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
27 #ifdef CONFIG_SYS_DPAA_FMAN
31 DECLARE_GLOBAL_DATA_PTR;
33 extern void ft_qe_setup(void *blob);
34 extern void ft_fixup_num_cores(void *blob);
35 extern void ft_srio_setup(void *blob);
40 void ft_fixup_cpu(void *blob, u64 memory_limit)
43 phys_addr_t spin_tbl_addr = get_spin_phys_addr();
44 u32 bootpg = determine_mp_bootpg(NULL);
46 const char *enable_method;
47 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
49 int tdm_hwconfig_enabled = 0;
50 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
53 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
54 while (off != -FDT_ERR_NOTFOUND) {
55 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
58 u32 phys_cpu_id = thread_to_core(*reg);
59 u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
60 val = cpu_to_fdt64(val);
62 fdt_setprop_string(blob, off, "status",
65 fdt_setprop_string(blob, off, "status",
69 if (hold_cores_in_reset(0)) {
70 #ifdef CONFIG_FSL_CORENET
71 /* Cores held in reset, use BRR to release */
72 enable_method = "fsl,brr-holdoff";
74 /* Cores held in reset, use EEBPCR to release */
75 enable_method = "fsl,eebpcr-holdoff";
78 /* Cores out of reset and in a spin-loop */
79 enable_method = "spin-table";
81 fdt_setprop(blob, off, "cpu-release-addr",
85 fdt_setprop_string(blob, off, "enable-method",
88 printf ("cpu NULL\n");
90 off = fdt_node_offset_by_prop_value(blob, off,
91 "device_type", "cpu", 4);
94 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
95 #define CONFIG_MEM_HOLE_16M 0x1000000
97 * Extract hwconfig from environment.
98 * Search for tdm entry in hwconfig.
100 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
102 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
104 /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
105 if (tdm_hwconfig_enabled) {
106 off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
107 CONFIG_MEM_HOLE_16M);
109 printf("Failed to reserve memory for tdm: %s\n",
114 /* Reserve the boot page so OSes dont use it */
115 if ((u64)bootpg < memory_limit) {
116 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
118 printf("Failed to reserve memory for bootpg: %s\n",
122 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
124 * Reserve the default boot page so OSes dont use it.
125 * The default boot page is always mapped to bootpg above using
126 * boot page translation.
128 if (0xfffff000ull < memory_limit) {
129 off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
131 printf("Failed to reserve memory for 0xfffff000: %s\n",
137 /* Reserve spin table page */
138 if (spin_tbl_addr < memory_limit) {
139 off = fdt_add_mem_rsv(blob,
140 (spin_tbl_addr & ~0xffful), 4096);
142 printf("Failed to reserve memory for spin table: %s\n",
145 #ifdef CONFIG_DEEP_SLEEP
146 #ifdef CONFIG_SPL_MMC_BOOT
147 off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
148 CONFIG_SYS_MMC_U_BOOT_SIZE);
150 printf("Failed to reserve memory for SD deep sleep: %s\n",
152 #elif defined(CONFIG_SPL_SPI_BOOT)
153 off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
154 CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
156 printf("Failed to reserve memory for SPI deep sleep: %s\n",
163 #ifdef CONFIG_SYS_FSL_CPC
164 static inline void ft_fixup_l3cache(void *blob, int off)
166 u32 line_size, num_ways, size, num_sets;
167 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
168 u32 cfg0 = in_be32(&cpc->cpccfg0);
170 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
171 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
172 line_size = CPC_CFG0_LINE_SZ(cfg0);
173 num_sets = size / (line_size * num_ways);
175 fdt_setprop(blob, off, "cache-unified", NULL, 0);
176 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
177 fdt_setprop_cell(blob, off, "cache-size", size);
178 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
179 fdt_setprop_cell(blob, off, "cache-level", 3);
180 #ifdef CONFIG_SYS_CACHE_STASHING
181 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
185 #define ft_fixup_l3cache(x, y)
188 #if defined(CONFIG_L2_CACHE) || \
189 defined(CONFIG_BACKSIDE_L2_CACHE) || \
190 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
191 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
194 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
199 if (isdigit(cpu->name[0])) {
200 /* MPCxxxx, where xxxx == 4-digit number */
201 len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
204 /* Pxxxx or Txxxx, where xxxx == 4-digit number */
205 len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
206 tolower(cpu->name[0]), cpu->name + 1) + 1;
210 * append "cache" after the NULL character that the previous
211 * sprintf wrote. This is how a device tree stores multiple
212 * strings in a property.
214 len += sprintf(buf + len, "cache") + 1;
216 fdt_setprop(blob, off, "compatible", buf, len);
221 #if defined(CONFIG_L2_CACHE)
222 /* return size in kilobytes */
223 static inline u32 l2cache_size(void)
225 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
226 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
227 u32 ver = SVR_SOC_VER(get_svr());
229 switch (l2siz_field) {
233 if (ver == SVR_8540 || ver == SVR_8560 ||
234 ver == SVR_8541 || ver == SVR_8555)
240 if (ver == SVR_8540 || ver == SVR_8560 ||
241 ver == SVR_8541 || ver == SVR_8555)
254 static inline void ft_fixup_l2cache(void *blob)
259 const u32 line_size = 32;
260 const u32 num_ways = 8;
261 const u32 size = l2cache_size() * 1024;
262 const u32 num_sets = size / (line_size * num_ways);
264 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
266 debug("no cpu node fount\n");
270 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
273 debug("no next-level-cache property\n");
277 off = fdt_node_offset_by_phandle(blob, *ph);
279 printf("%s: %s\n", __func__, fdt_strerror(off));
283 ft_fixup_l2cache_compatible(blob, off);
284 fdt_setprop(blob, off, "cache-unified", NULL, 0);
285 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
286 fdt_setprop_cell(blob, off, "cache-size", size);
287 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
288 fdt_setprop_cell(blob, off, "cache-level", 2);
290 /* we dont bother w/L3 since no platform of this type has one */
292 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
293 defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
294 static inline void ft_fixup_l2cache(void *blob)
296 int off, l2_off, l3_off = -1;
298 #ifdef CONFIG_BACKSIDE_L2_CACHE
299 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
301 struct ccsr_cluster_l2 *l2cache =
302 (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
303 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
305 u32 size, line_size, num_ways, num_sets;
308 /* P2040/P2040E has no L2, so dont set any L2 props */
309 if (SVR_SOC_VER(get_svr()) == SVR_P2040)
312 size = (l2cfg0 & 0x3fff) * 64 * 1024;
313 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
314 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
315 num_sets = size / (line_size * num_ways);
317 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
319 while (off != -FDT_ERR_NOTFOUND) {
320 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
323 debug("no next-level-cache property\n");
327 l2_off = fdt_node_offset_by_phandle(blob, *ph);
329 printf("%s: %s\n", __func__, fdt_strerror(off));
334 #ifdef CONFIG_SYS_CACHE_STASHING
335 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
336 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
337 /* Only initialize every eighth thread */
338 if (reg && !((*reg) % 8)) {
339 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
340 (*reg / 4) + 32 + 1);
344 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
345 (*reg * 2) + 32 + 1);
350 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
351 fdt_setprop_cell(blob, l2_off, "cache-block-size",
353 fdt_setprop_cell(blob, l2_off, "cache-size", size);
354 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
355 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
356 ft_fixup_l2cache_compatible(blob, l2_off);
360 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
363 debug("no next-level-cache property\n");
369 off = fdt_node_offset_by_prop_value(blob, off,
370 "device_type", "cpu", 4);
373 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
375 printf("%s: %s\n", __func__, fdt_strerror(off));
378 ft_fixup_l3cache(blob, l3_off);
382 #define ft_fixup_l2cache(x)
385 static inline void ft_fixup_cache(void *blob)
389 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
391 while (off != -FDT_ERR_NOTFOUND) {
392 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
393 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
394 u32 isize, iline_size, inum_sets, inum_ways;
395 u32 dsize, dline_size, dnum_sets, dnum_ways;
398 dsize = (l1cfg0 & 0x7ff) * 1024;
399 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
400 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
401 dnum_sets = dsize / (dline_size * dnum_ways);
403 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
404 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
405 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
407 #ifdef CONFIG_SYS_CACHE_STASHING
409 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
411 fdt_setprop_cell(blob, off, "cache-stash-id",
412 (*reg * 2) + 32 + 0);
417 isize = (l1cfg1 & 0x7ff) * 1024;
418 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
419 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
420 inum_sets = isize / (iline_size * inum_ways);
422 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
423 fdt_setprop_cell(blob, off, "i-cache-size", isize);
424 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
426 off = fdt_node_offset_by_prop_value(blob, off,
427 "device_type", "cpu", 4);
430 ft_fixup_l2cache(blob);
434 void fdt_add_enet_stashing(void *fdt)
436 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
438 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
440 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
441 do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
442 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
443 do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
446 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
447 #ifdef CONFIG_SYS_DPAA_FMAN
448 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
451 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
452 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
455 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
457 printf("WARNING enable to set clock-frequency "
458 "for %s: %s\n", compat, fdt_strerror(off));
463 static void ft_fixup_dpaa_clks(void *blob)
467 get_sys_info(&sysinfo);
468 #ifdef CONFIG_SYS_DPAA_FMAN
469 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
470 sysinfo.freq_fman[0]);
472 #if (CONFIG_SYS_NUM_FMAN == 2)
473 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
474 sysinfo.freq_fman[1]);
478 #ifdef CONFIG_SYS_DPAA_QBMAN
479 do_fixup_by_compat_u32(blob, "fsl,qman",
480 "clock-frequency", sysinfo.freq_qman, 1);
483 #ifdef CONFIG_SYS_DPAA_PME
484 do_fixup_by_compat_u32(blob, "fsl,pme",
485 "clock-frequency", sysinfo.freq_pme, 1);
489 #define ft_fixup_dpaa_clks(x)
493 static void ft_fixup_qe_snum(void *blob)
497 svr = mfspr(SPRN_SVR);
498 if (SVR_SOC_VER(svr) == SVR_8569) {
499 if(IS_SVR_REV(svr, 1, 0))
500 do_fixup_by_compat_u32(blob, "fsl,qe",
501 "fsl,qe-num-snums", 46, 1);
503 do_fixup_by_compat_u32(blob, "fsl,qe",
504 "fsl,qe-num-snums", 76, 1);
509 #if defined(CONFIG_ARCH_P4080)
510 static void fdt_fixup_usb(void *fdt)
512 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
513 u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
516 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
517 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
518 FSL_CORENET_RCWSR11_EC1_FM1_USB1)
519 fdt_status_disabled(fdt, off);
521 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
522 if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
523 FSL_CORENET_RCWSR11_EC2_USB2)
524 fdt_status_disabled(fdt, off);
527 #define fdt_fixup_usb(x)
530 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240)
531 void fdt_fixup_dma3(void *blob)
533 /* the 3rd DMA is not functional if SRIO2 is chosen */
535 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
537 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
538 #if defined(CONFIG_ARCH_T2080)
539 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
540 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
541 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
543 switch (srds_prtcl_s2) {
547 #elif defined(CONFIG_ARCH_T4240)
548 u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
549 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
550 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
552 switch (srds_prtcl_s4) {
558 nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
559 CONFIG_SYS_ELO3_DMA3);
561 fdt_status_disabled(blob, nodeoff);
563 printf("WARNING: unable to disable dma3\n");
570 #define fdt_fixup_dma3(x)
573 #if defined(CONFIG_ARCH_T1040)
574 static void fdt_fixup_l2_switch(void *blob)
579 /* The l2switch node from device-tree has
580 * compatible string "vitesse-9953" */
581 node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
582 if (node == -FDT_ERR_NOTFOUND)
583 /* no l2switch node has been found */
586 /* Get MAC address for the l2switch from "l2switchaddr"*/
587 if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
588 printf("Warning: MAC address for l2switch not found\n");
589 memset(l2swaddr, 0, sizeof(l2swaddr));
592 /* Add MAC address to l2switch node */
593 fdt_setprop(blob, node, "local-mac-address", l2swaddr,
597 #define fdt_fixup_l2_switch(x)
600 void ft_cpu_setup(void *blob, struct bd_info *bd)
607 /* delete crypto node if not on an E-processor */
608 if (!IS_E_PROCESSOR(get_svr()))
609 fdt_fixup_crypto_node(blob, 0);
610 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
612 ccsr_sec_t __iomem *sec;
614 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
615 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
619 fdt_add_enet_stashing(blob);
621 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
622 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
624 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
625 "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
627 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
628 "bus-frequency", bd->bi_busfreq, 1);
629 get_sys_info(&sysinfo);
630 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
631 while (off != -FDT_ERR_NOTFOUND) {
632 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
633 val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
634 fdt_setprop(blob, off, "clock-frequency", &val, 4);
635 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
638 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
639 "bus-frequency", bd->bi_busfreq, 1);
643 ft_fixup_qe_snum(blob);
646 #ifdef CONFIG_SYS_DPAA_FMAN
647 fdt_fixup_fman_firmware(blob);
650 #ifdef CONFIG_SYS_NS16550
651 do_fixup_by_compat_u32(blob, "ns16550",
652 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
655 #ifdef CONFIG_FSL_CORENET
656 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
657 "clock-frequency", get_board_sys_clk(), 1);
658 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
659 "clock-frequency", get_board_sys_clk(), 1);
660 do_fixup_by_compat_u32(blob, "fsl,mpic",
661 "clock-frequency", get_bus_freq(0)/2, 1);
663 do_fixup_by_compat_u32(blob, "fsl,mpic",
664 "clock-frequency", get_bus_freq(0), 1);
667 fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
670 ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size);
671 ft_fixup_num_cores(blob);
674 ft_fixup_cache(blob);
676 #if defined(CONFIG_FSL_ESDHC)
677 fdt_fixup_esdhc(blob, bd);
680 ft_fixup_dpaa_clks(blob);
682 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
683 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
684 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
685 CONFIG_SYS_BMAN_MEM_SIZE);
686 fdt_fixup_bportals(blob);
689 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
690 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
691 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
692 CONFIG_SYS_QMAN_MEM_SIZE);
694 fdt_fixup_qportals(blob);
697 #ifdef CONFIG_SYS_SRIO
702 * system-clock = CCB clock/2
703 * Here gd->bus_clk = CCB clock
704 * We are using the system clock as 1588 Timer reference
705 * clock source select
707 do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
708 "timer-frequency", gd->bus_clk/2, 1);
711 * clock-freq should change to clock-frequency and
712 * flexcan-v1.0 should change to p1010-flexcan respectively
715 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
716 "clock_freq", gd->bus_clk/2, 1);
718 do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
719 "clock-frequency", gd->bus_clk/2, 1);
721 do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
722 "clock-frequency", gd->bus_clk/2, 1);
726 fdt_fixup_l2_switch(blob);
728 fdt_fixup_dma3(blob);
732 * For some CCSR devices, we only have the virtual address, not the physical
733 * address. This is because we map CCSR as a whole, so we typically don't need
734 * a macro for the physical address of any device within CCSR. In this case,
735 * we calculate the physical address of that device using it's the difference
736 * between the virtual address of the device and the virtual address of the
739 #define CCSR_VIRT_TO_PHYS(x) \
740 (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
742 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
744 printf("Warning: U-Boot configured %s at address %llx,\n"
745 "but the device tree has it at %llx\n", name, uaddr, daddr);
749 * Verify the device tree
751 * This function compares several CONFIG_xxx macros that contain physical
752 * addresses with the corresponding nodes in the device tree, to see if
753 * the physical addresses are all correct. For example, if
754 * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
755 * of the first UART. We convert this to a physical address and compare
756 * that with the physical address of the first ns16550-compatible node
757 * in the device tree. If they don't match, then we display a warning.
759 * Returns 1 on success, 0 on failure
761 int ft_verify_fdt(void *fdt)
767 /* First check the CCSR base address */
768 off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
774 naddr = fdt_address_cells(fdt, off);
775 prop = fdt_getprop(fdt, off, "ranges", &size);
776 addr = fdt_translate_address(fdt, off, prop + naddr);
780 printf("Warning: could not determine base CCSR address in "
782 /* No point in checking anything else */
786 if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
787 msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
788 /* No point in checking anything else */
793 * Check some nodes via aliases. We assume that U-Boot and the device
794 * tree enumerate the devices equally. E.g. the first serial port in
795 * U-Boot is the same as "serial0" in the device tree.
797 aliases = fdt_path_offset(fdt, "/aliases");
799 #ifdef CONFIG_SYS_NS16550_COM1
800 if (!fdt_verify_alias_address(fdt, aliases, "serial0",
801 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
805 #ifdef CONFIG_SYS_NS16550_COM2
806 if (!fdt_verify_alias_address(fdt, aliases, "serial1",
807 CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
813 * The localbus node is typically a root node, even though the lbc
814 * controller is part of CCSR. If we were to put the lbc node under
815 * the SOC node, then the 'ranges' property in the lbc node would
816 * translate through the 'ranges' property of the parent SOC node, and
817 * we don't want that. Since it's a separate node, it's possible for
818 * the 'reg' property to be wrong, so check it here. For now, we
819 * only check for "fsl,elbc" nodes.
821 #ifdef CONFIG_SYS_LBC_ADDR
822 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
824 const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
826 uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
828 addr = fdt_translate_address(fdt, off, reg);
830 msg("the localbus", uaddr, addr);
840 void fdt_del_diu(void *blob)
844 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
846 fdt_del_node(blob, nodeoff);