arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12
  13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  15 #endif
  16
  17 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  18                              unsigned int ctrl_num)
  19 {
  20         unsigned int i;
  21         volatile ccsr_ddr_t *ddr;
  22         u32 temp_sdram_cfg;
  23
  24         switch (ctrl_num) {
  25         case 0:
  26                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  27                 break;
  28         case 1:
  29                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  30                 break;
  31         default:
  32                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  33                 return;
  34         }
  35
  36         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  37                 if (i == 0) {
  38                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  39                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  40                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  41
  42                 } else if (i == 1) {
  43                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  44                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  45                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  46
  47                 } else if (i == 2) {
  48                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  49                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  50                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  51
  52                 } else if (i == 3) {
  53                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  54                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  55                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  56                 }
  57         }
  58
  59         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  60         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  61         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  62         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  63         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  64         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  65         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  66         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  67         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  68         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  69         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  70         out_be32(&ddr->init_addr, regs->ddr_init_addr);
  71         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  72
  73         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  74         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  75         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  76         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  77         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  78         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  79         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  80
  81         /* Set, but do not enable the memory */
  82         temp_sdram_cfg = regs->ddr_sdram_cfg;
  83         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
  84         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
  85         /*
  86          * For 8572 DDR1 erratum - DDR controller may enter illegal state
  87          * when operatiing in 32-bit bus mode with 4-beat bursts,
  88          * This erratum does not affect DDR3 mode, only for DDR2 mode.
  89          */
  90 #ifdef CONFIG_MPC8572
  91         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
  92             && in_be32(&ddr->sdram_cfg) & 0x80000) {
  93                 /* set DEBUG_1[31] */
  94                 u32 temp = in_be32(&ddr->debug_1);
  95                 out_be32(&ddr->debug_1, temp | 1);
  96         }
  97 #endif
  98
  99         /*
 100          * 500 painful micro-seconds must elapse between
 101          * the DDR clock setup and the DDR config enable.
 102          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 103          * we choose the max, that is 500 us for all of case.
 104          */
 105         udelay(500);
 106         asm volatile("sync;isync");
 107
 108         /* Let the controller go */
 109         temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
 110         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 111
 112         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 113         while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
 114                 udelay(10000);          /* throttle polling rate */
 115         }
 116 }