arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  25         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  26         u32 total_gb_size_per_controller;
  27         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  28         int csn = -1;
  29 #endif
  30
  31         switch (ctrl_num) {
  32         case 0:
  33                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  34                 break;
  35         case 1:
  36                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  37                 break;
  38         default:
  39                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  40                 return;
  41         }
  42
  43         out_be32(&ddr->eor, regs->ddr_eor);
  44
  45 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  46         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  47         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  48                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  49                 cs_ea = regs->cs[i].bnds & 0xfff;
  50                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  51                         csn = i;
  52                         csn_bnds_backup = regs->cs[i].bnds;
  53                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  54                         if (cs_ea > 0xeff)
  55                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  56                         else
  57                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  58                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  59                                 "change it to 0x%x\n",
  60                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  61                         break;
  62                 }
  63         }
  64 #endif
  65         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  66                 if (i == 0) {
  67                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  68                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  69                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  70
  71                 } else if (i == 1) {
  72                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  73                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  74                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  75
  76                 } else if (i == 2) {
  77                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  78                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  79                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  80
  81                 } else if (i == 3) {
  82                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  83                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  84                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  85                 }
  86         }
  87
  88         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  89         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  90         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  91         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  92         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  93         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  94         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  95         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  96         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  97         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  98         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  99         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 100         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 101         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 102         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 103         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 104         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 105         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 106         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 107
 108         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 109         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 110         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 111         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 112         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 113         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 114         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 115         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 116         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 117         out_be32(&ddr->err_disable, regs->err_disable);
 118         out_be32(&ddr->err_int_en, regs->err_int_en);
 119         for (i = 0; i < 32; i++) {
 120                 if (regs->debug[i]) {
 121                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 122                         out_be32(&ddr->debug[i], regs->debug[i]);
 123                 }
 124         }
 125
 126 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 127         out_be32(&ddr->debug[12], 0x00000015);
 128         out_be32(&ddr->debug[21], 0x24000000);
 129 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 130
 131         /* Set, but do not enable the memory */
 132         temp_sdram_cfg = regs->ddr_sdram_cfg;
 133         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 134         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 135 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 136         debug("Workaround for ERRATUM_DDR_A003\n");
 137         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 138                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 139                 out_be32(&ddr->debug[2], 0x00000400);
 140                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 141                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 142                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 143                 out_be32(&ddr->mtcr, 0);
 144                 out_be32(&ddr->debug[12], 0x00000015);
 145                 out_be32(&ddr->debug[21], 0x24000000);
 146                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 147                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 148
 149                 asm volatile("sync;isync");
 150                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 151                         ;
 152
 153                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 154                 case 0x00000000:
 155                         out_be32(&ddr->sdram_md_cntl,
 156                                 MD_CNTL_MD_EN           |
 157                                 MD_CNTL_CS_SEL_CS0_CS1  |
 158                                 0x04000000              |
 159                                 MD_CNTL_WRCW            |
 160                                 MD_CNTL_MD_VALUE(0x02));
 161                         break;
 162                 case 0x00100000:
 163                         out_be32(&ddr->sdram_md_cntl,
 164                                 MD_CNTL_MD_EN           |
 165                                 MD_CNTL_CS_SEL_CS0_CS1  |
 166                                 0x04000000              |
 167                                 MD_CNTL_WRCW            |
 168                                 MD_CNTL_MD_VALUE(0x0a));
 169                         break;
 170                 case 0x00200000:
 171                         out_be32(&ddr->sdram_md_cntl,
 172                                 MD_CNTL_MD_EN           |
 173                                 MD_CNTL_CS_SEL_CS0_CS1  |
 174                                 0x04000000              |
 175                                 MD_CNTL_WRCW            |
 176                                 MD_CNTL_MD_VALUE(0x12));
 177                         break;
 178                 case 0x00300000:
 179                         out_be32(&ddr->sdram_md_cntl,
 180                                 MD_CNTL_MD_EN           |
 181                                 MD_CNTL_CS_SEL_CS0_CS1  |
 182                                 0x04000000              |
 183                                 MD_CNTL_WRCW            |
 184                                 MD_CNTL_MD_VALUE(0x1a));
 185                         break;
 186                 default:
 187                         out_be32(&ddr->sdram_md_cntl,
 188                                 MD_CNTL_MD_EN           |
 189                                 MD_CNTL_CS_SEL_CS0_CS1  |
 190                                 0x04000000              |
 191                                 MD_CNTL_WRCW            |
 192                                 MD_CNTL_MD_VALUE(0x02));
 193                         printf("Unsupported RC10\n");
 194                         break;
 195                 }
 196
 197                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 198                         ;
 199                 udelay(6);
 200                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 201                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 202                 out_be32(&ddr->debug[2], 0x0);
 203                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 204                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 205                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 206                 out_be32(&ddr->debug[12], 0x0);
 207                 out_be32(&ddr->debug[21], 0x0);
 208                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 209
 210         }
 211 #endif
 212         /*
 213          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 214          * when operatiing in 32-bit bus mode with 4-beat bursts,
 215          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 216          */
 217 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 218         debug("Workaround for ERRATUM_DDR_115\n");
 219         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 220             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 221                 /* set DEBUG_1[31] */
 222                 setbits_be32(&ddr->debug[0], 1);
 223         }
 224 #endif
 225 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 226         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 227         /*
 228          * This is the combined workaround for DDR111 and DDR134
 229          * following the published errata for MPC8572
 230          */
 231
 232         /* 1. Set EEBACR[3] */
 233         setbits_be32(&ecm->eebacr, 0x10000000);
 234         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 235
 236         /* 2. Set DINIT in SDRAM_CFG_2*/
 237         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 238         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 239                 in_be32(&ddr->sdram_cfg_2));
 240
 241         /* 3. Set DEBUG_3[21] */
 242         setbits_be32(&ddr->debug[2], 0x400);
 243         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 244
 245 #endif  /* part 1 of the workaound */
 246
 247         /*
 248          * 500 painful micro-seconds must elapse between
 249          * the DDR clock setup and the DDR config enable.
 250          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 251          * we choose the max, that is 500 us for all of case.
 252          */
 253         udelay(500);
 254         asm volatile("sync;isync");
 255
 256         /* Let the controller go */
 257         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 258         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 259         asm volatile("sync;isync");
 260
 261         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 262         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 263                 udelay(10000);          /* throttle polling rate */
 264
 265 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 266         /* continue this workaround */
 267
 268         /* 4. Clear DEBUG3[21] */
 269         clrbits_be32(&ddr->debug[2], 0x400);
 270         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 271
 272         /* DDR134 workaround starts */
 273         /* A: Clear sdram_cfg_2[odt_cfg] */
 274         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 275         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 276                 in_be32(&ddr->sdram_cfg_2));
 277
 278         /* B: Set DEBUG1[15] */
 279         setbits_be32(&ddr->debug[0], 0x10000);
 280         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 281
 282         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 283         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 284         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 285                 in_be32(&ddr->timing_cfg_2));
 286
 287         /* D: Set D6 to 0x9f9f9f9f */
 288         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 289         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 290
 291         /* E: Set D7 to 0x9f9f9f9f */
 292         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 293         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 294
 295         /* F: Set D2[20] */
 296         setbits_be32(&ddr->debug[1], 0x800);
 297         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 298
 299         /* G: Poll on D2[20] until cleared */
 300         while (in_be32(&ddr->debug[1]) & 0x800)
 301                 udelay(10000);          /* throttle polling rate */
 302
 303         /* H: Clear D1[15] */
 304         clrbits_be32(&ddr->debug[0], 0x10000);
 305         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 306
 307         /* I: Set sdram_cfg_2[odt_cfg] */
 308         setbits_be32(&ddr->sdram_cfg_2,
 309                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 310         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 311
 312         /* Continuing with the DDR111 workaround */
 313         /* 5. Set D2[21] */
 314         setbits_be32(&ddr->debug[1], 0x400);
 315         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 316
 317         /* 6. Poll D2[21] until its cleared */
 318         while (in_be32(&ddr->debug[1]) & 0x400)
 319                 udelay(10000);          /* throttle polling rate */
 320
 321         /* 7. Wait for 400ms/GB */
 322         total_gb_size_per_controller = 0;
 323         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 324                 if (i == csn) {
 325                         total_gb_size_per_controller +=
 326                                 ((csn_bnds_backup & 0xFFFF) >> 6)
 327                                 - (csn_bnds_backup >> 22) + 1;
 328                 } else {
 329                         total_gb_size_per_controller +=
 330                                 ((regs->cs[i].bnds & 0xFFFF) >> 6)
 331                                 - (regs->cs[i].bnds >> 22) + 1;
 332                 }
 333         }
 334         if (in_be32(&ddr->sdram_cfg) & 0x80000)
 335                 total_gb_size_per_controller <<= 1;
 336         debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
 337         udelay(total_gb_size_per_controller * 400000);
 338
 339         /* 8. Set sdram_cfg_2[dinit] if options requires */
 340         setbits_be32(&ddr->sdram_cfg_2,
 341                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 342         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 343
 344         /* 9. Poll until dinit is cleared */
 345         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 346                 udelay(10000);
 347
 348         /* 10. Clear EEBACR[3] */
 349         clrbits_be32(&ecm->eebacr, 10000000);
 350         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 351
 352         if (csn != -1) {
 353                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 354                 *csn_bnds_t = csn_bnds_backup;
 355                 debug("Change cs%d_bnds back to 0x%08x\n",
 356                         csn, regs->cs[csn].bnds);
 357                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 358                 switch (csn) {
 359                 case 0:
 360                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 361                         break;
 362                 case 1:
 363                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 364                         break;
 365                 case 2:
 366                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 367                         break;
 368                 case 3:
 369                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 370                         break;
 371                 }
 372                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 373         }
 374 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 375 }