arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  25         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  26         u32 total_gb_size_per_controller;
  27         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  28         int csn = -1;
  29 #endif
  30
  31         switch (ctrl_num) {
  32         case 0:
  33                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  34                 break;
  35         case 1:
  36                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  37                 break;
  38         default:
  39                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  40                 return;
  41         }
  42
  43         out_be32(&ddr->eor, regs->ddr_eor);
  44
  45 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  46         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  47                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  48                 cs_ea = regs->cs[i].bnds & 0xfff;
  49                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  50                         csn = i;
  51                         csn_bnds_backup = regs->cs[i].bnds;
  52                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  53                         if (cs_ea > 0xeff)
  54                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  55                         else
  56                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  57                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  58                                 "change it to 0x%x\n",
  59                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  60                         break;
  61                 }
  62         }
  63 #endif
  64         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  65                 if (i == 0) {
  66                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  67                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  68                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  69
  70                 } else if (i == 1) {
  71                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  72                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  73                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  74
  75                 } else if (i == 2) {
  76                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  77                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  78                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  79
  80                 } else if (i == 3) {
  81                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  82                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  83                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  84                 }
  85         }
  86
  87         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  88         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  89         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  90         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  91         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  92         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  93         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  94         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  95         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  96         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  97         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  98         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  99         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 100         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 101         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 102         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 103         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 104         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 105         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 106
 107         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 108         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 109         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 110         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 111         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 112         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 113         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 114         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 115         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 116         out_be32(&ddr->err_disable, regs->err_disable);
 117         out_be32(&ddr->err_int_en, regs->err_int_en);
 118         for (i = 0; i < 32; i++)
 119                 out_be32(&ddr->debug[i], regs->debug[i]);
 120
 121 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 122         out_be32(&ddr->debug[12], 0x00000015);
 123         out_be32(&ddr->debug[21], 0x24000000);
 124 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 125
 126         /* Set, but do not enable the memory */
 127         temp_sdram_cfg = regs->ddr_sdram_cfg;
 128         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 129         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 130 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 131         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 132                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 133                 out_be32(&ddr->debug[2], 0x00000400);
 134                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 135                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 136                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 137                 out_be32(&ddr->mtcr, 0);
 138                 out_be32(&ddr->debug[12], 0x00000015);
 139                 out_be32(&ddr->debug[21], 0x24000000);
 140                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 141                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 142
 143                 asm volatile("sync;isync");
 144                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 145                         ;
 146
 147                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 148                 case 0x00000000:
 149                         out_be32(&ddr->sdram_md_cntl,
 150                                 MD_CNTL_MD_EN           |
 151                                 MD_CNTL_CS_SEL_CS0_CS1  |
 152                                 0x04000000              |
 153                                 MD_CNTL_WRCW            |
 154                                 MD_CNTL_MD_VALUE(0x02));
 155                         break;
 156                 case 0x00100000:
 157                         out_be32(&ddr->sdram_md_cntl,
 158                                 MD_CNTL_MD_EN           |
 159                                 MD_CNTL_CS_SEL_CS0_CS1  |
 160                                 0x04000000              |
 161                                 MD_CNTL_WRCW            |
 162                                 MD_CNTL_MD_VALUE(0x0a));
 163                         break;
 164                 case 0x00200000:
 165                         out_be32(&ddr->sdram_md_cntl,
 166                                 MD_CNTL_MD_EN           |
 167                                 MD_CNTL_CS_SEL_CS0_CS1  |
 168                                 0x04000000              |
 169                                 MD_CNTL_WRCW            |
 170                                 MD_CNTL_MD_VALUE(0x12));
 171                         break;
 172                 case 0x00300000:
 173                         out_be32(&ddr->sdram_md_cntl,
 174                                 MD_CNTL_MD_EN           |
 175                                 MD_CNTL_CS_SEL_CS0_CS1  |
 176                                 0x04000000              |
 177                                 MD_CNTL_WRCW            |
 178                                 MD_CNTL_MD_VALUE(0x1a));
 179                         break;
 180                 default:
 181                         out_be32(&ddr->sdram_md_cntl,
 182                                 MD_CNTL_MD_EN           |
 183                                 MD_CNTL_CS_SEL_CS0_CS1  |
 184                                 0x04000000              |
 185                                 MD_CNTL_WRCW            |
 186                                 MD_CNTL_MD_VALUE(0x02));
 187                         printf("Unsupported RC10\n");
 188                         break;
 189                 }
 190
 191                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 192                         ;
 193                 udelay(6);
 194                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 195                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 196                 out_be32(&ddr->debug[2], 0x0);
 197                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 198                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 199                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 200                 out_be32(&ddr->debug[12], 0x0);
 201                 out_be32(&ddr->debug[21], 0x0);
 202                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 203
 204         }
 205 #endif
 206         /*
 207          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 208          * when operatiing in 32-bit bus mode with 4-beat bursts,
 209          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 210          */
 211 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 212         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 213             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 214                 /* set DEBUG_1[31] */
 215                 setbits_be32(&ddr->debug[0], 1);
 216         }
 217 #endif
 218 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 219         /*
 220          * This is the combined workaround for DDR111 and DDR134
 221          * following the published errata for MPC8572
 222          */
 223
 224         /* 1. Set EEBACR[3] */
 225         setbits_be32(&ecm->eebacr, 0x10000000);
 226         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 227
 228         /* 2. Set DINIT in SDRAM_CFG_2*/
 229         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 230         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 231                 in_be32(&ddr->sdram_cfg_2));
 232
 233         /* 3. Set DEBUG_3[21] */
 234         setbits_be32(&ddr->debug[2], 0x400);
 235         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 236
 237 #endif  /* part 1 of the workaound */
 238
 239         /*
 240          * 500 painful micro-seconds must elapse between
 241          * the DDR clock setup and the DDR config enable.
 242          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 243          * we choose the max, that is 500 us for all of case.
 244          */
 245         udelay(500);
 246         asm volatile("sync;isync");
 247
 248         /* Let the controller go */
 249         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 250         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 251         asm volatile("sync;isync");
 252
 253         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 254         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 255                 udelay(10000);          /* throttle polling rate */
 256
 257 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 258         /* continue this workaround */
 259
 260         /* 4. Clear DEBUG3[21] */
 261         clrbits_be32(&ddr->debug[2], 0x400);
 262         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 263
 264         /* DDR134 workaround starts */
 265         /* A: Clear sdram_cfg_2[odt_cfg] */
 266         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 267         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 268                 in_be32(&ddr->sdram_cfg_2));
 269
 270         /* B: Set DEBUG1[15] */
 271         setbits_be32(&ddr->debug[0], 0x10000);
 272         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 273
 274         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 275         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 276         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 277                 in_be32(&ddr->timing_cfg_2));
 278
 279         /* D: Set D6 to 0x9f9f9f9f */
 280         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 281         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 282
 283         /* E: Set D7 to 0x9f9f9f9f */
 284         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 285         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 286
 287         /* F: Set D2[20] */
 288         setbits_be32(&ddr->debug[1], 0x800);
 289         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 290
 291         /* G: Poll on D2[20] until cleared */
 292         while (in_be32(&ddr->debug[1]) & 0x800)
 293                 udelay(10000);          /* throttle polling rate */
 294
 295         /* H: Clear D1[15] */
 296         clrbits_be32(&ddr->debug[0], 0x10000);
 297         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 298
 299         /* I: Set sdram_cfg_2[odt_cfg] */
 300         setbits_be32(&ddr->sdram_cfg_2,
 301                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 302         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 303
 304         /* Continuing with the DDR111 workaround */
 305         /* 5. Set D2[21] */
 306         setbits_be32(&ddr->debug[1], 0x400);
 307         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 308
 309         /* 6. Poll D2[21] until its cleared */
 310         while (in_be32(&ddr->debug[1]) & 0x400)
 311                 udelay(10000);          /* throttle polling rate */
 312
 313         /* 7. Wait for 400ms/GB */
 314         total_gb_size_per_controller = 0;
 315         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 316                 if (i == csn) {
 317                         total_gb_size_per_controller +=
 318                                 ((csn_bnds_backup & 0xFFFF) >> 6)
 319                                 - (csn_bnds_backup >> 22) + 1;
 320                 } else {
 321                         total_gb_size_per_controller +=
 322                                 ((regs->cs[i].bnds & 0xFFFF) >> 6)
 323                                 - (regs->cs[i].bnds >> 22) + 1;
 324                 }
 325         }
 326         if (in_be32(&ddr->sdram_cfg) & 0x80000)
 327                 total_gb_size_per_controller <<= 1;
 328         debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
 329         udelay(total_gb_size_per_controller * 400000);
 330
 331         /* 8. Set sdram_cfg_2[dinit] if options requires */
 332         setbits_be32(&ddr->sdram_cfg_2,
 333                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 334         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 335
 336         /* 9. Poll until dinit is cleared */
 337         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 338                 udelay(10000);
 339
 340         /* 10. Clear EEBACR[3] */
 341         clrbits_be32(&ecm->eebacr, 10000000);
 342         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 343
 344         if (csn != -1) {
 345                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 346                 *csn_bnds_t = csn_bnds_backup;
 347                 debug("Change cs%d_bnds back to 0x%08x\n",
 348                         csn, regs->cs[csn].bnds);
 349                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 350                 switch (csn) {
 351                 case 0:
 352                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 353                         break;
 354                 case 1:
 355                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 356                         break;
 357                 case 2:
 358                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 359                         break;
 360                 case 3:
 361                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 362                         break;
 363                 }
 364                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 365         }
 366 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 367 }