arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  25         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  26         u32 total_gb_size_per_controller;
  27         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  28         int csn = -1;
  29 #endif
  30
  31         switch (ctrl_num) {
  32         case 0:
  33                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  34                 break;
  35 #if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  36         case 1:
  37                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  38                 break;
  39 #endif
  40 #if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  41         case 2:
  42                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
  43                 break;
  44 #endif
  45 #if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  46         case 3:
  47                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
  48                 break;
  49 #endif
  50         default:
  51                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  52                 return;
  53         }
  54
  55         out_be32(&ddr->eor, regs->ddr_eor);
  56
  57 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  58         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  59         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  60                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  61                 cs_ea = regs->cs[i].bnds & 0xfff;
  62                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  63                         csn = i;
  64                         csn_bnds_backup = regs->cs[i].bnds;
  65                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  66                         if (cs_ea > 0xeff)
  67                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  68                         else
  69                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  70                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  71                                 "change it to 0x%x\n",
  72                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  73                         break;
  74                 }
  75         }
  76 #endif
  77         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  78                 if (i == 0) {
  79                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  80                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  81                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  82
  83                 } else if (i == 1) {
  84                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  85                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  86                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  87
  88                 } else if (i == 2) {
  89                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  90                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  91                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  92
  93                 } else if (i == 3) {
  94                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  95                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  96                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  97                 }
  98         }
  99
 100         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 101         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 102         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 103         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 104         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 105         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 106         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 107         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 108         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 109         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 110         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 111         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 112         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 113         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 114         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 115         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 116         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 117         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 118         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 119
 120         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 121         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 122         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 123         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 124         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 125         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 126         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 127         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 128         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 129         out_be32(&ddr->err_disable, regs->err_disable);
 130         out_be32(&ddr->err_int_en, regs->err_int_en);
 131         for (i = 0; i < 32; i++) {
 132                 if (regs->debug[i]) {
 133                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 134                         out_be32(&ddr->debug[i], regs->debug[i]);
 135                 }
 136         }
 137
 138 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 139         out_be32(&ddr->debug[12], 0x00000015);
 140         out_be32(&ddr->debug[21], 0x24000000);
 141 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 142
 143         /* Set, but do not enable the memory */
 144         temp_sdram_cfg = regs->ddr_sdram_cfg;
 145         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 146         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 147 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 148         debug("Workaround for ERRATUM_DDR_A003\n");
 149         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 150                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 151                 out_be32(&ddr->debug[2], 0x00000400);
 152                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 153                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 154                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 155                 out_be32(&ddr->mtcr, 0);
 156                 out_be32(&ddr->debug[12], 0x00000015);
 157                 out_be32(&ddr->debug[21], 0x24000000);
 158                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 159                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 160
 161                 asm volatile("sync;isync");
 162                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 163                         ;
 164
 165                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 166                 case 0x00000000:
 167                         out_be32(&ddr->sdram_md_cntl,
 168                                 MD_CNTL_MD_EN           |
 169                                 MD_CNTL_CS_SEL_CS0_CS1  |
 170                                 0x04000000              |
 171                                 MD_CNTL_WRCW            |
 172                                 MD_CNTL_MD_VALUE(0x02));
 173                         break;
 174                 case 0x00100000:
 175                         out_be32(&ddr->sdram_md_cntl,
 176                                 MD_CNTL_MD_EN           |
 177                                 MD_CNTL_CS_SEL_CS0_CS1  |
 178                                 0x04000000              |
 179                                 MD_CNTL_WRCW            |
 180                                 MD_CNTL_MD_VALUE(0x0a));
 181                         break;
 182                 case 0x00200000:
 183                         out_be32(&ddr->sdram_md_cntl,
 184                                 MD_CNTL_MD_EN           |
 185                                 MD_CNTL_CS_SEL_CS0_CS1  |
 186                                 0x04000000              |
 187                                 MD_CNTL_WRCW            |
 188                                 MD_CNTL_MD_VALUE(0x12));
 189                         break;
 190                 case 0x00300000:
 191                         out_be32(&ddr->sdram_md_cntl,
 192                                 MD_CNTL_MD_EN           |
 193                                 MD_CNTL_CS_SEL_CS0_CS1  |
 194                                 0x04000000              |
 195                                 MD_CNTL_WRCW            |
 196                                 MD_CNTL_MD_VALUE(0x1a));
 197                         break;
 198                 default:
 199                         out_be32(&ddr->sdram_md_cntl,
 200                                 MD_CNTL_MD_EN           |
 201                                 MD_CNTL_CS_SEL_CS0_CS1  |
 202                                 0x04000000              |
 203                                 MD_CNTL_WRCW            |
 204                                 MD_CNTL_MD_VALUE(0x02));
 205                         printf("Unsupported RC10\n");
 206                         break;
 207                 }
 208
 209                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 210                         ;
 211                 udelay(6);
 212                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 213                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 214                 out_be32(&ddr->debug[2], 0x0);
 215                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 216                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 217                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 218                 out_be32(&ddr->debug[12], 0x0);
 219                 out_be32(&ddr->debug[21], 0x0);
 220                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 221
 222         }
 223 #endif
 224         /*
 225          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 226          * when operatiing in 32-bit bus mode with 4-beat bursts,
 227          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 228          */
 229 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 230         debug("Workaround for ERRATUM_DDR_115\n");
 231         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 232             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 233                 /* set DEBUG_1[31] */
 234                 setbits_be32(&ddr->debug[0], 1);
 235         }
 236 #endif
 237 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 238         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 239         /*
 240          * This is the combined workaround for DDR111 and DDR134
 241          * following the published errata for MPC8572
 242          */
 243
 244         /* 1. Set EEBACR[3] */
 245         setbits_be32(&ecm->eebacr, 0x10000000);
 246         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 247
 248         /* 2. Set DINIT in SDRAM_CFG_2*/
 249         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 250         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 251                 in_be32(&ddr->sdram_cfg_2));
 252
 253         /* 3. Set DEBUG_3[21] */
 254         setbits_be32(&ddr->debug[2], 0x400);
 255         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 256
 257 #endif  /* part 1 of the workaound */
 258
 259         /*
 260          * 500 painful micro-seconds must elapse between
 261          * the DDR clock setup and the DDR config enable.
 262          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 263          * we choose the max, that is 500 us for all of case.
 264          */
 265         udelay(500);
 266         asm volatile("sync;isync");
 267
 268         /* Let the controller go */
 269         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 270         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 271         asm volatile("sync;isync");
 272
 273         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 274         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 275                 udelay(10000);          /* throttle polling rate */
 276
 277 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 278         /* continue this workaround */
 279
 280         /* 4. Clear DEBUG3[21] */
 281         clrbits_be32(&ddr->debug[2], 0x400);
 282         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 283
 284         /* DDR134 workaround starts */
 285         /* A: Clear sdram_cfg_2[odt_cfg] */
 286         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 287         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 288                 in_be32(&ddr->sdram_cfg_2));
 289
 290         /* B: Set DEBUG1[15] */
 291         setbits_be32(&ddr->debug[0], 0x10000);
 292         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 293
 294         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 295         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 296         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 297                 in_be32(&ddr->timing_cfg_2));
 298
 299         /* D: Set D6 to 0x9f9f9f9f */
 300         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 301         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 302
 303         /* E: Set D7 to 0x9f9f9f9f */
 304         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 305         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 306
 307         /* F: Set D2[20] */
 308         setbits_be32(&ddr->debug[1], 0x800);
 309         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 310
 311         /* G: Poll on D2[20] until cleared */
 312         while (in_be32(&ddr->debug[1]) & 0x800)
 313                 udelay(10000);          /* throttle polling rate */
 314
 315         /* H: Clear D1[15] */
 316         clrbits_be32(&ddr->debug[0], 0x10000);
 317         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 318
 319         /* I: Set sdram_cfg_2[odt_cfg] */
 320         setbits_be32(&ddr->sdram_cfg_2,
 321                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 322         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 323
 324         /* Continuing with the DDR111 workaround */
 325         /* 5. Set D2[21] */
 326         setbits_be32(&ddr->debug[1], 0x400);
 327         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 328
 329         /* 6. Poll D2[21] until its cleared */
 330         while (in_be32(&ddr->debug[1]) & 0x400)
 331                 udelay(10000);          /* throttle polling rate */
 332
 333         /* 7. Wait for 400ms/GB */
 334         total_gb_size_per_controller = 0;
 335         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 336                 if (i == csn) {
 337                         total_gb_size_per_controller +=
 338                                 ((csn_bnds_backup & 0xFFFF) >> 6)
 339                                 - (csn_bnds_backup >> 22) + 1;
 340                 } else {
 341                         total_gb_size_per_controller +=
 342                                 ((regs->cs[i].bnds & 0xFFFF) >> 6)
 343                                 - (regs->cs[i].bnds >> 22) + 1;
 344                 }
 345         }
 346         if (in_be32(&ddr->sdram_cfg) & 0x80000)
 347                 total_gb_size_per_controller <<= 1;
 348         debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
 349         udelay(total_gb_size_per_controller * 400000);
 350
 351         /* 8. Set sdram_cfg_2[dinit] if options requires */
 352         setbits_be32(&ddr->sdram_cfg_2,
 353                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 354         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 355
 356         /* 9. Poll until dinit is cleared */
 357         while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
 358                 udelay(10000);
 359
 360         /* 10. Clear EEBACR[3] */
 361         clrbits_be32(&ecm->eebacr, 10000000);
 362         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 363
 364         if (csn != -1) {
 365                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 366                 *csn_bnds_t = csn_bnds_backup;
 367                 debug("Change cs%d_bnds back to 0x%08x\n",
 368                         csn, regs->cs[csn].bnds);
 369                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 370                 switch (csn) {
 371                 case 0:
 372                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 373                         break;
 374                 case 1:
 375                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 376                         break;
 377                 case 2:
 378                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 379                         break;
 380                 case 3:
 381                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 382                         break;
 383                 }
 384                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 385         }
 386 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 387 }