2 * Copyright 2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 fsl_lbc_t *lbc = LBC_BASE_ADDR;
31 * LCRR - Clock Ratio Register - set up local bus timing
34 out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
36 #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
37 set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
38 set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
40 #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
43 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
44 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
48 out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
50 /* set MBECCDIS=1, SBECCDIS=1 */
51 out_be32(&l2cache->l2errdis,
52 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
54 /* set L2E=1 & L2SRAM=001 */
55 out_be32(&l2cache->l2ctl,
56 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
58 /* Initialize L2 SRAM to zero */
59 l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
60 for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)