2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
28 #include <linux/compiler.h>
30 #ifdef CONFIG_FSL_CAAM
33 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
38 #include "../../../../drivers/block/fsl_sata.h"
40 #include "../../../../drivers/qe/qe.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
47 * For deriving usb clock from 100MHz sysclk, reference divisor is set
48 * to a value of 5, which gives an intermediate value 20(100/5). The
49 * multiplication factor integer is set to 24, which when multiplied to
50 * above intermediate value provides clock for usb ip.
52 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
56 get_sys_info(&sysinfo);
57 if (sysinfo.diff_sysclk == 1) {
58 clrbits_be32(&usb_phy->pllprg[1],
59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
60 setbits_be32(&usb_phy->pllprg[1],
61 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
62 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
63 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
68 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
69 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
71 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
72 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
74 /* Increase Disconnect Threshold by 50mV */
75 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
76 INC_DCNT_THRESHOLD_50MV;
77 /* Enable programming of USB High speed Disconnect threshold */
78 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
79 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
81 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
82 /* Increase Disconnect Threshold by 50mV */
83 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
84 INC_DCNT_THRESHOLD_50MV;
85 /* Enable programming of USB High speed Disconnect threshold */
86 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
87 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
91 u32 status = in_be32(&usb_phy->status1);
93 u32 squelch_prog_rd_0_2 =
94 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
95 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
97 u32 squelch_prog_rd_3_5 =
98 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
99 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
101 setbits_be32(&usb_phy->config1,
102 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
103 setbits_be32(&usb_phy->config2,
104 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
106 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
109 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
110 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
116 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
117 extern qe_iop_conf_t qe_iop_conf_tab[];
118 extern void qe_config_iopin(u8 port, u8 pin, int dir,
119 int open_drain, int assign);
120 extern void qe_init(uint qe_base);
121 extern void qe_reset(void);
123 static void config_qe_ioports(void)
126 int dir, open_drain, assign;
129 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
130 port = qe_iop_conf_tab[i].port;
131 pin = qe_iop_conf_tab[i].pin;
132 dir = qe_iop_conf_tab[i].dir;
133 open_drain = qe_iop_conf_tab[i].open_drain;
134 assign = qe_iop_conf_tab[i].assign;
135 qe_config_iopin(port, pin, dir, open_drain, assign);
141 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
145 for (portnum = 0; portnum < 4; portnum++) {
152 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
153 iop_conf_t *eiopc = iopc + 32;
158 * index 0 refers to pin 31,
159 * index 31 refers to pin 0
161 while (iopc < eiopc) {
181 volatile ioport_t *iop = ioport_addr (cpm, portnum);
185 * the (somewhat confused) paragraph at the
186 * bottom of page 35-5 warns that there might
187 * be "unknown behaviour" when programming
188 * PSORx and PDIRx, if PPARx = 1, so I
189 * decided this meant I had to disable the
190 * dedicated function first, and enable it
194 iop->psor = (iop->psor & tpmsk) | psor;
195 iop->podr = (iop->podr & tpmsk) | podr;
196 iop->pdat = (iop->pdat & tpmsk) | pdat;
197 iop->pdir = (iop->pdir & tpmsk) | pdir;
204 #ifdef CONFIG_SYS_FSL_CPC
205 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
206 void disable_cpc_sram(void)
210 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
212 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
213 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
214 /* find and disable LAW of SRAM */
215 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
217 if (law.index == -1) {
218 printf("\nFatal error happened\n");
221 disable_law(law.index);
223 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
224 out_be32(&cpc->cpccsr0, 0);
225 out_be32(&cpc->cpcsrcr0, 0);
231 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
233 #error POST memory test cannot be enabled with TDM
235 static void enable_tdm_law(void)
238 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
239 int tdm_hwconfig_enabled = 0;
242 * Extract hwconfig from environment since environment
243 * is not setup properly yet. Search for tdm entry in
246 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
248 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
249 /* If tdm is defined in hwconfig, set law for tdm workaround */
250 if (tdm_hwconfig_enabled)
251 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
257 void enable_cpc(void)
263 char buffer[HWCONFIG_BUFFER_SIZE];
265 bool have_hwconfig = false;
267 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
269 /* Extract hwconfig from environment */
270 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
273 * If "en_cpc" is not defined in hwconfig then by default all
274 * cpcs are enable. If this config is defined then individual
275 * cpcs which have to be enabled should also be defined.
276 * e.g en_cpc:cpc1,cpc2;
278 if (hwconfig_f("en_cpc", buffer))
279 have_hwconfig = true;
282 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
284 sprintf(cpc_subarg, "cpc%u", i + 1);
285 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
289 cpccfg0 = in_be32(&cpc->cpccfg0);
290 size += CPC_CFG0_SZ_K(cpccfg0);
292 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
293 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
295 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
296 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
298 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
299 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
301 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
302 if (has_erratum_a006379()) {
303 setbits_be32(&cpc->cpchdbcr0,
304 CPC_HDBCR0_SPLRU_LEVEL_EN);
308 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
309 /* Read back to sync write */
310 in_be32(&cpc->cpccsr0);
314 puts("Corenet Platform Cache: ");
315 print_size(size * 1024, " enabled\n");
318 static void invalidate_cpc(void)
321 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
323 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
324 /* skip CPC when it used as all SRAM */
325 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
327 /* Flash invalidate the CPC and clear all the locks */
328 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
329 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
335 #define invalidate_cpc()
336 #define disable_cpc_sram()
337 #endif /* CONFIG_SYS_FSL_CPC */
340 * Breathe some life into the CPU...
342 * Set up the memory map
343 * initialize a bunch of registers
346 #ifdef CONFIG_FSL_CORENET
347 static void corenet_tb_init(void)
349 volatile ccsr_rcpm_t *rcpm =
350 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
351 volatile ccsr_pic_t *pic =
352 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
353 u32 whoami = in_be32(&pic->whoami);
355 /* Enable the timebase register for this core */
356 out_be32(&rcpm->ctbenrl, (1 << whoami));
360 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
361 void fsl_erratum_a007212_workaround(void)
363 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
365 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
366 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
367 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
368 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
369 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
370 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
372 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
373 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
377 * Even this workaround applies to selected version of SoCs, it is
378 * safe to apply to all versions, with the limitation of odd ratios.
379 * If RCW has disabled DDR PLL, we have to apply this workaround,
380 * otherwise DDR will not work.
382 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
383 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
384 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
385 /* check if RCW sets ratio to 0, required by this workaround */
386 if (ddr_pll_ratio != 0)
388 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
389 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
390 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
391 /* check if reserved bits have the desired ratio */
392 if (ddr_pll_ratio == 0) {
393 printf("Error: Unknown DDR PLL ratio!\n");
398 setbits_be32(plldadcr1, 0x02000001);
399 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
400 setbits_be32(plldadcr2, 0x02000001);
401 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
402 setbits_be32(plldadcr3, 0x02000001);
405 setbits_be32(dpdovrcr4, 0xe0000000);
406 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
407 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
408 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
409 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
410 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
414 clrbits_be32(plldadcr1, 0x02000001);
415 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
416 clrbits_be32(plldadcr2, 0x02000001);
417 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
418 clrbits_be32(plldadcr3, 0x02000001);
421 clrbits_be32(dpdovrcr4, 0xe0000000);
425 ulong cpu_init_f(void)
427 extern void m8560_cpm_reset (void);
428 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
429 (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
430 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
432 #if defined(CONFIG_SECURE_BOOT)
433 struct law_entry law;
435 #ifdef CONFIG_MPC8548
436 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
437 uint svr = get_svr();
440 * CPU2 errata workaround: A core hang possible while executing
441 * a msync instruction and a snoopable transaction from an I/O
442 * master tagged to make quick forward progress is present.
443 * Fixed in silicon rev 2.1.
445 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
446 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
452 #if defined(CONFIG_SECURE_BOOT)
453 /* Disable the LAW created for NOR flash by the PBI commands */
454 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
456 disable_law(law.index);
458 #if defined(CONFIG_SYS_CPC_REINIT_F)
462 #if defined(CONFIG_FSL_CORENET)
463 /* Put PAMU in bypass mode */
464 out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
470 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
473 init_early_memctl_regs();
475 #if defined(CONFIG_CPM2)
479 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
480 /* Config QE ioports */
484 #if defined(CONFIG_FSL_DMA)
487 #ifdef CONFIG_FSL_CORENET
490 init_used_tlb_cams();
492 /* Invalidate the CPC before DDR gets enabled */
495 #ifdef CONFIG_SYS_DCSRBAR_PHYS
496 /* set DCSRCR so that DCSR space is 1G */
497 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
498 in_be32(&gur->dcsrcr);
501 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
502 fsl_erratum_a007212_workaround();
508 /* Implement a dummy function for those platforms w/o SERDES */
509 static void __fsl_serdes__init(void)
513 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
515 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
516 int enable_cluster_l2(void)
519 u32 cluster, svr = get_svr();
520 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
521 struct ccsr_cluster_l2 __iomem *l2cache;
523 /* only the L2 of first cluster should be enabled as expected on T4080,
524 * but there is no EOC in the first cluster as HW sake, so return here
525 * to skip enabling L2 cache of the 2nd cluster.
527 if (SVR_SOC_VER(svr) == SVR_T4080)
530 cluster = in_be32(&gur->tp_cluster[i].lower);
531 if (cluster & TP_CLUSTER_EOC)
534 /* The first cache has already been set up, so skip it */
537 /* Look through the remaining clusters, and set up their caches */
539 int j, cluster_valid = 0;
541 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
543 cluster = in_be32(&gur->tp_cluster[i].lower);
545 /* check that at least one core/accel is enabled in cluster */
546 for (j = 0; j < 4; j++) {
547 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
548 u32 type = in_be32(&gur->tp_ityp[idx]);
550 if ((type & TP_ITYP_AV) &&
551 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
556 /* set stash ID to (cluster) * 2 + 32 + 1 */
557 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
559 printf("enable l2 for cluster %d %p\n", i, l2cache);
561 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
562 while ((in_be32(&l2cache->l2csr0)
563 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
565 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
568 } while (!(cluster & TP_CLUSTER_EOC));
575 * Initialize L2 as cache.
577 int l2cache_init(void)
579 __maybe_unused u32 svr = get_svr();
580 #ifdef CONFIG_L2_CACHE
581 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
582 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
583 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
588 #if defined(CONFIG_L2_CACHE)
589 volatile uint cache_ctl;
593 ver = SVR_SOC_VER(svr);
596 cache_ctl = l2cache->l2ctl;
598 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
599 if (cache_ctl & MPC85xx_L2CTL_L2E) {
600 /* Clear L2 SRAM memory-mapped base address */
601 out_be32(&l2cache->l2srbar0, 0x0);
602 out_be32(&l2cache->l2srbar1, 0x0);
604 /* set MBECCDIS=0, SBECCDIS=0 */
605 clrbits_be32(&l2cache->l2errdis,
606 (MPC85xx_L2ERRDIS_MBECC |
607 MPC85xx_L2ERRDIS_SBECC));
609 /* set L2E=0, L2SRAM=0 */
610 clrbits_be32(&l2cache->l2ctl,
612 MPC85xx_L2CTL_L2SRAM_ENTIRE));
616 l2siz_field = (cache_ctl >> 28) & 0x3;
618 switch (l2siz_field) {
620 printf(" unknown size (0x%08x)\n", cache_ctl);
624 if (ver == SVR_8540 || ver == SVR_8560 ||
625 ver == SVR_8541 || ver == SVR_8555) {
627 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
628 cache_ctl = 0xc4000000;
631 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
635 if (ver == SVR_8540 || ver == SVR_8560 ||
636 ver == SVR_8541 || ver == SVR_8555) {
638 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
639 cache_ctl = 0xc8000000;
642 /* set L2E=1, L2I=1, & L2SRAM=0 */
643 cache_ctl = 0xc0000000;
648 /* set L2E=1, L2I=1, & L2SRAM=0 */
649 cache_ctl = 0xc0000000;
653 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
654 puts("already enabled");
655 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
656 u32 l2srbar = l2cache->l2srbar0;
657 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
658 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
659 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
660 l2cache->l2srbar0 = l2srbar;
661 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
663 #endif /* CONFIG_SYS_INIT_L2_ADDR */
667 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
671 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
672 if (SVR_SOC_VER(svr) == SVR_P2040) {
677 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
679 /* invalidate the L2 cache */
680 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
681 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
684 #ifdef CONFIG_SYS_CACHE_STASHING
685 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
686 mtspr(SPRN_L2CSR1, (32 + 1));
689 /* enable the cache */
690 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
692 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
693 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
695 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
699 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
700 if (l2cache->l2csr0 & L2CSR0_L2E)
701 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
714 * The newer 8548, etc, parts have twice as much cache, but
715 * use the same bit-encoding as the older 8555, etc, parts.
720 __maybe_unused u32 svr = get_svr();
721 #ifdef CONFIG_SYS_LBC_LCRR
722 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
724 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
725 extern int spin_table_compat;
728 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
729 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
731 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
732 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
734 * CPU22 and NMG_CPU_A011 share the same workaround.
735 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
736 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
737 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
738 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
739 * be disabled by hwconfig with syntax:
741 * fsl_cpu_a011:disable
743 extern int enable_cpu_a011_workaround;
744 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
745 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
747 char buffer[HWCONFIG_BUFFER_SIZE];
751 n = getenv_f("hwconfig", buffer, sizeof(buffer));
755 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
757 enable_cpu_a011_workaround = 0;
759 if (n >= HWCONFIG_BUFFER_SIZE) {
760 printf("fsl_cpu_a011 was not found. hwconfig variable "
761 "may be too long\n");
763 enable_cpu_a011_workaround =
764 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
765 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
768 if (enable_cpu_a011_workaround) {
770 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
774 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
776 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
777 * in write shadow mode. Checking DCWS before setting SPR 976.
779 if (mfspr(L1CSR2) & L1CSR2_DCWS)
780 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
783 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
784 spin = getenv("spin_table_compat");
785 if (spin && (*spin == 'n'))
786 spin_table_compat = 0;
788 spin_table_compat = 1;
792 #if defined(CONFIG_RAMBOOT_PBL)
796 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
800 #ifndef CONFIG_SYS_FSL_NO_SERDES
801 /* needs to be in ram since code uses global static vars */
805 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
806 #define MCFGR_AXIPIPE 0x000000f0
807 if (IS_SVR_REV(svr, 1, 0))
808 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
811 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
812 if (IS_SVR_REV(svr, 1, 0)) {
814 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
816 for (i = 0; i < 12; i++) {
817 p += i + (i > 5 ? 11 : 0);
820 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
825 #ifdef CONFIG_SYS_SRIO
827 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
828 char *s = getenv("bootmaster");
830 if (!strcmp(s, "SRIO1")) {
832 srio_boot_master_release_slave(1);
834 if (!strcmp(s, "SRIO2")) {
836 srio_boot_master_release_slave(2);
842 #if defined(CONFIG_MP)
846 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
848 if (SVR_MAJ(svr) < 3) {
850 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
851 setbits_be32(p, 1 << (31 - 14));
856 #ifdef CONFIG_SYS_LBC_LCRR
858 * Modify the CLKDIV field of LCRR register to improve the writing
859 * speed for NOR flash.
861 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
862 __raw_readl(&lbc->lcrr);
864 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
869 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
871 struct ccsr_usb_phy __iomem *usb_phy1 =
872 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
873 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
874 if (has_erratum_a006261())
875 fsl_erratum_a006261_workaround(usb_phy1);
877 out_be32(&usb_phy1->usb_enable_override,
878 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
881 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
883 struct ccsr_usb_phy __iomem *usb_phy2 =
884 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
885 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
886 if (has_erratum_a006261())
887 fsl_erratum_a006261_workaround(usb_phy2);
889 out_be32(&usb_phy2->usb_enable_override,
890 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
894 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
895 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
896 * multi-bit ECC errors which has impact on performance, so software
897 * should disable all ECC reporting from USB1 and USB2.
899 if (IS_SVR_REV(get_svr(), 1, 0)) {
900 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
901 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
902 setbits_be32(&dcfg->ecccr1,
903 (DCSR_DCFG_ECC_DISABLE_USB1 |
904 DCSR_DCFG_ECC_DISABLE_USB2));
908 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
909 struct ccsr_usb_phy __iomem *usb_phy =
910 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
911 setbits_be32(&usb_phy->pllprg[1],
912 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
913 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
914 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
915 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
916 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
917 usb_single_source_clk_configure(usb_phy);
919 setbits_be32(&usb_phy->port1.ctrl,
920 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
921 setbits_be32(&usb_phy->port1.drvvbuscfg,
922 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
923 setbits_be32(&usb_phy->port1.pwrfltcfg,
924 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
925 setbits_be32(&usb_phy->port2.ctrl,
926 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
927 setbits_be32(&usb_phy->port2.drvvbuscfg,
928 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
929 setbits_be32(&usb_phy->port2.pwrfltcfg,
930 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
932 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
933 if (has_erratum_a006261())
934 fsl_erratum_a006261_workaround(usb_phy);
937 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
939 #ifdef CONFIG_FMAN_ENET
943 #ifdef CONFIG_FSL_CAAM
947 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
949 * For P1022/1013 Rev1.0 silicon, after power on SATA host
950 * controller is configured in legacy mode instead of the
951 * expected enterprise mode. Software needs to clear bit[28]
952 * of HControl register to change to enterprise mode from
953 * legacy mode. We assume that the controller is offline.
955 if (IS_SVR_REV(svr, 1, 0) &&
956 ((SVR_SOC_VER(svr) == SVR_P1022) ||
957 (SVR_SOC_VER(svr) == SVR_P1013))) {
960 /* first SATA controller */
961 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
962 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
964 /* second SATA controller */
965 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
966 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
970 init_used_tlb_cams();
975 void arch_preboot_os(void)
980 * We are changing interrupt offsets and are about to boot the OS so
981 * we need to make sure we disable all async interrupts. EE is already
982 * disabled by the time we get called.
985 msr &= ~(MSR_ME|MSR_CE);
989 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
990 int sata_initialize(void)
992 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
993 return __sata_initialize();
999 void cpu_secondary_init_r(void)
1002 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1003 #elif defined CONFIG_QE
1004 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */