2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
28 #include <linux/compiler.h>
30 #ifdef CONFIG_CHAIN_OF_TRUST
31 #include <fsl_validate.h>
33 #ifdef CONFIG_FSL_CAAM
36 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
41 #include "../../../../drivers/block/fsl_sata.h"
43 #include "../../../../drivers/qe/qe.h"
46 DECLARE_GLOBAL_DATA_PTR;
48 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
50 * For deriving usb clock from 100MHz sysclk, reference divisor is set
51 * to a value of 5, which gives an intermediate value 20(100/5). The
52 * multiplication factor integer is set to 24, which when multiplied to
53 * above intermediate value provides clock for usb ip.
55 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
59 get_sys_info(&sysinfo);
60 if (sysinfo.diff_sysclk == 1) {
61 clrbits_be32(&usb_phy->pllprg[1],
62 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
63 setbits_be32(&usb_phy->pllprg[1],
64 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
65 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
66 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
71 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
72 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
74 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
75 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
77 /* Increase Disconnect Threshold by 50mV */
78 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
79 INC_DCNT_THRESHOLD_50MV;
80 /* Enable programming of USB High speed Disconnect threshold */
81 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
82 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
84 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
85 /* Increase Disconnect Threshold by 50mV */
86 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
87 INC_DCNT_THRESHOLD_50MV;
88 /* Enable programming of USB High speed Disconnect threshold */
89 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
90 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
94 u32 status = in_be32(&usb_phy->status1);
96 u32 squelch_prog_rd_0_2 =
97 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
98 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
100 u32 squelch_prog_rd_3_5 =
101 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
102 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
104 setbits_be32(&usb_phy->config1,
105 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
106 setbits_be32(&usb_phy->config2,
107 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
109 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
110 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
112 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
113 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
119 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
120 extern qe_iop_conf_t qe_iop_conf_tab[];
121 extern void qe_config_iopin(u8 port, u8 pin, int dir,
122 int open_drain, int assign);
123 extern void qe_init(uint qe_base);
124 extern void qe_reset(void);
126 static void config_qe_ioports(void)
129 int dir, open_drain, assign;
132 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
133 port = qe_iop_conf_tab[i].port;
134 pin = qe_iop_conf_tab[i].pin;
135 dir = qe_iop_conf_tab[i].dir;
136 open_drain = qe_iop_conf_tab[i].open_drain;
137 assign = qe_iop_conf_tab[i].assign;
138 qe_config_iopin(port, pin, dir, open_drain, assign);
144 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
148 for (portnum = 0; portnum < 4; portnum++) {
155 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
156 iop_conf_t *eiopc = iopc + 32;
161 * index 0 refers to pin 31,
162 * index 31 refers to pin 0
164 while (iopc < eiopc) {
184 volatile ioport_t *iop = ioport_addr (cpm, portnum);
188 * the (somewhat confused) paragraph at the
189 * bottom of page 35-5 warns that there might
190 * be "unknown behaviour" when programming
191 * PSORx and PDIRx, if PPARx = 1, so I
192 * decided this meant I had to disable the
193 * dedicated function first, and enable it
197 iop->psor = (iop->psor & tpmsk) | psor;
198 iop->podr = (iop->podr & tpmsk) | podr;
199 iop->pdat = (iop->pdat & tpmsk) | pdat;
200 iop->pdir = (iop->pdir & tpmsk) | pdir;
207 #ifdef CONFIG_SYS_FSL_CPC
208 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
209 void disable_cpc_sram(void)
213 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
215 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
216 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
217 /* find and disable LAW of SRAM */
218 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
220 if (law.index == -1) {
221 printf("\nFatal error happened\n");
224 disable_law(law.index);
226 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
227 out_be32(&cpc->cpccsr0, 0);
228 out_be32(&cpc->cpcsrcr0, 0);
234 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
236 #error POST memory test cannot be enabled with TDM
238 static void enable_tdm_law(void)
241 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
242 int tdm_hwconfig_enabled = 0;
245 * Extract hwconfig from environment since environment
246 * is not setup properly yet. Search for tdm entry in
249 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
251 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
252 /* If tdm is defined in hwconfig, set law for tdm workaround */
253 if (tdm_hwconfig_enabled)
254 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
260 void enable_cpc(void)
266 char buffer[HWCONFIG_BUFFER_SIZE];
268 bool have_hwconfig = false;
270 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
272 /* Extract hwconfig from environment */
273 ret = getenv_f("hwconfig", buffer, sizeof(buffer));
276 * If "en_cpc" is not defined in hwconfig then by default all
277 * cpcs are enable. If this config is defined then individual
278 * cpcs which have to be enabled should also be defined.
279 * e.g en_cpc:cpc1,cpc2;
281 if (hwconfig_f("en_cpc", buffer))
282 have_hwconfig = true;
285 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
287 sprintf(cpc_subarg, "cpc%u", i + 1);
288 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
292 cpccfg0 = in_be32(&cpc->cpccfg0);
293 size += CPC_CFG0_SZ_K(cpccfg0);
295 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
296 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
298 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
299 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
301 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
302 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
304 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
305 if (has_erratum_a006379()) {
306 setbits_be32(&cpc->cpchdbcr0,
307 CPC_HDBCR0_SPLRU_LEVEL_EN);
311 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
312 /* Read back to sync write */
313 in_be32(&cpc->cpccsr0);
317 puts("Corenet Platform Cache: ");
318 print_size(size * 1024, " enabled\n");
321 static void invalidate_cpc(void)
324 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
326 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
327 /* skip CPC when it used as all SRAM */
328 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
330 /* Flash invalidate the CPC and clear all the locks */
331 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
332 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
338 #define invalidate_cpc()
339 #define disable_cpc_sram()
340 #endif /* CONFIG_SYS_FSL_CPC */
343 * Breathe some life into the CPU...
345 * Set up the memory map
346 * initialize a bunch of registers
349 #ifdef CONFIG_FSL_CORENET
350 static void corenet_tb_init(void)
352 volatile ccsr_rcpm_t *rcpm =
353 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
354 volatile ccsr_pic_t *pic =
355 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
356 u32 whoami = in_be32(&pic->whoami);
358 /* Enable the timebase register for this core */
359 out_be32(&rcpm->ctbenrl, (1 << whoami));
363 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
364 void fsl_erratum_a007212_workaround(void)
366 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
368 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
369 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
370 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
371 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
372 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
373 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
374 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
375 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
376 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
380 * Even this workaround applies to selected version of SoCs, it is
381 * safe to apply to all versions, with the limitation of odd ratios.
382 * If RCW has disabled DDR PLL, we have to apply this workaround,
383 * otherwise DDR will not work.
385 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
386 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
387 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
388 /* check if RCW sets ratio to 0, required by this workaround */
389 if (ddr_pll_ratio != 0)
391 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
392 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
393 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
394 /* check if reserved bits have the desired ratio */
395 if (ddr_pll_ratio == 0) {
396 printf("Error: Unknown DDR PLL ratio!\n");
401 setbits_be32(plldadcr1, 0x02000001);
402 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
403 setbits_be32(plldadcr2, 0x02000001);
404 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
405 setbits_be32(plldadcr3, 0x02000001);
408 setbits_be32(dpdovrcr4, 0xe0000000);
409 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
410 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
411 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
412 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
413 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
417 clrbits_be32(plldadcr1, 0x02000001);
418 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
419 clrbits_be32(plldadcr2, 0x02000001);
420 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
421 clrbits_be32(plldadcr3, 0x02000001);
424 clrbits_be32(dpdovrcr4, 0xe0000000);
428 ulong cpu_init_f(void)
430 extern void m8560_cpm_reset (void);
431 #if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
432 (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
433 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
435 #if defined(CONFIG_SECURE_BOOT)
436 struct law_entry law;
438 #ifdef CONFIG_MPC8548
439 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
440 uint svr = get_svr();
443 * CPU2 errata workaround: A core hang possible while executing
444 * a msync instruction and a snoopable transaction from an I/O
445 * master tagged to make quick forward progress is present.
446 * Fixed in silicon rev 2.1.
448 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
449 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
455 #if defined(CONFIG_SECURE_BOOT)
456 /* Disable the LAW created for NOR flash by the PBI commands */
457 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
459 disable_law(law.index);
461 #if defined(CONFIG_SYS_CPC_REINIT_F)
465 #if defined(CONFIG_FSL_CORENET)
466 /* Put PAMU in bypass mode */
467 out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
473 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
476 init_early_memctl_regs();
478 #if defined(CONFIG_CPM2)
482 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
483 /* Config QE ioports */
487 #if defined(CONFIG_FSL_DMA)
490 #ifdef CONFIG_FSL_CORENET
493 init_used_tlb_cams();
495 /* Invalidate the CPC before DDR gets enabled */
498 #ifdef CONFIG_SYS_DCSRBAR_PHYS
499 /* set DCSRCR so that DCSR space is 1G */
500 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
501 in_be32(&gur->dcsrcr);
504 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
505 fsl_erratum_a007212_workaround();
511 /* Implement a dummy function for those platforms w/o SERDES */
512 static void __fsl_serdes__init(void)
516 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
518 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
519 int enable_cluster_l2(void)
522 u32 cluster, svr = get_svr();
523 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
524 struct ccsr_cluster_l2 __iomem *l2cache;
526 /* only the L2 of first cluster should be enabled as expected on T4080,
527 * but there is no EOC in the first cluster as HW sake, so return here
528 * to skip enabling L2 cache of the 2nd cluster.
530 if (SVR_SOC_VER(svr) == SVR_T4080)
533 cluster = in_be32(&gur->tp_cluster[i].lower);
534 if (cluster & TP_CLUSTER_EOC)
537 /* The first cache has already been set up, so skip it */
540 /* Look through the remaining clusters, and set up their caches */
542 int j, cluster_valid = 0;
544 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
546 cluster = in_be32(&gur->tp_cluster[i].lower);
548 /* check that at least one core/accel is enabled in cluster */
549 for (j = 0; j < 4; j++) {
550 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
551 u32 type = in_be32(&gur->tp_ityp[idx]);
553 if ((type & TP_ITYP_AV) &&
554 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
559 /* set stash ID to (cluster) * 2 + 32 + 1 */
560 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
562 printf("enable l2 for cluster %d %p\n", i, l2cache);
564 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
565 while ((in_be32(&l2cache->l2csr0)
566 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
568 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
571 } while (!(cluster & TP_CLUSTER_EOC));
578 * Initialize L2 as cache.
580 int l2cache_init(void)
582 __maybe_unused u32 svr = get_svr();
583 #ifdef CONFIG_L2_CACHE
584 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
585 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
586 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
591 #if defined(CONFIG_L2_CACHE)
592 volatile uint cache_ctl;
596 ver = SVR_SOC_VER(svr);
599 cache_ctl = l2cache->l2ctl;
601 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
602 if (cache_ctl & MPC85xx_L2CTL_L2E) {
603 /* Clear L2 SRAM memory-mapped base address */
604 out_be32(&l2cache->l2srbar0, 0x0);
605 out_be32(&l2cache->l2srbar1, 0x0);
607 /* set MBECCDIS=0, SBECCDIS=0 */
608 clrbits_be32(&l2cache->l2errdis,
609 (MPC85xx_L2ERRDIS_MBECC |
610 MPC85xx_L2ERRDIS_SBECC));
612 /* set L2E=0, L2SRAM=0 */
613 clrbits_be32(&l2cache->l2ctl,
615 MPC85xx_L2CTL_L2SRAM_ENTIRE));
619 l2siz_field = (cache_ctl >> 28) & 0x3;
621 switch (l2siz_field) {
623 printf(" unknown size (0x%08x)\n", cache_ctl);
627 if (ver == SVR_8540 || ver == SVR_8560 ||
628 ver == SVR_8541 || ver == SVR_8555) {
630 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
631 cache_ctl = 0xc4000000;
634 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
638 if (ver == SVR_8540 || ver == SVR_8560 ||
639 ver == SVR_8541 || ver == SVR_8555) {
641 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
642 cache_ctl = 0xc8000000;
645 /* set L2E=1, L2I=1, & L2SRAM=0 */
646 cache_ctl = 0xc0000000;
651 /* set L2E=1, L2I=1, & L2SRAM=0 */
652 cache_ctl = 0xc0000000;
656 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
657 puts("already enabled");
658 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
659 u32 l2srbar = l2cache->l2srbar0;
660 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
661 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
662 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
663 l2cache->l2srbar0 = l2srbar;
664 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
666 #endif /* CONFIG_SYS_INIT_L2_ADDR */
670 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
674 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
675 if (SVR_SOC_VER(svr) == SVR_P2040) {
680 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
682 /* invalidate the L2 cache */
683 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
684 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
687 #ifdef CONFIG_SYS_CACHE_STASHING
688 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
689 mtspr(SPRN_L2CSR1, (32 + 1));
692 /* enable the cache */
693 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
695 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
696 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
698 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
702 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
703 if (l2cache->l2csr0 & L2CSR0_L2E)
704 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
717 * The newer 8548, etc, parts have twice as much cache, but
718 * use the same bit-encoding as the older 8555, etc, parts.
723 __maybe_unused u32 svr = get_svr();
724 #ifdef CONFIG_SYS_LBC_LCRR
725 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
727 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
728 extern int spin_table_compat;
731 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
732 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
734 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
735 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
737 * CPU22 and NMG_CPU_A011 share the same workaround.
738 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
739 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
740 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
741 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
742 * be disabled by hwconfig with syntax:
744 * fsl_cpu_a011:disable
746 extern int enable_cpu_a011_workaround;
747 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
748 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
750 char buffer[HWCONFIG_BUFFER_SIZE];
754 n = getenv_f("hwconfig", buffer, sizeof(buffer));
758 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
760 enable_cpu_a011_workaround = 0;
762 if (n >= HWCONFIG_BUFFER_SIZE) {
763 printf("fsl_cpu_a011 was not found. hwconfig variable "
764 "may be too long\n");
766 enable_cpu_a011_workaround =
767 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
768 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
771 if (enable_cpu_a011_workaround) {
773 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
777 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
779 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
780 * in write shadow mode. Checking DCWS before setting SPR 976.
782 if (mfspr(L1CSR2) & L1CSR2_DCWS)
783 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
786 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
787 spin = getenv("spin_table_compat");
788 if (spin && (*spin == 'n'))
789 spin_table_compat = 0;
791 spin_table_compat = 1;
795 #if defined(CONFIG_RAMBOOT_PBL)
799 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
803 #ifndef CONFIG_SYS_FSL_NO_SERDES
804 /* needs to be in ram since code uses global static vars */
808 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
809 #define MCFGR_AXIPIPE 0x000000f0
810 if (IS_SVR_REV(svr, 1, 0))
811 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
814 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
815 if (IS_SVR_REV(svr, 1, 0)) {
817 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
819 for (i = 0; i < 12; i++) {
820 p += i + (i > 5 ? 11 : 0);
823 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
828 #ifdef CONFIG_SYS_SRIO
830 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
831 char *s = getenv("bootmaster");
833 if (!strcmp(s, "SRIO1")) {
835 srio_boot_master_release_slave(1);
837 if (!strcmp(s, "SRIO2")) {
839 srio_boot_master_release_slave(2);
845 #if defined(CONFIG_MP)
849 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
851 if (SVR_MAJ(svr) < 3) {
853 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
854 setbits_be32(p, 1 << (31 - 14));
859 #ifdef CONFIG_SYS_LBC_LCRR
861 * Modify the CLKDIV field of LCRR register to improve the writing
862 * speed for NOR flash.
864 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
865 __raw_readl(&lbc->lcrr);
867 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
872 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
874 struct ccsr_usb_phy __iomem *usb_phy1 =
875 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
876 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
877 if (has_erratum_a006261())
878 fsl_erratum_a006261_workaround(usb_phy1);
880 out_be32(&usb_phy1->usb_enable_override,
881 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
884 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
886 struct ccsr_usb_phy __iomem *usb_phy2 =
887 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
888 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
889 if (has_erratum_a006261())
890 fsl_erratum_a006261_workaround(usb_phy2);
892 out_be32(&usb_phy2->usb_enable_override,
893 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
897 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
898 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
899 * multi-bit ECC errors which has impact on performance, so software
900 * should disable all ECC reporting from USB1 and USB2.
902 if (IS_SVR_REV(get_svr(), 1, 0)) {
903 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
904 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
905 setbits_be32(&dcfg->ecccr1,
906 (DCSR_DCFG_ECC_DISABLE_USB1 |
907 DCSR_DCFG_ECC_DISABLE_USB2));
911 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
912 struct ccsr_usb_phy __iomem *usb_phy =
913 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
914 setbits_be32(&usb_phy->pllprg[1],
915 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
916 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
917 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
918 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
919 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
920 usb_single_source_clk_configure(usb_phy);
922 setbits_be32(&usb_phy->port1.ctrl,
923 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
924 setbits_be32(&usb_phy->port1.drvvbuscfg,
925 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
926 setbits_be32(&usb_phy->port1.pwrfltcfg,
927 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
928 setbits_be32(&usb_phy->port2.ctrl,
929 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
930 setbits_be32(&usb_phy->port2.drvvbuscfg,
931 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
932 setbits_be32(&usb_phy->port2.pwrfltcfg,
933 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
935 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
936 if (has_erratum_a006261())
937 fsl_erratum_a006261_workaround(usb_phy);
940 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
942 #ifdef CONFIG_FMAN_ENET
946 #ifdef CONFIG_FSL_CAAM
950 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
952 * For P1022/1013 Rev1.0 silicon, after power on SATA host
953 * controller is configured in legacy mode instead of the
954 * expected enterprise mode. Software needs to clear bit[28]
955 * of HControl register to change to enterprise mode from
956 * legacy mode. We assume that the controller is offline.
958 if (IS_SVR_REV(svr, 1, 0) &&
959 ((SVR_SOC_VER(svr) == SVR_P1022) ||
960 (SVR_SOC_VER(svr) == SVR_P1013))) {
963 /* first SATA controller */
964 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
965 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
967 /* second SATA controller */
968 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
969 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
973 init_used_tlb_cams();
978 void arch_preboot_os(void)
983 * We are changing interrupt offsets and are about to boot the OS so
984 * we need to make sure we disable all async interrupts. EE is already
985 * disabled by the time we get called.
988 msr &= ~(MSR_ME|MSR_CE);
992 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
993 int sata_initialize(void)
995 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
996 return __sata_initialize();
1002 void cpu_secondary_init_r(void)
1005 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1006 #elif defined CONFIG_QE
1007 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1016 #ifdef CONFIG_BOARD_LATE_INIT
1017 int board_late_init(void)
1019 #ifdef CONFIG_CHAIN_OF_TRUST
1020 fsl_setenv_chain_of_trust();