2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
20 #include <asm/cache.h>
22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
28 #include <linux/compiler.h>
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
35 #include "../../../../drivers/block/fsl_sata.h"
37 #include "../../../../drivers/qe/qe.h"
40 DECLARE_GLOBAL_DATA_PTR;
42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
44 * For deriving usb clock from 100MHz sysclk, reference divisor is set
45 * to a value of 5, which gives an intermediate value 20(100/5). The
46 * multiplication factor integer is set to 24, which when multiplied to
47 * above intermediate value provides clock for usb ip.
49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
53 get_sys_info(&sysinfo);
54 if (sysinfo.diff_sysclk == 1) {
55 clrbits_be32(&usb_phy->pllprg[1],
56 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
57 setbits_be32(&usb_phy->pllprg[1],
58 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
59 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
60 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
69 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
71 /* Increase Disconnect Threshold by 50mV */
72 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
73 INC_DCNT_THRESHOLD_50MV;
74 /* Enable programming of USB High speed Disconnect threshold */
75 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
76 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
78 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
79 /* Increase Disconnect Threshold by 50mV */
80 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
81 INC_DCNT_THRESHOLD_50MV;
82 /* Enable programming of USB High speed Disconnect threshold */
83 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
84 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
88 u32 status = in_be32(&usb_phy->status1);
90 u32 squelch_prog_rd_0_2 =
91 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
92 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
94 u32 squelch_prog_rd_3_5 =
95 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
96 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
98 setbits_be32(&usb_phy->config1,
99 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
100 setbits_be32(&usb_phy->config2,
101 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
103 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
104 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
106 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
107 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
114 extern qe_iop_conf_t qe_iop_conf_tab[];
115 extern void qe_config_iopin(u8 port, u8 pin, int dir,
116 int open_drain, int assign);
117 extern void qe_init(uint qe_base);
118 extern void qe_reset(void);
120 static void config_qe_ioports(void)
123 int dir, open_drain, assign;
126 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
127 port = qe_iop_conf_tab[i].port;
128 pin = qe_iop_conf_tab[i].pin;
129 dir = qe_iop_conf_tab[i].dir;
130 open_drain = qe_iop_conf_tab[i].open_drain;
131 assign = qe_iop_conf_tab[i].assign;
132 qe_config_iopin(port, pin, dir, open_drain, assign);
138 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
142 for (portnum = 0; portnum < 4; portnum++) {
149 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
150 iop_conf_t *eiopc = iopc + 32;
155 * index 0 refers to pin 31,
156 * index 31 refers to pin 0
158 while (iopc < eiopc) {
178 volatile ioport_t *iop = ioport_addr (cpm, portnum);
182 * the (somewhat confused) paragraph at the
183 * bottom of page 35-5 warns that there might
184 * be "unknown behaviour" when programming
185 * PSORx and PDIRx, if PPARx = 1, so I
186 * decided this meant I had to disable the
187 * dedicated function first, and enable it
191 iop->psor = (iop->psor & tpmsk) | psor;
192 iop->podr = (iop->podr & tpmsk) | podr;
193 iop->pdat = (iop->pdat & tpmsk) | pdat;
194 iop->pdir = (iop->pdir & tpmsk) | pdir;
201 #ifdef CONFIG_SYS_FSL_CPC
202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
203 static void disable_cpc_sram(void)
207 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
209 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
210 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
211 /* find and disable LAW of SRAM */
212 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
214 if (law.index == -1) {
215 printf("\nFatal error happened\n");
218 disable_law(law.index);
220 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
221 out_be32(&cpc->cpccsr0, 0);
222 out_be32(&cpc->cpcsrcr0, 0);
228 static void enable_cpc(void)
233 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
235 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
236 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
237 size += CPC_CFG0_SZ_K(cpccfg0);
239 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
240 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
242 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
243 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
245 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
246 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
248 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
249 if (has_erratum_a006379()) {
250 setbits_be32(&cpc->cpchdbcr0,
251 CPC_HDBCR0_SPLRU_LEVEL_EN);
255 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
256 /* Read back to sync write */
257 in_be32(&cpc->cpccsr0);
261 puts("Corenet Platform Cache: ");
262 print_size(size * 1024, " enabled\n");
265 static void invalidate_cpc(void)
268 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
270 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
271 /* skip CPC when it used as all SRAM */
272 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
274 /* Flash invalidate the CPC and clear all the locks */
275 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
276 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
282 #define invalidate_cpc()
283 #endif /* CONFIG_SYS_FSL_CPC */
286 * Breathe some life into the CPU...
288 * Set up the memory map
289 * initialize a bunch of registers
292 #ifdef CONFIG_FSL_CORENET
293 static void corenet_tb_init(void)
295 volatile ccsr_rcpm_t *rcpm =
296 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
297 volatile ccsr_pic_t *pic =
298 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
299 u32 whoami = in_be32(&pic->whoami);
301 /* Enable the timebase register for this core */
302 out_be32(&rcpm->ctbenrl, (1 << whoami));
306 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
307 void fsl_erratum_a007212_workaround(void)
309 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
311 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
312 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
313 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
314 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
315 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
316 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
317 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
318 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
319 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
323 * Even this workaround applies to selected version of SoCs, it is
324 * safe to apply to all versions, with the limitation of odd ratios.
325 * If RCW has disabled DDR PLL, we have to apply this workaround,
326 * otherwise DDR will not work.
328 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
329 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
330 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
331 /* check if RCW sets ratio to 0, required by this workaround */
332 if (ddr_pll_ratio != 0)
334 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
335 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
336 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
337 /* check if reserved bits have the desired ratio */
338 if (ddr_pll_ratio == 0) {
339 printf("Error: Unknown DDR PLL ratio!\n");
344 setbits_be32(plldadcr1, 0x02000001);
345 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
346 setbits_be32(plldadcr2, 0x02000001);
347 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
348 setbits_be32(plldadcr3, 0x02000001);
351 setbits_be32(dpdovrcr4, 0xe0000000);
352 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
353 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
354 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
355 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
356 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
360 clrbits_be32(plldadcr1, 0x02000001);
361 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
362 clrbits_be32(plldadcr2, 0x02000001);
363 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
364 clrbits_be32(plldadcr3, 0x02000001);
367 clrbits_be32(dpdovrcr4, 0xe0000000);
371 ulong cpu_init_f(void)
374 extern void m8560_cpm_reset (void);
375 #ifdef CONFIG_SYS_DCSRBAR_PHYS
376 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
378 #if defined(CONFIG_SECURE_BOOT)
379 struct law_entry law;
381 #ifdef CONFIG_MPC8548
382 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
383 uint svr = get_svr();
386 * CPU2 errata workaround: A core hang possible while executing
387 * a msync instruction and a snoopable transaction from an I/O
388 * master tagged to make quick forward progress is present.
389 * Fixed in silicon rev 2.1.
391 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
392 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
398 #if defined(CONFIG_SECURE_BOOT)
399 /* Disable the LAW created for NOR flash by the PBI commands */
400 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
402 disable_law(law.index);
404 #if defined(CONFIG_SYS_CPC_REINIT_F)
410 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
413 init_early_memctl_regs();
415 #if defined(CONFIG_CPM2)
419 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
420 /* Config QE ioports */
424 #if defined(CONFIG_FSL_DMA)
427 #ifdef CONFIG_FSL_CORENET
430 init_used_tlb_cams();
432 /* Invalidate the CPC before DDR gets enabled */
435 #ifdef CONFIG_SYS_DCSRBAR_PHYS
436 /* set DCSRCR so that DCSR space is 1G */
437 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
438 in_be32(&gur->dcsrcr);
441 #ifdef CONFIG_SYS_DCSRBAR_PHYS
442 #ifdef CONFIG_DEEP_SLEEP
443 /* disable the console if boot from deep sleep */
444 if (in_be32(&gur->scrtsr[0]) & (1 << 3))
445 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
448 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
449 fsl_erratum_a007212_workaround();
455 /* Implement a dummy function for those platforms w/o SERDES */
456 static void __fsl_serdes__init(void)
460 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
462 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
463 int enable_cluster_l2(void)
466 u32 cluster, svr = get_svr();
467 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
468 struct ccsr_cluster_l2 __iomem *l2cache;
470 /* only the L2 of first cluster should be enabled as expected on T4080,
471 * but there is no EOC in the first cluster as HW sake, so return here
472 * to skip enabling L2 cache of the 2nd cluster.
474 if (SVR_SOC_VER(svr) == SVR_T4080)
477 cluster = in_be32(&gur->tp_cluster[i].lower);
478 if (cluster & TP_CLUSTER_EOC)
481 /* The first cache has already been set up, so skip it */
484 /* Look through the remaining clusters, and set up their caches */
486 int j, cluster_valid = 0;
488 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
490 cluster = in_be32(&gur->tp_cluster[i].lower);
492 /* check that at least one core/accel is enabled in cluster */
493 for (j = 0; j < 4; j++) {
494 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
495 u32 type = in_be32(&gur->tp_ityp[idx]);
497 if (type & TP_ITYP_AV)
502 /* set stash ID to (cluster) * 2 + 32 + 1 */
503 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
505 printf("enable l2 for cluster %d %p\n", i, l2cache);
507 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
508 while ((in_be32(&l2cache->l2csr0)
509 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
511 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
514 } while (!(cluster & TP_CLUSTER_EOC));
521 * Initialize L2 as cache.
523 * The newer 8548, etc, parts have twice as much cache, but
524 * use the same bit-encoding as the older 8555, etc, parts.
529 __maybe_unused u32 svr = get_svr();
530 #ifdef CONFIG_SYS_LBC_LCRR
531 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
533 #ifdef CONFIG_L2_CACHE
534 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
535 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
536 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
538 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
539 extern int spin_table_compat;
542 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
543 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
545 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
546 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
548 * CPU22 and NMG_CPU_A011 share the same workaround.
549 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
550 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
551 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
552 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
553 * be disabled by hwconfig with syntax:
555 * fsl_cpu_a011:disable
557 extern int enable_cpu_a011_workaround;
558 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
559 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
561 char buffer[HWCONFIG_BUFFER_SIZE];
565 n = getenv_f("hwconfig", buffer, sizeof(buffer));
569 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
571 enable_cpu_a011_workaround = 0;
573 if (n >= HWCONFIG_BUFFER_SIZE) {
574 printf("fsl_cpu_a011 was not found. hwconfig variable "
575 "may be too long\n");
577 enable_cpu_a011_workaround =
578 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
579 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
582 if (enable_cpu_a011_workaround) {
584 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
588 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
590 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
591 * in write shadow mode. Checking DCWS before setting SPR 976.
593 if (mfspr(L1CSR2) & L1CSR2_DCWS)
594 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
597 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
598 spin = getenv("spin_table_compat");
599 if (spin && (*spin == 'n'))
600 spin_table_compat = 0;
602 spin_table_compat = 1;
607 #if defined(CONFIG_L2_CACHE)
608 volatile uint cache_ctl;
612 ver = SVR_SOC_VER(svr);
615 cache_ctl = l2cache->l2ctl;
617 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
618 if (cache_ctl & MPC85xx_L2CTL_L2E) {
619 /* Clear L2 SRAM memory-mapped base address */
620 out_be32(&l2cache->l2srbar0, 0x0);
621 out_be32(&l2cache->l2srbar1, 0x0);
623 /* set MBECCDIS=0, SBECCDIS=0 */
624 clrbits_be32(&l2cache->l2errdis,
625 (MPC85xx_L2ERRDIS_MBECC |
626 MPC85xx_L2ERRDIS_SBECC));
628 /* set L2E=0, L2SRAM=0 */
629 clrbits_be32(&l2cache->l2ctl,
631 MPC85xx_L2CTL_L2SRAM_ENTIRE));
635 l2siz_field = (cache_ctl >> 28) & 0x3;
637 switch (l2siz_field) {
639 printf(" unknown size (0x%08x)\n", cache_ctl);
643 if (ver == SVR_8540 || ver == SVR_8560 ||
644 ver == SVR_8541 || ver == SVR_8555) {
646 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
647 cache_ctl = 0xc4000000;
650 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
654 if (ver == SVR_8540 || ver == SVR_8560 ||
655 ver == SVR_8541 || ver == SVR_8555) {
657 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
658 cache_ctl = 0xc8000000;
661 /* set L2E=1, L2I=1, & L2SRAM=0 */
662 cache_ctl = 0xc0000000;
667 /* set L2E=1, L2I=1, & L2SRAM=0 */
668 cache_ctl = 0xc0000000;
672 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
673 puts("already enabled");
674 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
675 u32 l2srbar = l2cache->l2srbar0;
676 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
677 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
678 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
679 l2cache->l2srbar0 = l2srbar;
680 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
682 #endif /* CONFIG_SYS_INIT_L2_ADDR */
686 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
690 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
691 if (SVR_SOC_VER(svr) == SVR_P2040) {
696 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
698 /* invalidate the L2 cache */
699 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
700 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
703 #ifdef CONFIG_SYS_CACHE_STASHING
704 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
705 mtspr(SPRN_L2CSR1, (32 + 1));
708 /* enable the cache */
709 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
711 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
712 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
714 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
718 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
719 if (l2cache->l2csr0 & L2CSR0_L2E)
720 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
728 #if defined(CONFIG_RAMBOOT_PBL)
733 #ifndef CONFIG_SYS_FSL_NO_SERDES
734 /* needs to be in ram since code uses global static vars */
738 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
739 #define MCFGR_AXIPIPE 0x000000f0
740 if (IS_SVR_REV(svr, 1, 0))
741 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
744 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
745 if (IS_SVR_REV(svr, 1, 0)) {
747 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
749 for (i = 0; i < 12; i++) {
750 p += i + (i > 5 ? 11 : 0);
753 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
758 #ifdef CONFIG_SYS_SRIO
760 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
761 char *s = getenv("bootmaster");
763 if (!strcmp(s, "SRIO1")) {
765 srio_boot_master_release_slave(1);
767 if (!strcmp(s, "SRIO2")) {
769 srio_boot_master_release_slave(2);
775 #if defined(CONFIG_MP)
779 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
781 if (SVR_MAJ(svr) < 3) {
783 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
784 setbits_be32(p, 1 << (31 - 14));
789 #ifdef CONFIG_SYS_LBC_LCRR
791 * Modify the CLKDIV field of LCRR register to improve the writing
792 * speed for NOR flash.
794 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
795 __raw_readl(&lbc->lcrr);
797 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
802 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
804 struct ccsr_usb_phy __iomem *usb_phy1 =
805 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
806 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
807 if (has_erratum_a006261())
808 fsl_erratum_a006261_workaround(usb_phy1);
810 out_be32(&usb_phy1->usb_enable_override,
811 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
814 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
816 struct ccsr_usb_phy __iomem *usb_phy2 =
817 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
818 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
819 if (has_erratum_a006261())
820 fsl_erratum_a006261_workaround(usb_phy2);
822 out_be32(&usb_phy2->usb_enable_override,
823 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
827 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
828 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
829 * multi-bit ECC errors which has impact on performance, so software
830 * should disable all ECC reporting from USB1 and USB2.
832 if (IS_SVR_REV(get_svr(), 1, 0)) {
833 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
834 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
835 setbits_be32(&dcfg->ecccr1,
836 (DCSR_DCFG_ECC_DISABLE_USB1 |
837 DCSR_DCFG_ECC_DISABLE_USB2));
841 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
842 struct ccsr_usb_phy __iomem *usb_phy =
843 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
844 setbits_be32(&usb_phy->pllprg[1],
845 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
846 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
847 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
848 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
849 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
850 usb_single_source_clk_configure(usb_phy);
852 setbits_be32(&usb_phy->port1.ctrl,
853 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
854 setbits_be32(&usb_phy->port1.drvvbuscfg,
855 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
856 setbits_be32(&usb_phy->port1.pwrfltcfg,
857 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
858 setbits_be32(&usb_phy->port2.ctrl,
859 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
860 setbits_be32(&usb_phy->port2.drvvbuscfg,
861 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
862 setbits_be32(&usb_phy->port2.pwrfltcfg,
863 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
865 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
866 if (has_erratum_a006261())
867 fsl_erratum_a006261_workaround(usb_phy);
870 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
872 #ifdef CONFIG_FMAN_ENET
876 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
878 * For P1022/1013 Rev1.0 silicon, after power on SATA host
879 * controller is configured in legacy mode instead of the
880 * expected enterprise mode. Software needs to clear bit[28]
881 * of HControl register to change to enterprise mode from
882 * legacy mode. We assume that the controller is offline.
884 if (IS_SVR_REV(svr, 1, 0) &&
885 ((SVR_SOC_VER(svr) == SVR_P1022) ||
886 (SVR_SOC_VER(svr) == SVR_P1013))) {
889 /* first SATA controller */
890 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
891 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
893 /* second SATA controller */
894 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
895 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
899 init_used_tlb_cams();
904 void arch_preboot_os(void)
909 * We are changing interrupt offsets and are about to boot the OS so
910 * we need to make sure we disable all async interrupts. EE is already
911 * disabled by the time we get called.
914 msr &= ~(MSR_ME|MSR_CE);
918 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
919 int sata_initialize(void)
921 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
922 return __sata_initialize();
928 void cpu_secondary_init_r(void)
931 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
932 #elif defined CONFIG_QE
933 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */