mpc85xx/t104x: Enable L2 and CPC cache when resume
[platform/kernel/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c
1 /*
2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * (C) Copyright 2003 Motorola Inc.
5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
6  *
7  * (C) Copyright 2000
8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 #include <common.h>
14 #include <watchdog.h>
15 #include <asm/processor.h>
16 #include <ioports.h>
17 #include <sata.h>
18 #include <fm_eth.h>
19 #include <asm/io.h>
20 #include <asm/cache.h>
21 #include <asm/mmu.h>
22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h>
26 #include <fsl_usb.h>
27 #include <hwconfig.h>
28 #include <linux/compiler.h>
29 #include "mp.h"
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
31 #include <nand.h>
32 #include <errno.h>
33 #endif
34
35 #include "../../../../drivers/block/fsl_sata.h"
36 #ifdef CONFIG_U_QE
37 #include "../../../../drivers/qe/qe.h"
38 #endif
39
40 DECLARE_GLOBAL_DATA_PTR;
41
42 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
43 /*
44  * For deriving usb clock from 100MHz sysclk, reference divisor is set
45  * to a value of 5, which gives an intermediate value 20(100/5). The
46  * multiplication factor integer is set to 24, which when multiplied to
47  * above intermediate value provides clock for usb ip.
48  */
49 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
50 {
51         sys_info_t sysinfo;
52
53         get_sys_info(&sysinfo);
54         if (sysinfo.diff_sysclk == 1) {
55                 clrbits_be32(&usb_phy->pllprg[1],
56                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
57                 setbits_be32(&usb_phy->pllprg[1],
58                              CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
59                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
60                              CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
61                 }
62 }
63 #endif
64
65 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
66 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
67 {
68 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
69         u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
70
71         /* Increase Disconnect Threshold by 50mV */
72         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
73                                                 INC_DCNT_THRESHOLD_50MV;
74         /* Enable programming of USB High speed Disconnect threshold */
75         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
76         out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
77
78         xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
79         /* Increase Disconnect Threshold by 50mV */
80         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
81                                                 INC_DCNT_THRESHOLD_50MV;
82         /* Enable programming of USB High speed Disconnect threshold */
83         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
84         out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
85 #else
86
87         u32 temp = 0;
88         u32 status = in_be32(&usb_phy->status1);
89
90         u32 squelch_prog_rd_0_2 =
91                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
92                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
93
94         u32 squelch_prog_rd_3_5 =
95                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
96                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
97
98         setbits_be32(&usb_phy->config1,
99                      CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
100         setbits_be32(&usb_phy->config2,
101                      CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
102
103         temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
104         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
105
106         temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
107         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
108 #endif
109 }
110 #endif
111
112
113 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
114 extern qe_iop_conf_t qe_iop_conf_tab[];
115 extern void qe_config_iopin(u8 port, u8 pin, int dir,
116                                 int open_drain, int assign);
117 extern void qe_init(uint qe_base);
118 extern void qe_reset(void);
119
120 static void config_qe_ioports(void)
121 {
122         u8      port, pin;
123         int     dir, open_drain, assign;
124         int     i;
125
126         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
127                 port            = qe_iop_conf_tab[i].port;
128                 pin             = qe_iop_conf_tab[i].pin;
129                 dir             = qe_iop_conf_tab[i].dir;
130                 open_drain      = qe_iop_conf_tab[i].open_drain;
131                 assign          = qe_iop_conf_tab[i].assign;
132                 qe_config_iopin(port, pin, dir, open_drain, assign);
133         }
134 }
135 #endif
136
137 #ifdef CONFIG_CPM2
138 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
139 {
140         int portnum;
141
142         for (portnum = 0; portnum < 4; portnum++) {
143                 uint pmsk = 0,
144                      ppar = 0,
145                      psor = 0,
146                      pdir = 0,
147                      podr = 0,
148                      pdat = 0;
149                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
150                 iop_conf_t *eiopc = iopc + 32;
151                 uint msk = 1;
152
153                 /*
154                  * NOTE:
155                  * index 0 refers to pin 31,
156                  * index 31 refers to pin 0
157                  */
158                 while (iopc < eiopc) {
159                         if (iopc->conf) {
160                                 pmsk |= msk;
161                                 if (iopc->ppar)
162                                         ppar |= msk;
163                                 if (iopc->psor)
164                                         psor |= msk;
165                                 if (iopc->pdir)
166                                         pdir |= msk;
167                                 if (iopc->podr)
168                                         podr |= msk;
169                                 if (iopc->pdat)
170                                         pdat |= msk;
171                         }
172
173                         msk <<= 1;
174                         iopc++;
175                 }
176
177                 if (pmsk != 0) {
178                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
179                         uint tpmsk = ~pmsk;
180
181                         /*
182                          * the (somewhat confused) paragraph at the
183                          * bottom of page 35-5 warns that there might
184                          * be "unknown behaviour" when programming
185                          * PSORx and PDIRx, if PPARx = 1, so I
186                          * decided this meant I had to disable the
187                          * dedicated function first, and enable it
188                          * last.
189                          */
190                         iop->ppar &= tpmsk;
191                         iop->psor = (iop->psor & tpmsk) | psor;
192                         iop->podr = (iop->podr & tpmsk) | podr;
193                         iop->pdat = (iop->pdat & tpmsk) | pdat;
194                         iop->pdir = (iop->pdir & tpmsk) | pdir;
195                         iop->ppar |= ppar;
196                 }
197         }
198 }
199 #endif
200
201 #ifdef CONFIG_SYS_FSL_CPC
202 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
203 void disable_cpc_sram(void)
204 {
205         int i;
206
207         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
208
209         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
210                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
211                         /* find and disable LAW of SRAM */
212                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
213
214                         if (law.index == -1) {
215                                 printf("\nFatal error happened\n");
216                                 return;
217                         }
218                         disable_law(law.index);
219
220                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
221                         out_be32(&cpc->cpccsr0, 0);
222                         out_be32(&cpc->cpcsrcr0, 0);
223                 }
224         }
225 }
226 #endif
227
228 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
229 #ifdef CONFIG_POST
230 #error POST memory test cannot be enabled with TDM
231 #endif
232 static void enable_tdm_law(void)
233 {
234         int ret;
235         char buffer[HWCONFIG_BUFFER_SIZE] = {0};
236         int tdm_hwconfig_enabled = 0;
237
238         /*
239          * Extract hwconfig from environment since environment
240          * is not setup properly yet. Search for tdm entry in
241          * hwconfig.
242          */
243         ret = getenv_f("hwconfig", buffer, sizeof(buffer));
244         if (ret > 0) {
245                 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
246                 /* If tdm is defined in hwconfig, set law for tdm workaround */
247                 if (tdm_hwconfig_enabled)
248                         set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
249                                      LAW_TRGT_IF_CCSR);
250         }
251 }
252 #endif
253
254 void enable_cpc(void)
255 {
256         int i;
257         u32 size = 0;
258
259         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
260
261         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
262                 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
263                 size += CPC_CFG0_SZ_K(cpccfg0);
264
265 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
266                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
267 #endif
268 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
269                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
270 #endif
271 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
272                 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
273 #endif
274 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
275                 if (has_erratum_a006379()) {
276                         setbits_be32(&cpc->cpchdbcr0,
277                                      CPC_HDBCR0_SPLRU_LEVEL_EN);
278                 }
279 #endif
280
281                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
282                 /* Read back to sync write */
283                 in_be32(&cpc->cpccsr0);
284
285         }
286
287         puts("Corenet Platform Cache: ");
288         print_size(size * 1024, " enabled\n");
289 }
290
291 static void invalidate_cpc(void)
292 {
293         int i;
294         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
295
296         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
297                 /* skip CPC when it used as all SRAM */
298                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
299                         continue;
300                 /* Flash invalidate the CPC and clear all the locks */
301                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
302                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
303                         ;
304         }
305 }
306 #else
307 #define enable_cpc()
308 #define invalidate_cpc()
309 #define disable_cpc_sram()
310 #endif /* CONFIG_SYS_FSL_CPC */
311
312 /*
313  * Breathe some life into the CPU...
314  *
315  * Set up the memory map
316  * initialize a bunch of registers
317  */
318
319 #ifdef CONFIG_FSL_CORENET
320 static void corenet_tb_init(void)
321 {
322         volatile ccsr_rcpm_t *rcpm =
323                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
324         volatile ccsr_pic_t *pic =
325                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
326         u32 whoami = in_be32(&pic->whoami);
327
328         /* Enable the timebase register for this core */
329         out_be32(&rcpm->ctbenrl, (1 << whoami));
330 }
331 #endif
332
333 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
334 void fsl_erratum_a007212_workaround(void)
335 {
336         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
337         u32 ddr_pll_ratio;
338         u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
339         u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
340         u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
341 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
342         u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
343         u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
344 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
345         u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
346         u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
347 #endif
348 #endif
349         /*
350          * Even this workaround applies to selected version of SoCs, it is
351          * safe to apply to all versions, with the limitation of odd ratios.
352          * If RCW has disabled DDR PLL, we have to apply this workaround,
353          * otherwise DDR will not work.
354          */
355         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
356                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
357                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
358         /* check if RCW sets ratio to 0, required by this workaround */
359         if (ddr_pll_ratio != 0)
360                 return;
361         ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
362                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
363                 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
364         /* check if reserved bits have the desired ratio */
365         if (ddr_pll_ratio == 0) {
366                 printf("Error: Unknown DDR PLL ratio!\n");
367                 return;
368         }
369         ddr_pll_ratio >>= 1;
370
371         setbits_be32(plldadcr1, 0x02000001);
372 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
373         setbits_be32(plldadcr2, 0x02000001);
374 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
375         setbits_be32(plldadcr3, 0x02000001);
376 #endif
377 #endif
378         setbits_be32(dpdovrcr4, 0xe0000000);
379         out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
380 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
381         out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
382 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
383         out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
384 #endif
385 #endif
386         udelay(100);
387         clrbits_be32(plldadcr1, 0x02000001);
388 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
389         clrbits_be32(plldadcr2, 0x02000001);
390 #if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
391         clrbits_be32(plldadcr3, 0x02000001);
392 #endif
393 #endif
394         clrbits_be32(dpdovrcr4, 0xe0000000);
395 }
396 #endif
397
398 ulong cpu_init_f(void)
399 {
400         ulong flag = 0;
401         extern void m8560_cpm_reset (void);
402 #ifdef CONFIG_SYS_DCSRBAR_PHYS
403         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
404 #endif
405 #if defined(CONFIG_SECURE_BOOT)
406         struct law_entry law;
407 #endif
408 #ifdef CONFIG_MPC8548
409         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
410         uint svr = get_svr();
411
412         /*
413          * CPU2 errata workaround: A core hang possible while executing
414          * a msync instruction and a snoopable transaction from an I/O
415          * master tagged to make quick forward progress is present.
416          * Fixed in silicon rev 2.1.
417          */
418         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
419                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
420 #endif
421
422         disable_tlb(14);
423         disable_tlb(15);
424
425 #if defined(CONFIG_SECURE_BOOT)
426         /* Disable the LAW created for NOR flash by the PBI commands */
427         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
428         if (law.index != -1)
429                 disable_law(law.index);
430
431 #if defined(CONFIG_SYS_CPC_REINIT_F)
432         disable_cpc_sram();
433 #endif
434 #endif
435
436 #ifdef CONFIG_CPM2
437         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
438 #endif
439
440        init_early_memctl_regs();
441
442 #if defined(CONFIG_CPM2)
443         m8560_cpm_reset();
444 #endif
445
446 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
447         /* Config QE ioports */
448         config_qe_ioports();
449 #endif
450
451 #if defined(CONFIG_FSL_DMA)
452         dma_init();
453 #endif
454 #ifdef CONFIG_FSL_CORENET
455         corenet_tb_init();
456 #endif
457         init_used_tlb_cams();
458
459         /* Invalidate the CPC before DDR gets enabled */
460         invalidate_cpc();
461
462  #ifdef CONFIG_SYS_DCSRBAR_PHYS
463         /* set DCSRCR so that DCSR space is 1G */
464         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
465         in_be32(&gur->dcsrcr);
466 #endif
467
468 #ifdef CONFIG_SYS_DCSRBAR_PHYS
469 #ifdef CONFIG_DEEP_SLEEP
470         /* disable the console if boot from deep sleep */
471         if (in_be32(&gur->scrtsr[0]) & (1 << 3))
472                 flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
473 #endif
474 #endif
475 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
476         fsl_erratum_a007212_workaround();
477 #endif
478
479         return flag;
480 }
481
482 /* Implement a dummy function for those platforms w/o SERDES */
483 static void __fsl_serdes__init(void)
484 {
485         return ;
486 }
487 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
488
489 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
490 int enable_cluster_l2(void)
491 {
492         int i = 0;
493         u32 cluster, svr = get_svr();
494         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
495         struct ccsr_cluster_l2 __iomem *l2cache;
496
497         /* only the L2 of first cluster should be enabled as expected on T4080,
498          * but there is no EOC in the first cluster as HW sake, so return here
499          * to skip enabling L2 cache of the 2nd cluster.
500          */
501         if (SVR_SOC_VER(svr) == SVR_T4080)
502                 return 0;
503
504         cluster = in_be32(&gur->tp_cluster[i].lower);
505         if (cluster & TP_CLUSTER_EOC)
506                 return 0;
507
508         /* The first cache has already been set up, so skip it */
509         i++;
510
511         /* Look through the remaining clusters, and set up their caches */
512         do {
513                 int j, cluster_valid = 0;
514
515                 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
516
517                 cluster = in_be32(&gur->tp_cluster[i].lower);
518
519                 /* check that at least one core/accel is enabled in cluster */
520                 for (j = 0; j < 4; j++) {
521                         u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
522                         u32 type = in_be32(&gur->tp_ityp[idx]);
523
524                         if ((type & TP_ITYP_AV) &&
525                             TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
526                                 cluster_valid = 1;
527                 }
528
529                 if (cluster_valid) {
530                         /* set stash ID to (cluster) * 2 + 32 + 1 */
531                         clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
532
533                         printf("enable l2 for cluster %d %p\n", i, l2cache);
534
535                         out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
536                         while ((in_be32(&l2cache->l2csr0)
537                                 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
538                                         ;
539                         out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
540                 }
541                 i++;
542         } while (!(cluster & TP_CLUSTER_EOC));
543
544         return 0;
545 }
546 #endif
547
548 /*
549  * Initialize L2 as cache.
550  */
551 int l2cache_init(void)
552 {
553         __maybe_unused u32 svr = get_svr();
554 #ifdef CONFIG_L2_CACHE
555         ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
556 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
557         struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
558 #endif
559
560         puts ("L2:    ");
561
562 #if defined(CONFIG_L2_CACHE)
563         volatile uint cache_ctl;
564         uint ver;
565         u32 l2siz_field;
566
567         ver = SVR_SOC_VER(svr);
568
569         asm("msync;isync");
570         cache_ctl = l2cache->l2ctl;
571
572 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
573         if (cache_ctl & MPC85xx_L2CTL_L2E) {
574                 /* Clear L2 SRAM memory-mapped base address */
575                 out_be32(&l2cache->l2srbar0, 0x0);
576                 out_be32(&l2cache->l2srbar1, 0x0);
577
578                 /* set MBECCDIS=0, SBECCDIS=0 */
579                 clrbits_be32(&l2cache->l2errdis,
580                                 (MPC85xx_L2ERRDIS_MBECC |
581                                  MPC85xx_L2ERRDIS_SBECC));
582
583                 /* set L2E=0, L2SRAM=0 */
584                 clrbits_be32(&l2cache->l2ctl,
585                                 (MPC85xx_L2CTL_L2E |
586                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
587         }
588 #endif
589
590         l2siz_field = (cache_ctl >> 28) & 0x3;
591
592         switch (l2siz_field) {
593         case 0x0:
594                 printf(" unknown size (0x%08x)\n", cache_ctl);
595                 return -1;
596                 break;
597         case 0x1:
598                 if (ver == SVR_8540 || ver == SVR_8560   ||
599                     ver == SVR_8541 || ver == SVR_8555) {
600                         puts("128 KiB ");
601                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
602                         cache_ctl = 0xc4000000;
603                 } else {
604                         puts("256 KiB ");
605                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
606                 }
607                 break;
608         case 0x2:
609                 if (ver == SVR_8540 || ver == SVR_8560   ||
610                     ver == SVR_8541 || ver == SVR_8555) {
611                         puts("256 KiB ");
612                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
613                         cache_ctl = 0xc8000000;
614                 } else {
615                         puts("512 KiB ");
616                         /* set L2E=1, L2I=1, & L2SRAM=0 */
617                         cache_ctl = 0xc0000000;
618                 }
619                 break;
620         case 0x3:
621                 puts("1024 KiB ");
622                 /* set L2E=1, L2I=1, & L2SRAM=0 */
623                 cache_ctl = 0xc0000000;
624                 break;
625         }
626
627         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
628                 puts("already enabled");
629 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
630                 u32 l2srbar = l2cache->l2srbar0;
631                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
632                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
633                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
634                         l2cache->l2srbar0 = l2srbar;
635                         printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
636                 }
637 #endif /* CONFIG_SYS_INIT_L2_ADDR */
638                 puts("\n");
639         } else {
640                 asm("msync;isync");
641                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
642                 asm("msync;isync");
643                 puts("enabled\n");
644         }
645 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
646         if (SVR_SOC_VER(svr) == SVR_P2040) {
647                 puts("N/A\n");
648                 goto skip_l2;
649         }
650
651         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
652
653         /* invalidate the L2 cache */
654         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
655         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
656                 ;
657
658 #ifdef CONFIG_SYS_CACHE_STASHING
659         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
660         mtspr(SPRN_L2CSR1, (32 + 1));
661 #endif
662
663         /* enable the cache */
664         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
665
666         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
667                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
668                         ;
669                 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
670         }
671
672 skip_l2:
673 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
674         if (l2cache->l2csr0 & L2CSR0_L2E)
675                 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
676                            " enabled\n");
677
678         enable_cluster_l2();
679 #else
680         puts("disabled\n");
681 #endif
682
683         return 0;
684 }
685
686 /*
687  *
688  * The newer 8548, etc, parts have twice as much cache, but
689  * use the same bit-encoding as the older 8555, etc, parts.
690  *
691  */
692 int cpu_init_r(void)
693 {
694         __maybe_unused u32 svr = get_svr();
695 #ifdef CONFIG_SYS_LBC_LCRR
696         fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
697 #endif
698 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
699         extern int spin_table_compat;
700         const char *spin;
701 #endif
702 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
703         ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
704 #endif
705 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
706         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
707         /*
708          * CPU22 and NMG_CPU_A011 share the same workaround.
709          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
710          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
711          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
712          * fixed in 2.0. NMG_CPU_A011 is activated by default and can
713          * be disabled by hwconfig with syntax:
714          *
715          * fsl_cpu_a011:disable
716          */
717         extern int enable_cpu_a011_workaround;
718 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
719         enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
720 #else
721         char buffer[HWCONFIG_BUFFER_SIZE];
722         char *buf = NULL;
723         int n, res;
724
725         n = getenv_f("hwconfig", buffer, sizeof(buffer));
726         if (n > 0)
727                 buf = buffer;
728
729         res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
730         if (res > 0) {
731                 enable_cpu_a011_workaround = 0;
732         } else {
733                 if (n >= HWCONFIG_BUFFER_SIZE) {
734                         printf("fsl_cpu_a011 was not found. hwconfig variable "
735                                 "may be too long\n");
736                 }
737                 enable_cpu_a011_workaround =
738                         (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
739                         (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
740         }
741 #endif
742         if (enable_cpu_a011_workaround) {
743                 flush_dcache();
744                 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
745                 sync();
746         }
747 #endif
748 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
749         /*
750          * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
751          * in write shadow mode. Checking DCWS before setting SPR 976.
752          */
753         if (mfspr(L1CSR2) & L1CSR2_DCWS)
754                 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
755 #endif
756
757 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
758         spin = getenv("spin_table_compat");
759         if (spin && (*spin == 'n'))
760                 spin_table_compat = 0;
761         else
762                 spin_table_compat = 1;
763 #endif
764
765         l2cache_init();
766 #if defined(CONFIG_RAMBOOT_PBL)
767         disable_cpc_sram();
768 #endif
769         enable_cpc();
770 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
771         enable_tdm_law();
772 #endif
773
774 #ifndef CONFIG_SYS_FSL_NO_SERDES
775         /* needs to be in ram since code uses global static vars */
776         fsl_serdes_init();
777 #endif
778
779 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
780 #define MCFGR_AXIPIPE 0x000000f0
781         if (IS_SVR_REV(svr, 1, 0))
782                 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
783 #endif
784
785 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
786         if (IS_SVR_REV(svr, 1, 0)) {
787                 int i;
788                 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
789
790                 for (i = 0; i < 12; i++) {
791                         p += i + (i > 5 ? 11 : 0);
792                         out_be32(p, 0x2);
793                 }
794                 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
795                 out_be32(p, 0x34);
796         }
797 #endif
798
799 #ifdef CONFIG_SYS_SRIO
800         srio_init();
801 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
802         char *s = getenv("bootmaster");
803         if (s) {
804                 if (!strcmp(s, "SRIO1")) {
805                         srio_boot_master(1);
806                         srio_boot_master_release_slave(1);
807                 }
808                 if (!strcmp(s, "SRIO2")) {
809                         srio_boot_master(2);
810                         srio_boot_master_release_slave(2);
811                 }
812         }
813 #endif
814 #endif
815
816 #if defined(CONFIG_MP)
817         setup_mp();
818 #endif
819
820 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
821         {
822                 if (SVR_MAJ(svr) < 3) {
823                         void *p;
824                         p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
825                         setbits_be32(p, 1 << (31 - 14));
826                 }
827         }
828 #endif
829
830 #ifdef CONFIG_SYS_LBC_LCRR
831         /*
832          * Modify the CLKDIV field of LCRR register to improve the writing
833          * speed for NOR flash.
834          */
835         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
836         __raw_readl(&lbc->lcrr);
837         isync();
838 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
839         udelay(100);
840 #endif
841 #endif
842
843 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
844         {
845                 struct ccsr_usb_phy __iomem *usb_phy1 =
846                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
847 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
848                 if (has_erratum_a006261())
849                         fsl_erratum_a006261_workaround(usb_phy1);
850 #endif
851                 out_be32(&usb_phy1->usb_enable_override,
852                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
853         }
854 #endif
855 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
856         {
857                 struct ccsr_usb_phy __iomem *usb_phy2 =
858                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
859 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
860                 if (has_erratum_a006261())
861                         fsl_erratum_a006261_workaround(usb_phy2);
862 #endif
863                 out_be32(&usb_phy2->usb_enable_override,
864                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
865         }
866 #endif
867
868 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
869         /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
870          * multi-bit ECC errors which has impact on performance, so software
871          * should disable all ECC reporting from USB1 and USB2.
872          */
873         if (IS_SVR_REV(get_svr(), 1, 0)) {
874                 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
875                         (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
876                 setbits_be32(&dcfg->ecccr1,
877                                 (DCSR_DCFG_ECC_DISABLE_USB1 |
878                                  DCSR_DCFG_ECC_DISABLE_USB2));
879         }
880 #endif
881
882 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
883                 struct ccsr_usb_phy __iomem *usb_phy =
884                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
885                 setbits_be32(&usb_phy->pllprg[1],
886                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
887                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
888                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
889                              CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
890 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
891                 usb_single_source_clk_configure(usb_phy);
892 #endif
893                 setbits_be32(&usb_phy->port1.ctrl,
894                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
895                 setbits_be32(&usb_phy->port1.drvvbuscfg,
896                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
897                 setbits_be32(&usb_phy->port1.pwrfltcfg,
898                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
899                 setbits_be32(&usb_phy->port2.ctrl,
900                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
901                 setbits_be32(&usb_phy->port2.drvvbuscfg,
902                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
903                 setbits_be32(&usb_phy->port2.pwrfltcfg,
904                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
905
906 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
907                 if (has_erratum_a006261())
908                         fsl_erratum_a006261_workaround(usb_phy);
909 #endif
910
911 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
912
913 #ifdef CONFIG_FMAN_ENET
914         fman_enet_init();
915 #endif
916
917 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
918         /*
919          * For P1022/1013 Rev1.0 silicon, after power on SATA host
920          * controller is configured in legacy mode instead of the
921          * expected enterprise mode. Software needs to clear bit[28]
922          * of HControl register to change to enterprise mode from
923          * legacy mode.  We assume that the controller is offline.
924          */
925         if (IS_SVR_REV(svr, 1, 0) &&
926             ((SVR_SOC_VER(svr) == SVR_P1022) ||
927              (SVR_SOC_VER(svr) == SVR_P1013))) {
928                 fsl_sata_reg_t *reg;
929
930                 /* first SATA controller */
931                 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
932                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
933
934                 /* second SATA controller */
935                 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
936                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
937         }
938 #endif
939
940         init_used_tlb_cams();
941
942         return 0;
943 }
944
945 void arch_preboot_os(void)
946 {
947         u32 msr;
948
949         /*
950          * We are changing interrupt offsets and are about to boot the OS so
951          * we need to make sure we disable all async interrupts. EE is already
952          * disabled by the time we get called.
953          */
954         msr = mfmsr();
955         msr &= ~(MSR_ME|MSR_CE);
956         mtmsr(msr);
957 }
958
959 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
960 int sata_initialize(void)
961 {
962         if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
963                 return __sata_initialize();
964
965         return 1;
966 }
967 #endif
968
969 void cpu_secondary_init_r(void)
970 {
971 #ifdef CONFIG_U_QE
972         uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
973 #elif defined CONFIG_QE
974         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
975 #endif
976
977 #ifdef CONFIG_QE
978         qe_init(qe_base);
979         qe_reset();
980 #endif
981 }