arch/powerpc/cpu/mpc85xx/cpu_init.c

   1 /*
   2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <watchdog.h>
  15 #include <asm/processor.h>
  16 #include <ioports.h>
  17 #include <sata.h>
  18 #include <fm_eth.h>
  19 #include <asm/io.h>
  20 #include <asm/cache.h>
  21 #include <asm/mmu.h>
  22 #include <asm/fsl_errata.h>
  23 #include <asm/fsl_law.h>
  24 #include <asm/fsl_serdes.h>
  25 #include <asm/fsl_srio.h>
  26 #include <fsl_usb.h>
  27 #include <hwconfig.h>
  28 #include <linux/compiler.h>
  29 #include "mp.h"
  30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  31 #include <nand.h>
  32 #include <errno.h>
  33 #endif
  34
  35 #include "../../../../drivers/block/fsl_sata.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  40 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  41 {
  42 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  43         u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  44
  45         /* Increase Disconnect Threshold by 50mV */
  46         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  47                                                 INC_DCNT_THRESHOLD_50MV;
  48         /* Enable programming of USB High speed Disconnect threshold */
  49         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  50         out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  51
  52         xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  53         /* Increase Disconnect Threshold by 50mV */
  54         xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  55                                                 INC_DCNT_THRESHOLD_50MV;
  56         /* Enable programming of USB High speed Disconnect threshold */
  57         xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  58         out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  59 #else
  60
  61         u32 temp = 0;
  62         u32 status = in_be32(&usb_phy->status1);
  63
  64         u32 squelch_prog_rd_0_2 =
  65                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
  66                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  67
  68         u32 squelch_prog_rd_3_5 =
  69                 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
  70                         & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  71
  72         setbits_be32(&usb_phy->config1,
  73                      CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
  74         setbits_be32(&usb_phy->config2,
  75                      CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
  76
  77         temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
  78         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  79
  80         temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
  81         out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  82 #endif
  83 }
  84 #endif
  85
  86
  87 #ifdef CONFIG_QE
  88 extern qe_iop_conf_t qe_iop_conf_tab[];
  89 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  90                                 int open_drain, int assign);
  91 extern void qe_init(uint qe_base);
  92 extern void qe_reset(void);
  93
  94 static void config_qe_ioports(void)
  95 {
  96         u8      port, pin;
  97         int     dir, open_drain, assign;
  98         int     i;
  99
 100         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
 101                 port            = qe_iop_conf_tab[i].port;
 102                 pin             = qe_iop_conf_tab[i].pin;
 103                 dir             = qe_iop_conf_tab[i].dir;
 104                 open_drain      = qe_iop_conf_tab[i].open_drain;
 105                 assign          = qe_iop_conf_tab[i].assign;
 106                 qe_config_iopin(port, pin, dir, open_drain, assign);
 107         }
 108 }
 109 #endif
 110
 111 #ifdef CONFIG_CPM2
 112 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 113 {
 114         int portnum;
 115
 116         for (portnum = 0; portnum < 4; portnum++) {
 117                 uint pmsk = 0,
 118                      ppar = 0,
 119                      psor = 0,
 120                      pdir = 0,
 121                      podr = 0,
 122                      pdat = 0;
 123                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
 124                 iop_conf_t *eiopc = iopc + 32;
 125                 uint msk = 1;
 126
 127                 /*
 128                  * NOTE:
 129                  * index 0 refers to pin 31,
 130                  * index 31 refers to pin 0
 131                  */
 132                 while (iopc < eiopc) {
 133                         if (iopc->conf) {
 134                                 pmsk |= msk;
 135                                 if (iopc->ppar)
 136                                         ppar |= msk;
 137                                 if (iopc->psor)
 138                                         psor |= msk;
 139                                 if (iopc->pdir)
 140                                         pdir |= msk;
 141                                 if (iopc->podr)
 142                                         podr |= msk;
 143                                 if (iopc->pdat)
 144                                         pdat |= msk;
 145                         }
 146
 147                         msk <<= 1;
 148                         iopc++;
 149                 }
 150
 151                 if (pmsk != 0) {
 152                         volatile ioport_t *iop = ioport_addr (cpm, portnum);
 153                         uint tpmsk = ~pmsk;
 154
 155                         /*
 156                          * the (somewhat confused) paragraph at the
 157                          * bottom of page 35-5 warns that there might
 158                          * be "unknown behaviour" when programming
 159                          * PSORx and PDIRx, if PPARx = 1, so I
 160                          * decided this meant I had to disable the
 161                          * dedicated function first, and enable it
 162                          * last.
 163                          */
 164                         iop->ppar &= tpmsk;
 165                         iop->psor = (iop->psor & tpmsk) | psor;
 166                         iop->podr = (iop->podr & tpmsk) | podr;
 167                         iop->pdat = (iop->pdat & tpmsk) | pdat;
 168                         iop->pdir = (iop->pdir & tpmsk) | pdir;
 169                         iop->ppar |= ppar;
 170                 }
 171         }
 172 }
 173 #endif
 174
 175 #ifdef CONFIG_SYS_FSL_CPC
 176 static void enable_cpc(void)
 177 {
 178         int i;
 179         u32 size = 0;
 180
 181         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 182
 183         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 184                 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
 185                 size += CPC_CFG0_SZ_K(cpccfg0);
 186 #ifdef CONFIG_RAMBOOT_PBL
 187                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 188                         /* find and disable LAW of SRAM */
 189                         struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 190
 191                         if (law.index == -1) {
 192                                 printf("\nFatal error happened\n");
 193                                 return;
 194                         }
 195                         disable_law(law.index);
 196
 197                         clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 198                         out_be32(&cpc->cpccsr0, 0);
 199                         out_be32(&cpc->cpcsrcr0, 0);
 200                 }
 201 #endif
 202
 203 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 204                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 205 #endif
 206 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 207                 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 208 #endif
 209 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 210                 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 211 #endif
 212 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
 213                 if (has_erratum_a006379()) {
 214                         setbits_be32(&cpc->cpchdbcr0,
 215                                      CPC_HDBCR0_SPLRU_LEVEL_EN);
 216                 }
 217 #endif
 218
 219                 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 220                 /* Read back to sync write */
 221                 in_be32(&cpc->cpccsr0);
 222
 223         }
 224
 225         puts("Corenet Platform Cache: ");
 226         print_size(size * 1024, " enabled\n");
 227 }
 228
 229 static void invalidate_cpc(void)
 230 {
 231         int i;
 232         cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 233
 234         for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 235                 /* skip CPC when it used as all SRAM */
 236                 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 237                         continue;
 238                 /* Flash invalidate the CPC and clear all the locks */
 239                 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 240                 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 241                         ;
 242         }
 243 }
 244 #else
 245 #define enable_cpc()
 246 #define invalidate_cpc()
 247 #endif /* CONFIG_SYS_FSL_CPC */
 248
 249 /*
 250  * Breathe some life into the CPU...
 251  *
 252  * Set up the memory map
 253  * initialize a bunch of registers
 254  */
 255
 256 #ifdef CONFIG_FSL_CORENET
 257 static void corenet_tb_init(void)
 258 {
 259         volatile ccsr_rcpm_t *rcpm =
 260                 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 261         volatile ccsr_pic_t *pic =
 262                 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 263         u32 whoami = in_be32(&pic->whoami);
 264
 265         /* Enable the timebase register for this core */
 266         out_be32(&rcpm->ctbenrl, (1 << whoami));
 267 }
 268 #endif
 269
 270 void cpu_init_f (void)
 271 {
 272         extern void m8560_cpm_reset (void);
 273 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 274         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 275 #endif
 276 #if defined(CONFIG_SECURE_BOOT)
 277         struct law_entry law;
 278 #endif
 279 #ifdef CONFIG_MPC8548
 280         ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 281         uint svr = get_svr();
 282
 283         /*
 284          * CPU2 errata workaround: A core hang possible while executing
 285          * a msync instruction and a snoopable transaction from an I/O
 286          * master tagged to make quick forward progress is present.
 287          * Fixed in silicon rev 2.1.
 288          */
 289         if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 290                 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 291 #endif
 292
 293         disable_tlb(14);
 294         disable_tlb(15);
 295
 296 #if defined(CONFIG_SECURE_BOOT)
 297         /* Disable the LAW created for NOR flash by the PBI commands */
 298         law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 299         if (law.index != -1)
 300                 disable_law(law.index);
 301 #endif
 302
 303 #ifdef CONFIG_CPM2
 304         config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 305 #endif
 306
 307        init_early_memctl_regs();
 308
 309 #if defined(CONFIG_CPM2)
 310         m8560_cpm_reset();
 311 #endif
 312 #ifdef CONFIG_QE
 313         /* Config QE ioports */
 314         config_qe_ioports();
 315 #endif
 316 #if defined(CONFIG_FSL_DMA)
 317         dma_init();
 318 #endif
 319 #ifdef CONFIG_FSL_CORENET
 320         corenet_tb_init();
 321 #endif
 322         init_used_tlb_cams();
 323
 324         /* Invalidate the CPC before DDR gets enabled */
 325         invalidate_cpc();
 326
 327  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 328         /* set DCSRCR so that DCSR space is 1G */
 329         setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 330         in_be32(&gur->dcsrcr);
 331 #endif
 332
 333 }
 334
 335 /* Implement a dummy function for those platforms w/o SERDES */
 336 static void __fsl_serdes__init(void)
 337 {
 338         return ;
 339 }
 340 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 341
 342 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 343 int enable_cluster_l2(void)
 344 {
 345         int i = 0;
 346         u32 cluster;
 347         ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 348         struct ccsr_cluster_l2 __iomem *l2cache;
 349
 350         cluster = in_be32(&gur->tp_cluster[i].lower);
 351         if (cluster & TP_CLUSTER_EOC)
 352                 return 0;
 353
 354         /* The first cache has already been set up, so skip it */
 355         i++;
 356
 357         /* Look through the remaining clusters, and set up their caches */
 358         do {
 359                 int j, cluster_valid = 0;
 360
 361                 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 362
 363                 cluster = in_be32(&gur->tp_cluster[i].lower);
 364
 365                 /* check that at least one core/accel is enabled in cluster */
 366                 for (j = 0; j < 4; j++) {
 367                         u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
 368                         u32 type = in_be32(&gur->tp_ityp[idx]);
 369
 370                         if (type & TP_ITYP_AV)
 371                                 cluster_valid = 1;
 372                 }
 373
 374                 if (cluster_valid) {
 375                         /* set stash ID to (cluster) * 2 + 32 + 1 */
 376                         clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 377
 378                         printf("enable l2 for cluster %d %p\n", i, l2cache);
 379
 380                         out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
 381                         while ((in_be32(&l2cache->l2csr0)
 382                                 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 383                                         ;
 384                         out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
 385                 }
 386                 i++;
 387         } while (!(cluster & TP_CLUSTER_EOC));
 388
 389         return 0;
 390 }
 391 #endif
 392
 393 /*
 394  * Initialize L2 as cache.
 395  *
 396  * The newer 8548, etc, parts have twice as much cache, but
 397  * use the same bit-encoding as the older 8555, etc, parts.
 398  *
 399  */
 400 int cpu_init_r(void)
 401 {
 402         __maybe_unused u32 svr = get_svr();
 403 #ifdef CONFIG_SYS_LBC_LCRR
 404         fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 405 #endif
 406 #ifdef CONFIG_L2_CACHE
 407         ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
 408 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 409         struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 410 #endif
 411 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 412         extern int spin_table_compat;
 413         const char *spin;
 414 #endif
 415 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 416         ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
 417 #endif
 418 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 419         defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 420         /*
 421          * CPU22 and NMG_CPU_A011 share the same workaround.
 422          * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 423          * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 424          * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
 425          * fixed in 2.0. NMG_CPU_A011 is activated by default and can
 426          * be disabled by hwconfig with syntax:
 427          *
 428          * fsl_cpu_a011:disable
 429          */
 430         extern int enable_cpu_a011_workaround;
 431 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
 432         enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
 433 #else
 434         char buffer[HWCONFIG_BUFFER_SIZE];
 435         char *buf = NULL;
 436         int n, res;
 437
 438         n = getenv_f("hwconfig", buffer, sizeof(buffer));
 439         if (n > 0)
 440                 buf = buffer;
 441
 442         res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
 443         if (res > 0)
 444                 enable_cpu_a011_workaround = 0;
 445         else {
 446                 if (n >= HWCONFIG_BUFFER_SIZE) {
 447                         printf("fsl_cpu_a011 was not found. hwconfig variable "
 448                                 "may be too long\n");
 449                 }
 450                 enable_cpu_a011_workaround =
 451                         (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
 452                         (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
 453         }
 454 #endif
 455         if (enable_cpu_a011_workaround) {
 456                 flush_dcache();
 457                 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 458                 sync();
 459         }
 460 #endif
 461 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
 462         /*
 463          * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
 464          * in write shadow mode. Checking DCWS before setting SPR 976.
 465          */
 466         if (mfspr(L1CSR2) & L1CSR2_DCWS)
 467                 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
 468 #endif
 469
 470 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 471         spin = getenv("spin_table_compat");
 472         if (spin && (*spin == 'n'))
 473                 spin_table_compat = 0;
 474         else
 475                 spin_table_compat = 1;
 476 #endif
 477
 478         puts ("L2:    ");
 479
 480 #if defined(CONFIG_L2_CACHE)
 481         volatile uint cache_ctl;
 482         uint ver;
 483         u32 l2siz_field;
 484
 485         ver = SVR_SOC_VER(svr);
 486
 487         asm("msync;isync");
 488         cache_ctl = l2cache->l2ctl;
 489
 490 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 491         if (cache_ctl & MPC85xx_L2CTL_L2E) {
 492                 /* Clear L2 SRAM memory-mapped base address */
 493                 out_be32(&l2cache->l2srbar0, 0x0);
 494                 out_be32(&l2cache->l2srbar1, 0x0);
 495
 496                 /* set MBECCDIS=0, SBECCDIS=0 */
 497                 clrbits_be32(&l2cache->l2errdis,
 498                                 (MPC85xx_L2ERRDIS_MBECC |
 499                                  MPC85xx_L2ERRDIS_SBECC));
 500
 501                 /* set L2E=0, L2SRAM=0 */
 502                 clrbits_be32(&l2cache->l2ctl,
 503                                 (MPC85xx_L2CTL_L2E |
 504                                  MPC85xx_L2CTL_L2SRAM_ENTIRE));
 505         }
 506 #endif
 507
 508         l2siz_field = (cache_ctl >> 28) & 0x3;
 509
 510         switch (l2siz_field) {
 511         case 0x0:
 512                 printf(" unknown size (0x%08x)\n", cache_ctl);
 513                 return -1;
 514                 break;
 515         case 0x1:
 516                 if (ver == SVR_8540 || ver == SVR_8560   ||
 517                     ver == SVR_8541 || ver == SVR_8555) {
 518                         puts("128 KiB ");
 519                         /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
 520                         cache_ctl = 0xc4000000;
 521                 } else {
 522                         puts("256 KiB ");
 523                         cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 524                 }
 525                 break;
 526         case 0x2:
 527                 if (ver == SVR_8540 || ver == SVR_8560   ||
 528                     ver == SVR_8541 || ver == SVR_8555) {
 529                         puts("256 KiB ");
 530                         /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
 531                         cache_ctl = 0xc8000000;
 532                 } else {
 533                         puts("512 KiB ");
 534                         /* set L2E=1, L2I=1, & L2SRAM=0 */
 535                         cache_ctl = 0xc0000000;
 536                 }
 537                 break;
 538         case 0x3:
 539                 puts("1024 KiB ");
 540                 /* set L2E=1, L2I=1, & L2SRAM=0 */
 541                 cache_ctl = 0xc0000000;
 542                 break;
 543         }
 544
 545         if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 546                 puts("already enabled");
 547 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 548                 u32 l2srbar = l2cache->l2srbar0;
 549                 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 550                                 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
 551                         l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 552                         l2cache->l2srbar0 = l2srbar;
 553                         printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 554                 }
 555 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 556                 puts("\n");
 557         } else {
 558                 asm("msync;isync");
 559                 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 560                 asm("msync;isync");
 561                 puts("enabled\n");
 562         }
 563 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 564         if (SVR_SOC_VER(svr) == SVR_P2040) {
 565                 puts("N/A\n");
 566                 goto skip_l2;
 567         }
 568
 569         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 570
 571         /* invalidate the L2 cache */
 572         mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 573         while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 574                 ;
 575
 576 #ifdef CONFIG_SYS_CACHE_STASHING
 577         /* set stash id to (coreID) * 2 + 32 + L2 (1) */
 578         mtspr(SPRN_L2CSR1, (32 + 1));
 579 #endif
 580
 581         /* enable the cache */
 582         mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 583
 584         if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 585                 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 586                         ;
 587                 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
 588         }
 589
 590 skip_l2:
 591 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 592         if (l2cache->l2csr0 & L2CSR0_L2E)
 593                 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 594                            " enabled\n");
 595
 596         enable_cluster_l2();
 597 #else
 598         puts("disabled\n");
 599 #endif
 600
 601         enable_cpc();
 602
 603 #ifndef CONFIG_SYS_FSL_NO_SERDES
 604         /* needs to be in ram since code uses global static vars */
 605         fsl_serdes_init();
 606 #endif
 607
 608 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 609 #define MCFGR_AXIPIPE 0x000000f0
 610         if (IS_SVR_REV(svr, 1, 0))
 611                 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
 612 #endif
 613
 614 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 615         if (IS_SVR_REV(svr, 1, 0)) {
 616                 int i;
 617                 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
 618
 619                 for (i = 0; i < 12; i++) {
 620                         p += i + (i > 5 ? 11 : 0);
 621                         out_be32(p, 0x2);
 622                 }
 623                 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
 624                 out_be32(p, 0x34);
 625         }
 626 #endif
 627
 628 #ifdef CONFIG_SYS_SRIO
 629         srio_init();
 630 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 631         char *s = getenv("bootmaster");
 632         if (s) {
 633                 if (!strcmp(s, "SRIO1")) {
 634                         srio_boot_master(1);
 635                         srio_boot_master_release_slave(1);
 636                 }
 637                 if (!strcmp(s, "SRIO2")) {
 638                         srio_boot_master(2);
 639                         srio_boot_master_release_slave(2);
 640                 }
 641         }
 642 #endif
 643 #endif
 644
 645 #if defined(CONFIG_MP)
 646         setup_mp();
 647 #endif
 648
 649 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 650         {
 651                 if (SVR_MAJ(svr) < 3) {
 652                         void *p;
 653                         p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 654                         setbits_be32(p, 1 << (31 - 14));
 655                 }
 656         }
 657 #endif
 658
 659 #ifdef CONFIG_SYS_LBC_LCRR
 660         /*
 661          * Modify the CLKDIV field of LCRR register to improve the writing
 662          * speed for NOR flash.
 663          */
 664         clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 665         __raw_readl(&lbc->lcrr);
 666         isync();
 667 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 668         udelay(100);
 669 #endif
 670 #endif
 671
 672 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 673         {
 674                 struct ccsr_usb_phy __iomem *usb_phy1 =
 675                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 676 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 677                 if (has_erratum_a006261())
 678                         fsl_erratum_a006261_workaround(usb_phy1);
 679 #endif
 680                 out_be32(&usb_phy1->usb_enable_override,
 681                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 682         }
 683 #endif
 684 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 685         {
 686                 struct ccsr_usb_phy __iomem *usb_phy2 =
 687                         (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 688 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 689                 if (has_erratum_a006261())
 690                         fsl_erratum_a006261_workaround(usb_phy2);
 691 #endif
 692                 out_be32(&usb_phy2->usb_enable_override,
 693                                 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 694         }
 695 #endif
 696
 697 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 698         /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
 699          * multi-bit ECC errors which has impact on performance, so software
 700          * should disable all ECC reporting from USB1 and USB2.
 701          */
 702         if (IS_SVR_REV(get_svr(), 1, 0)) {
 703                 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
 704                         (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
 705                 setbits_be32(&dcfg->ecccr1,
 706                                 (DCSR_DCFG_ECC_DISABLE_USB1 |
 707                                  DCSR_DCFG_ECC_DISABLE_USB2));
 708         }
 709 #endif
 710
 711 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 712                 struct ccsr_usb_phy __iomem *usb_phy =
 713                         (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 714                 setbits_be32(&usb_phy->pllprg[1],
 715                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 716                              CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
 717                              CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
 718                              CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 719                 setbits_be32(&usb_phy->port1.ctrl,
 720                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 721                 setbits_be32(&usb_phy->port1.drvvbuscfg,
 722                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 723                 setbits_be32(&usb_phy->port1.pwrfltcfg,
 724                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 725                 setbits_be32(&usb_phy->port2.ctrl,
 726                              CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 727                 setbits_be32(&usb_phy->port2.drvvbuscfg,
 728                              CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 729                 setbits_be32(&usb_phy->port2.pwrfltcfg,
 730                              CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 731
 732 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 733                 if (has_erratum_a006261())
 734                         fsl_erratum_a006261_workaround(usb_phy);
 735 #endif
 736
 737 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 738
 739 #ifdef CONFIG_FMAN_ENET
 740         fman_enet_init();
 741 #endif
 742
 743 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
 744         /*
 745          * For P1022/1013 Rev1.0 silicon, after power on SATA host
 746          * controller is configured in legacy mode instead of the
 747          * expected enterprise mode. Software needs to clear bit[28]
 748          * of HControl register to change to enterprise mode from
 749          * legacy mode.  We assume that the controller is offline.
 750          */
 751         if (IS_SVR_REV(svr, 1, 0) &&
 752             ((SVR_SOC_VER(svr) == SVR_P1022) ||
 753              (SVR_SOC_VER(svr) == SVR_P1013))) {
 754                 fsl_sata_reg_t *reg;
 755
 756                 /* first SATA controller */
 757                 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
 758                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 759
 760                 /* second SATA controller */
 761                 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
 762                 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 763         }
 764 #endif
 765
 766
 767         return 0;
 768 }
 769
 770 extern void setup_ivors(void);
 771
 772 void arch_preboot_os(void)
 773 {
 774         u32 msr;
 775
 776         /*
 777          * We are changing interrupt offsets and are about to boot the OS so
 778          * we need to make sure we disable all async interrupts. EE is already
 779          * disabled by the time we get called.
 780          */
 781         msr = mfmsr();
 782         msr &= ~(MSR_ME|MSR_CE);
 783         mtmsr(msr);
 784
 785         setup_ivors();
 786 }
 787
 788 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
 789 int sata_initialize(void)
 790 {
 791         if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
 792                 return __sata_initialize();
 793
 794         return 1;
 795 }
 796 #endif
 797
 798 void cpu_secondary_init_r(void)
 799 {
 800 #ifdef CONFIG_QE
 801         uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 802 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 803         int ret;
 804         size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
 805
 806         /* load QE firmware from NAND flash to DDR first */
 807         ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
 808                         &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
 809
 810         if (ret && ret == -EUCLEAN) {
 811                 printf ("NAND read for QE firmware at offset %x failed %d\n",
 812                                 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
 813         }
 814 #endif
 815         qe_init(qe_base);
 816         qe_reset();
 817 #endif
 818 }