1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003 Motorola Inc.
6 * Modified by Xianghua Xiao, X.Xiao@motorola.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
17 #include <asm/processor.h>
22 #include <asm/cache.h>
24 #include <fsl_errata.h>
25 #include <asm/fsl_law.h>
26 #include <asm/fsl_serdes.h>
27 #include <asm/fsl_srio.h>
28 #ifdef CONFIG_FSL_CORENET
29 #include <asm/fsl_portals.h>
30 #include <asm/fsl_liodn.h>
31 #include <fsl_qbman.h>
35 #include <linux/compiler.h>
36 #include <linux/delay.h>
38 #ifdef CONFIG_CHAIN_OF_TRUST
39 #include <fsl_validate.h>
41 #ifdef CONFIG_FSL_CAAM
44 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
45 #include <asm/fsl_pamu.h>
46 #include <fsl_secboot_err.h>
48 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
52 #ifndef CONFIG_ARCH_QEMU_E500
55 #include "../../../../drivers/ata/fsl_sata.h"
60 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
62 * For deriving usb clock from 100MHz sysclk, reference divisor is set
63 * to a value of 5, which gives an intermediate value 20(100/5). The
64 * multiplication factor integer is set to 24, which when multiplied to
65 * above intermediate value provides clock for usb ip.
67 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
71 get_sys_info(&sysinfo);
72 if (sysinfo.diff_sysclk == 1) {
73 clrbits_be32(&usb_phy->pllprg[1],
74 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
75 setbits_be32(&usb_phy->pllprg[1],
76 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
77 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
78 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
83 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
84 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
86 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
87 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
89 /* Increase Disconnect Threshold by 50mV */
90 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
91 INC_DCNT_THRESHOLD_50MV;
92 /* Enable programming of USB High speed Disconnect threshold */
93 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
94 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
96 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
97 /* Increase Disconnect Threshold by 50mV */
98 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
99 INC_DCNT_THRESHOLD_50MV;
100 /* Enable programming of USB High speed Disconnect threshold */
101 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
102 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
106 u32 status = in_be32(&usb_phy->status1);
108 u32 squelch_prog_rd_0_2 =
109 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
110 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
112 u32 squelch_prog_rd_3_5 =
113 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
114 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
116 setbits_be32(&usb_phy->config1,
117 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
118 setbits_be32(&usb_phy->config2,
119 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
121 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
122 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
124 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
125 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
131 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
132 extern qe_iop_conf_t qe_iop_conf_tab[];
133 extern void qe_config_iopin(u8 port, u8 pin, int dir,
134 int open_drain, int assign);
135 extern void qe_init(uint qe_base);
136 extern void qe_reset(void);
138 static void config_qe_ioports(void)
141 int dir, open_drain, assign;
144 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
145 port = qe_iop_conf_tab[i].port;
146 pin = qe_iop_conf_tab[i].pin;
147 dir = qe_iop_conf_tab[i].dir;
148 open_drain = qe_iop_conf_tab[i].open_drain;
149 assign = qe_iop_conf_tab[i].assign;
150 qe_config_iopin(port, pin, dir, open_drain, assign);
156 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
160 for (portnum = 0; portnum < 4; portnum++) {
167 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
168 iop_conf_t *eiopc = iopc + 32;
173 * index 0 refers to pin 31,
174 * index 31 refers to pin 0
176 while (iopc < eiopc) {
196 volatile ioport_t *iop = ioport_addr (cpm, portnum);
200 * the (somewhat confused) paragraph at the
201 * bottom of page 35-5 warns that there might
202 * be "unknown behaviour" when programming
203 * PSORx and PDIRx, if PPARx = 1, so I
204 * decided this meant I had to disable the
205 * dedicated function first, and enable it
209 iop->psor = (iop->psor & tpmsk) | psor;
210 iop->podr = (iop->podr & tpmsk) | podr;
211 iop->pdat = (iop->pdat & tpmsk) | pdat;
212 iop->pdir = (iop->pdir & tpmsk) | pdir;
219 #ifdef CONFIG_SYS_FSL_CPC
220 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
221 void disable_cpc_sram(void)
225 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
227 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
228 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
229 /* find and disable LAW of SRAM */
230 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
232 if (law.index == -1) {
233 printf("\nFatal error happened\n");
236 disable_law(law.index);
238 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
239 out_be32(&cpc->cpccsr0, 0);
240 out_be32(&cpc->cpcsrcr0, 0);
246 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
248 #error POST memory test cannot be enabled with TDM
250 static void enable_tdm_law(void)
253 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
254 int tdm_hwconfig_enabled = 0;
257 * Extract hwconfig from environment since environment
258 * is not setup properly yet. Search for tdm entry in
261 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
263 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
264 /* If tdm is defined in hwconfig, set law for tdm workaround */
265 if (tdm_hwconfig_enabled)
266 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
272 void enable_cpc(void)
278 char buffer[HWCONFIG_BUFFER_SIZE];
280 bool have_hwconfig = false;
282 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
284 /* Extract hwconfig from environment */
285 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
288 * If "en_cpc" is not defined in hwconfig then by default all
289 * cpcs are enable. If this config is defined then individual
290 * cpcs which have to be enabled should also be defined.
291 * e.g en_cpc:cpc1,cpc2;
293 if (hwconfig_f("en_cpc", buffer))
294 have_hwconfig = true;
297 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
299 sprintf(cpc_subarg, "cpc%u", i + 1);
300 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
304 cpccfg0 = in_be32(&cpc->cpccfg0);
305 size += CPC_CFG0_SZ_K(cpccfg0);
307 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
308 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
310 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
311 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
313 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
314 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
316 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
317 if (has_erratum_a006379()) {
318 setbits_be32(&cpc->cpchdbcr0,
319 CPC_HDBCR0_SPLRU_LEVEL_EN);
323 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
324 /* Read back to sync write */
325 in_be32(&cpc->cpccsr0);
329 puts("Corenet Platform Cache: ");
330 print_size(size * 1024, " enabled\n");
333 static void invalidate_cpc(void)
336 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
338 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
339 /* skip CPC when it used as all SRAM */
340 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
342 /* Flash invalidate the CPC and clear all the locks */
343 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
344 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
350 #define invalidate_cpc()
351 #define disable_cpc_sram()
352 #endif /* CONFIG_SYS_FSL_CPC */
355 * Breathe some life into the CPU...
357 * Set up the memory map
358 * initialize a bunch of registers
361 #ifdef CONFIG_FSL_CORENET
362 static void corenet_tb_init(void)
364 volatile ccsr_rcpm_t *rcpm =
365 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
366 volatile ccsr_pic_t *pic =
367 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
368 u32 whoami = in_be32(&pic->whoami);
370 /* Enable the timebase register for this core */
371 out_be32(&rcpm->ctbenrl, (1 << whoami));
375 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
376 void fsl_erratum_a007212_workaround(void)
378 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
380 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
381 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
382 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
383 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
384 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
385 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
386 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
387 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
388 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
392 * Even this workaround applies to selected version of SoCs, it is
393 * safe to apply to all versions, with the limitation of odd ratios.
394 * If RCW has disabled DDR PLL, we have to apply this workaround,
395 * otherwise DDR will not work.
397 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
398 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
399 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
400 /* check if RCW sets ratio to 0, required by this workaround */
401 if (ddr_pll_ratio != 0)
403 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
404 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
405 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
406 /* check if reserved bits have the desired ratio */
407 if (ddr_pll_ratio == 0) {
408 printf("Error: Unknown DDR PLL ratio!\n");
413 setbits_be32(plldadcr1, 0x02000001);
414 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
415 setbits_be32(plldadcr2, 0x02000001);
416 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
417 setbits_be32(plldadcr3, 0x02000001);
420 setbits_be32(dpdovrcr4, 0xe0000000);
421 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
422 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
423 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
424 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
425 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
429 clrbits_be32(plldadcr1, 0x02000001);
430 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
431 clrbits_be32(plldadcr2, 0x02000001);
432 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
433 clrbits_be32(plldadcr3, 0x02000001);
436 clrbits_be32(dpdovrcr4, 0xe0000000);
440 ulong cpu_init_f(void)
442 extern void m8560_cpm_reset (void);
443 #ifdef CONFIG_SYS_DCSRBAR_PHYS
444 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
446 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
447 struct law_entry law;
449 #ifdef CONFIG_ARCH_MPC8548
450 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
451 uint svr = get_svr();
454 * CPU2 errata workaround: A core hang possible while executing
455 * a msync instruction and a snoopable transaction from an I/O
456 * master tagged to make quick forward progress is present.
457 * Fixed in silicon rev 2.1.
459 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
460 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
466 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
467 /* Disable the LAW created for NOR flash by the PBI commands */
468 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
470 disable_law(law.index);
472 #if defined(CONFIG_SYS_CPC_REINIT_F)
478 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
481 init_early_memctl_regs();
483 #if defined(CONFIG_CPM2)
487 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
488 /* Config QE ioports */
492 #if defined(CONFIG_FSL_DMA)
495 #ifdef CONFIG_FSL_CORENET
498 init_used_tlb_cams();
500 /* Invalidate the CPC before DDR gets enabled */
503 #ifdef CONFIG_SYS_DCSRBAR_PHYS
504 /* set DCSRCR so that DCSR space is 1G */
505 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
506 in_be32(&gur->dcsrcr);
509 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
510 fsl_erratum_a007212_workaround();
516 /* Implement a dummy function for those platforms w/o SERDES */
517 static void __fsl_serdes__init(void)
521 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
523 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
524 int enable_cluster_l2(void)
527 u32 cluster, svr = get_svr();
528 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
529 struct ccsr_cluster_l2 __iomem *l2cache;
531 /* only the L2 of first cluster should be enabled as expected on T4080,
532 * but there is no EOC in the first cluster as HW sake, so return here
533 * to skip enabling L2 cache of the 2nd cluster.
535 if (SVR_SOC_VER(svr) == SVR_T4080)
538 cluster = in_be32(&gur->tp_cluster[i].lower);
539 if (cluster & TP_CLUSTER_EOC)
542 /* The first cache has already been set up, so skip it */
545 /* Look through the remaining clusters, and set up their caches */
547 int j, cluster_valid = 0;
549 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
551 cluster = in_be32(&gur->tp_cluster[i].lower);
553 /* check that at least one core/accel is enabled in cluster */
554 for (j = 0; j < 4; j++) {
555 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
556 u32 type = in_be32(&gur->tp_ityp[idx]);
558 if ((type & TP_ITYP_AV) &&
559 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
564 /* set stash ID to (cluster) * 2 + 32 + 1 */
565 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
567 printf("enable l2 for cluster %d %p\n", i, l2cache);
569 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
570 while ((in_be32(&l2cache->l2csr0)
571 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
573 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
576 } while (!(cluster & TP_CLUSTER_EOC));
583 * Initialize L2 as cache.
585 int l2cache_init(void)
587 __maybe_unused u32 svr = get_svr();
588 #ifdef CONFIG_L2_CACHE
589 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
590 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
591 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
596 #if defined(CONFIG_L2_CACHE)
597 volatile uint cache_ctl;
601 ver = SVR_SOC_VER(svr);
604 cache_ctl = l2cache->l2ctl;
606 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
607 if (cache_ctl & MPC85xx_L2CTL_L2E) {
608 /* Clear L2 SRAM memory-mapped base address */
609 out_be32(&l2cache->l2srbar0, 0x0);
610 out_be32(&l2cache->l2srbar1, 0x0);
612 /* set MBECCDIS=0, SBECCDIS=0 */
613 clrbits_be32(&l2cache->l2errdis,
614 (MPC85xx_L2ERRDIS_MBECC |
615 MPC85xx_L2ERRDIS_SBECC));
617 /* set L2E=0, L2SRAM=0 */
618 clrbits_be32(&l2cache->l2ctl,
620 MPC85xx_L2CTL_L2SRAM_ENTIRE));
624 l2siz_field = (cache_ctl >> 28) & 0x3;
626 switch (l2siz_field) {
628 printf(" unknown size (0x%08x)\n", cache_ctl);
632 if (ver == SVR_8540 || ver == SVR_8560 ||
633 ver == SVR_8541 || ver == SVR_8555) {
635 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
636 cache_ctl = 0xc4000000;
639 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
643 if (ver == SVR_8540 || ver == SVR_8560 ||
644 ver == SVR_8541 || ver == SVR_8555) {
646 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
647 cache_ctl = 0xc8000000;
650 /* set L2E=1, L2I=1, & L2SRAM=0 */
651 cache_ctl = 0xc0000000;
656 /* set L2E=1, L2I=1, & L2SRAM=0 */
657 cache_ctl = 0xc0000000;
661 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
662 puts("already enabled");
663 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
664 u32 l2srbar = l2cache->l2srbar0;
665 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
666 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
667 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
668 l2cache->l2srbar0 = l2srbar;
669 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
671 #endif /* CONFIG_SYS_INIT_L2_ADDR */
675 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
679 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
680 if (SVR_SOC_VER(svr) == SVR_P2040) {
685 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
687 /* invalidate the L2 cache */
688 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
689 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
692 #ifdef CONFIG_SYS_CACHE_STASHING
693 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
694 mtspr(SPRN_L2CSR1, (32 + 1));
697 /* enable the cache */
698 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
700 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
701 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
703 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
707 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
708 if (l2cache->l2csr0 & L2CSR0_L2E)
709 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
722 * The newer 8548, etc, parts have twice as much cache, but
723 * use the same bit-encoding as the older 8555, etc, parts.
728 __maybe_unused u32 svr = get_svr();
729 #ifdef CONFIG_SYS_LBC_LCRR
730 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
732 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
733 extern int spin_table_compat;
736 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
737 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
739 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
740 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
742 * CPU22 and NMG_CPU_A011 share the same workaround.
743 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
744 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
745 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
746 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
747 * be disabled by hwconfig with syntax:
749 * fsl_cpu_a011:disable
751 extern int enable_cpu_a011_workaround;
752 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
753 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
755 char buffer[HWCONFIG_BUFFER_SIZE];
759 n = env_get_f("hwconfig", buffer, sizeof(buffer));
763 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
765 enable_cpu_a011_workaround = 0;
767 if (n >= HWCONFIG_BUFFER_SIZE) {
768 printf("fsl_cpu_a011 was not found. hwconfig variable "
769 "may be too long\n");
771 enable_cpu_a011_workaround =
772 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
773 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
776 if (enable_cpu_a011_workaround) {
778 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
783 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
785 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
789 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
791 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
792 * in write shadow mode. Checking DCWS before setting SPR 976.
794 if (mfspr(L1CSR2) & L1CSR2_DCWS)
795 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
798 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
799 spin = env_get("spin_table_compat");
800 if (spin && (*spin == 'n'))
801 spin_table_compat = 0;
803 spin_table_compat = 1;
806 #ifdef CONFIG_FSL_CORENET
808 #ifdef CONFIG_SYS_DPAA_QBMAN
809 setup_qbman_portals();
814 #if defined(CONFIG_RAMBOOT_PBL)
818 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
822 #ifndef CONFIG_SYS_FSL_NO_SERDES
823 /* needs to be in ram since code uses global static vars */
827 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
828 #define MCFGR_AXIPIPE 0x000000f0
829 if (IS_SVR_REV(svr, 1, 0))
830 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
833 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
834 if (IS_SVR_REV(svr, 1, 0)) {
836 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
838 for (i = 0; i < 12; i++) {
839 p += i + (i > 5 ? 11 : 0);
842 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
847 #ifdef CONFIG_SYS_SRIO
849 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
850 char *s = env_get("bootmaster");
852 if (!strcmp(s, "SRIO1")) {
854 srio_boot_master_release_slave(1);
856 if (!strcmp(s, "SRIO2")) {
858 srio_boot_master_release_slave(2);
864 #if defined(CONFIG_MP)
868 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
870 if (SVR_MAJ(svr) < 3) {
872 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
873 setbits_be32(p, 1 << (31 - 14));
878 #ifdef CONFIG_SYS_LBC_LCRR
880 * Modify the CLKDIV field of LCRR register to improve the writing
881 * speed for NOR flash.
883 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
884 __raw_readl(&lbc->lcrr);
886 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
891 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
893 struct ccsr_usb_phy __iomem *usb_phy1 =
894 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
895 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
896 if (has_erratum_a006261())
897 fsl_erratum_a006261_workaround(usb_phy1);
899 out_be32(&usb_phy1->usb_enable_override,
900 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
903 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
905 struct ccsr_usb_phy __iomem *usb_phy2 =
906 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
907 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
908 if (has_erratum_a006261())
909 fsl_erratum_a006261_workaround(usb_phy2);
911 out_be32(&usb_phy2->usb_enable_override,
912 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
916 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
917 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
918 * multi-bit ECC errors which has impact on performance, so software
919 * should disable all ECC reporting from USB1 and USB2.
921 if (IS_SVR_REV(get_svr(), 1, 0)) {
922 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
923 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
924 setbits_be32(&dcfg->ecccr1,
925 (DCSR_DCFG_ECC_DISABLE_USB1 |
926 DCSR_DCFG_ECC_DISABLE_USB2));
930 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
931 struct ccsr_usb_phy __iomem *usb_phy =
932 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
933 setbits_be32(&usb_phy->pllprg[1],
934 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
935 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
936 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
937 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
938 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
939 usb_single_source_clk_configure(usb_phy);
941 setbits_be32(&usb_phy->port1.ctrl,
942 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
943 setbits_be32(&usb_phy->port1.drvvbuscfg,
944 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
945 setbits_be32(&usb_phy->port1.pwrfltcfg,
946 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
947 setbits_be32(&usb_phy->port2.ctrl,
948 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
949 setbits_be32(&usb_phy->port2.drvvbuscfg,
950 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
951 setbits_be32(&usb_phy->port2.pwrfltcfg,
952 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
954 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
955 if (has_erratum_a006261())
956 fsl_erratum_a006261_workaround(usb_phy);
959 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
961 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
962 erratum_a009942_check_cpo();
965 #ifdef CONFIG_FMAN_ENET
966 #ifndef CONFIG_DM_ETH
971 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
973 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
976 #ifdef CONFIG_FSL_CAAM
979 #if defined(CONFIG_ARCH_C29X)
980 if ((SVR_SOC_VER(svr) == SVR_C292) ||
981 (SVR_SOC_VER(svr) == SVR_C293))
984 if (SVR_SOC_VER(svr) == SVR_C293)
989 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
991 * For P1022/1013 Rev1.0 silicon, after power on SATA host
992 * controller is configured in legacy mode instead of the
993 * expected enterprise mode. Software needs to clear bit[28]
994 * of HControl register to change to enterprise mode from
995 * legacy mode. We assume that the controller is offline.
997 if (IS_SVR_REV(svr, 1, 0) &&
998 ((SVR_SOC_VER(svr) == SVR_P1022) ||
999 (SVR_SOC_VER(svr) == SVR_P1013))) {
1000 fsl_sata_reg_t *reg;
1002 /* first SATA controller */
1003 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
1004 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
1006 /* second SATA controller */
1007 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
1008 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
1012 init_used_tlb_cams();
1017 void arch_preboot_os(void)
1022 * We are changing interrupt offsets and are about to boot the OS so
1023 * we need to make sure we disable all async interrupts. EE is already
1024 * disabled by the time we get called.
1027 msr &= ~(MSR_ME|MSR_CE);
1031 int cpu_secondary_init_r(void)
1035 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
1037 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
1047 #ifdef CONFIG_BOARD_LATE_INIT
1048 int board_late_init(void)
1050 #ifdef CONFIG_CHAIN_OF_TRUST
1051 fsl_setenv_chain_of_trust();