1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003 Motorola Inc.
6 * Modified by Xianghua Xiao, X.Xiao@motorola.com
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #include <display_options.h>
18 #include <asm/processor.h>
23 #include <asm/cache.h>
25 #include <fsl_errata.h>
26 #include <asm/fsl_law.h>
27 #include <asm/fsl_serdes.h>
28 #include <asm/fsl_srio.h>
29 #ifdef CONFIG_FSL_CORENET
30 #include <asm/fsl_portals.h>
31 #include <asm/fsl_liodn.h>
32 #include <fsl_qbman.h>
36 #include <linux/compiler.h>
37 #include <linux/delay.h>
39 #ifdef CONFIG_CHAIN_OF_TRUST
40 #include <fsl_validate.h>
42 #ifdef CONFIG_FSL_CAAM
45 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
46 #include <asm/fsl_pamu.h>
47 #include <fsl_secboot_err.h>
49 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
53 #ifndef CONFIG_ARCH_QEMU_E500
56 #include "../../../../drivers/ata/fsl_sata.h"
62 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
64 * For deriving usb clock from 100MHz sysclk, reference divisor is set
65 * to a value of 5, which gives an intermediate value 20(100/5). The
66 * multiplication factor integer is set to 24, which when multiplied to
67 * above intermediate value provides clock for usb ip.
69 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
73 get_sys_info(&sysinfo);
74 if (sysinfo.diff_sysclk == 1) {
75 clrbits_be32(&usb_phy->pllprg[1],
76 CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
77 setbits_be32(&usb_phy->pllprg[1],
78 CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
79 CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
80 CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
85 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
86 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
88 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
89 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
91 /* Increase Disconnect Threshold by 50mV */
92 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
93 INC_DCNT_THRESHOLD_50MV;
94 /* Enable programming of USB High speed Disconnect threshold */
95 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
96 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
98 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
99 /* Increase Disconnect Threshold by 50mV */
100 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
101 INC_DCNT_THRESHOLD_50MV;
102 /* Enable programming of USB High speed Disconnect threshold */
103 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
104 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
108 u32 status = in_be32(&usb_phy->status1);
110 u32 squelch_prog_rd_0_2 =
111 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
112 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
114 u32 squelch_prog_rd_3_5 =
115 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
116 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
118 setbits_be32(&usb_phy->config1,
119 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
120 setbits_be32(&usb_phy->config2,
121 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
123 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
124 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
126 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
127 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
133 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
134 extern qe_iop_conf_t qe_iop_conf_tab[];
135 extern void qe_config_iopin(u8 port, u8 pin, int dir,
136 int open_drain, int assign);
137 extern void qe_init(uint qe_base);
138 extern void qe_reset(void);
140 static void config_qe_ioports(void)
143 int dir, open_drain, assign;
146 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
147 port = qe_iop_conf_tab[i].port;
148 pin = qe_iop_conf_tab[i].pin;
149 dir = qe_iop_conf_tab[i].dir;
150 open_drain = qe_iop_conf_tab[i].open_drain;
151 assign = qe_iop_conf_tab[i].assign;
152 qe_config_iopin(port, pin, dir, open_drain, assign);
157 #ifdef CONFIG_SYS_FSL_CPC
158 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
159 void disable_cpc_sram(void)
163 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
165 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
166 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
167 /* find and disable LAW of SRAM */
168 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
170 if (law.index == -1) {
171 printf("\nFatal error happened\n");
174 disable_law(law.index);
176 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
177 out_be32(&cpc->cpccsr0, 0);
178 out_be32(&cpc->cpcsrcr0, 0);
184 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
186 #error POST memory test cannot be enabled with TDM
188 static void enable_tdm_law(void)
191 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
192 int tdm_hwconfig_enabled = 0;
195 * Extract hwconfig from environment since environment
196 * is not setup properly yet. Search for tdm entry in
199 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
201 tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
202 /* If tdm is defined in hwconfig, set law for tdm workaround */
203 if (tdm_hwconfig_enabled)
204 set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
210 void enable_cpc(void)
216 char buffer[HWCONFIG_BUFFER_SIZE];
218 bool have_hwconfig = false;
220 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
222 /* Extract hwconfig from environment */
223 ret = env_get_f("hwconfig", buffer, sizeof(buffer));
226 * If "en_cpc" is not defined in hwconfig then by default all
227 * cpcs are enable. If this config is defined then individual
228 * cpcs which have to be enabled should also be defined.
229 * e.g en_cpc:cpc1,cpc2;
231 if (hwconfig_f("en_cpc", buffer))
232 have_hwconfig = true;
235 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
237 sprintf(cpc_subarg, "cpc%u", i + 1);
238 cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
242 cpccfg0 = in_be32(&cpc->cpccfg0);
243 size += CPC_CFG0_SZ_K(cpccfg0);
245 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
246 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
248 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
249 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
251 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
252 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
254 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
255 if (has_erratum_a006379()) {
256 setbits_be32(&cpc->cpchdbcr0,
257 CPC_HDBCR0_SPLRU_LEVEL_EN);
261 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
262 /* Read back to sync write */
263 in_be32(&cpc->cpccsr0);
267 puts("Corenet Platform Cache: ");
268 print_size(size * 1024, " enabled\n");
271 static void invalidate_cpc(void)
274 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
276 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
277 /* skip CPC when it used as all SRAM */
278 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
280 /* Flash invalidate the CPC and clear all the locks */
281 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
282 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
288 #define invalidate_cpc()
289 #define disable_cpc_sram()
290 #endif /* CONFIG_SYS_FSL_CPC */
293 * Breathe some life into the CPU...
295 * Set up the memory map
296 * initialize a bunch of registers
299 #ifdef CONFIG_FSL_CORENET
300 static void corenet_tb_init(void)
302 volatile ccsr_rcpm_t *rcpm =
303 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
304 volatile ccsr_pic_t *pic =
305 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
306 u32 whoami = in_be32(&pic->whoami);
308 /* Enable the timebase register for this core */
309 out_be32(&rcpm->ctbenrl, (1 << whoami));
313 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
314 void fsl_erratum_a007212_workaround(void)
316 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
318 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
319 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
320 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
321 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
322 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
323 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
324 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
325 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
326 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
330 * Even this workaround applies to selected version of SoCs, it is
331 * safe to apply to all versions, with the limitation of odd ratios.
332 * If RCW has disabled DDR PLL, we have to apply this workaround,
333 * otherwise DDR will not work.
335 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
336 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
337 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
338 /* check if RCW sets ratio to 0, required by this workaround */
339 if (ddr_pll_ratio != 0)
341 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
342 FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
343 FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
344 /* check if reserved bits have the desired ratio */
345 if (ddr_pll_ratio == 0) {
346 printf("Error: Unknown DDR PLL ratio!\n");
351 setbits_be32(plldadcr1, 0x02000001);
352 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
353 setbits_be32(plldadcr2, 0x02000001);
354 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
355 setbits_be32(plldadcr3, 0x02000001);
358 setbits_be32(dpdovrcr4, 0xe0000000);
359 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
360 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
361 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
362 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
363 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
367 clrbits_be32(plldadcr1, 0x02000001);
368 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
369 clrbits_be32(plldadcr2, 0x02000001);
370 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
371 clrbits_be32(plldadcr3, 0x02000001);
374 clrbits_be32(dpdovrcr4, 0xe0000000);
378 ulong cpu_init_f(void)
380 extern void m8560_cpm_reset (void);
381 #ifdef CONFIG_SYS_DCSRBAR_PHYS
382 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
384 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
385 struct law_entry law;
387 #ifdef CONFIG_ARCH_MPC8548
388 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
389 uint svr = get_svr();
392 * CPU2 errata workaround: A core hang possible while executing
393 * a msync instruction and a snoopable transaction from an I/O
394 * master tagged to make quick forward progress is present.
395 * Fixed in silicon rev 2.1.
397 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
398 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
404 #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
405 /* Disable the LAW created for NOR flash by the PBI commands */
406 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
408 disable_law(law.index);
410 #if defined(CONFIG_SYS_CPC_REINIT_F)
415 init_early_memctl_regs();
417 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
418 /* Config QE ioports */
422 #if defined(CONFIG_FSL_DMA)
425 #ifdef CONFIG_FSL_CORENET
428 init_used_tlb_cams();
430 /* Invalidate the CPC before DDR gets enabled */
433 #ifdef CONFIG_SYS_DCSRBAR_PHYS
434 /* set DCSRCR so that DCSR space is 1G */
435 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
436 in_be32(&gur->dcsrcr);
439 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
440 fsl_erratum_a007212_workaround();
446 /* Implement a dummy function for those platforms w/o SERDES */
447 static void __fsl_serdes__init(void)
451 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
453 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
454 int enable_cluster_l2(void)
457 u32 cluster, svr = get_svr();
458 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
459 struct ccsr_cluster_l2 __iomem *l2cache;
461 /* only the L2 of first cluster should be enabled as expected on T4080,
462 * but there is no EOC in the first cluster as HW sake, so return here
463 * to skip enabling L2 cache of the 2nd cluster.
465 if (SVR_SOC_VER(svr) == SVR_T4080)
468 cluster = in_be32(&gur->tp_cluster[i].lower);
469 if (cluster & TP_CLUSTER_EOC)
472 /* The first cache has already been set up, so skip it */
475 /* Look through the remaining clusters, and set up their caches */
477 int j, cluster_valid = 0;
479 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
481 cluster = in_be32(&gur->tp_cluster[i].lower);
483 /* check that at least one core/accel is enabled in cluster */
484 for (j = 0; j < 4; j++) {
485 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
486 u32 type = in_be32(&gur->tp_ityp[idx]);
488 if ((type & TP_ITYP_AV) &&
489 TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
494 /* set stash ID to (cluster) * 2 + 32 + 1 */
495 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
497 printf("enable l2 for cluster %d %p\n", i, l2cache);
499 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
500 while ((in_be32(&l2cache->l2csr0)
501 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
503 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
506 } while (!(cluster & TP_CLUSTER_EOC));
513 * Initialize L2 as cache.
515 int l2cache_init(void)
517 __maybe_unused u32 svr = get_svr();
518 #ifdef CONFIG_L2_CACHE
519 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
520 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
521 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
526 #if defined(CONFIG_L2_CACHE)
527 volatile uint cache_ctl;
531 ver = SVR_SOC_VER(svr);
534 cache_ctl = l2cache->l2ctl;
536 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
537 if (cache_ctl & MPC85xx_L2CTL_L2E) {
538 /* Clear L2 SRAM memory-mapped base address */
539 out_be32(&l2cache->l2srbar0, 0x0);
540 out_be32(&l2cache->l2srbar1, 0x0);
542 /* set MBECCDIS=0, SBECCDIS=0 */
543 clrbits_be32(&l2cache->l2errdis,
544 (MPC85xx_L2ERRDIS_MBECC |
545 MPC85xx_L2ERRDIS_SBECC));
547 /* set L2E=0, L2SRAM=0 */
548 clrbits_be32(&l2cache->l2ctl,
550 MPC85xx_L2CTL_L2SRAM_ENTIRE));
554 l2siz_field = (cache_ctl >> 28) & 0x3;
556 switch (l2siz_field) {
558 printf(" unknown size (0x%08x)\n", cache_ctl);
562 if (ver == SVR_8540 || ver == SVR_8560 ||
563 ver == SVR_8541 || ver == SVR_8555) {
565 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
566 cache_ctl = 0xc4000000;
569 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
573 if (ver == SVR_8540 || ver == SVR_8560 ||
574 ver == SVR_8541 || ver == SVR_8555) {
576 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
577 cache_ctl = 0xc8000000;
580 /* set L2E=1, L2I=1, & L2SRAM=0 */
581 cache_ctl = 0xc0000000;
586 /* set L2E=1, L2I=1, & L2SRAM=0 */
587 cache_ctl = 0xc0000000;
591 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
592 puts("already enabled");
593 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
594 u32 l2srbar = l2cache->l2srbar0;
595 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
596 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
597 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
598 l2cache->l2srbar0 = l2srbar;
599 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
601 #endif /* CONFIG_SYS_INIT_L2_ADDR */
605 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
609 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
610 if (SVR_SOC_VER(svr) == SVR_P2040) {
615 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
617 /* invalidate the L2 cache */
618 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
619 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
622 #ifdef CONFIG_SYS_CACHE_STASHING
623 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
624 mtspr(SPRN_L2CSR1, (32 + 1));
627 /* enable the cache */
628 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
630 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
631 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
633 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
637 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
638 if (l2cache->l2csr0 & L2CSR0_L2E)
639 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
652 * The newer 8548, etc, parts have twice as much cache, but
653 * use the same bit-encoding as the older 8555, etc, parts.
658 __maybe_unused u32 svr = get_svr();
659 #ifdef CONFIG_SYS_LBC_LCRR
660 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
662 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
663 extern int spin_table_compat;
666 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
667 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
669 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
670 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
672 * CPU22 and NMG_CPU_A011 share the same workaround.
673 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
674 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
675 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
676 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
677 * be disabled by hwconfig with syntax:
679 * fsl_cpu_a011:disable
681 extern int enable_cpu_a011_workaround;
682 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
683 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
685 char buffer[HWCONFIG_BUFFER_SIZE];
689 n = env_get_f("hwconfig", buffer, sizeof(buffer));
693 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
695 enable_cpu_a011_workaround = 0;
697 if (n >= HWCONFIG_BUFFER_SIZE) {
698 printf("fsl_cpu_a011 was not found. hwconfig variable "
699 "may be too long\n");
701 enable_cpu_a011_workaround =
702 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
703 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
706 if (enable_cpu_a011_workaround) {
708 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
713 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
715 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
719 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
721 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
722 * in write shadow mode. Checking DCWS before setting SPR 976.
724 if (mfspr(L1CSR2) & L1CSR2_DCWS)
725 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
728 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
729 spin = env_get("spin_table_compat");
730 if (spin && (*spin == 'n'))
731 spin_table_compat = 0;
733 spin_table_compat = 1;
736 #ifdef CONFIG_FSL_CORENET
738 #ifdef CONFIG_SYS_DPAA_QBMAN
739 setup_qbman_portals();
744 #if defined(CONFIG_RAMBOOT_PBL)
748 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
752 #ifndef CONFIG_SYS_FSL_NO_SERDES
753 /* needs to be in ram since code uses global static vars */
757 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
758 #define MCFGR_AXIPIPE 0x000000f0
759 if (IS_SVR_REV(svr, 1, 0))
760 sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
763 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
764 if (IS_SVR_REV(svr, 1, 0)) {
766 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
768 for (i = 0; i < 12; i++) {
769 p += i + (i > 5 ? 11 : 0);
772 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
777 #ifdef CONFIG_SYS_SRIO
779 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
780 char *s = env_get("bootmaster");
782 if (!strcmp(s, "SRIO1")) {
784 srio_boot_master_release_slave(1);
786 if (!strcmp(s, "SRIO2")) {
788 srio_boot_master_release_slave(2);
794 #if defined(CONFIG_MP)
798 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
800 if (SVR_MAJ(svr) < 3) {
802 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
803 setbits_be32(p, 1 << (31 - 14));
808 #ifdef CONFIG_SYS_LBC_LCRR
810 * Modify the CLKDIV field of LCRR register to improve the writing
811 * speed for NOR flash.
813 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
814 __raw_readl(&lbc->lcrr);
816 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
821 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
823 struct ccsr_usb_phy __iomem *usb_phy1 =
824 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
825 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
826 if (has_erratum_a006261())
827 fsl_erratum_a006261_workaround(usb_phy1);
829 out_be32(&usb_phy1->usb_enable_override,
830 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
833 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
835 struct ccsr_usb_phy __iomem *usb_phy2 =
836 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
837 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
838 if (has_erratum_a006261())
839 fsl_erratum_a006261_workaround(usb_phy2);
841 out_be32(&usb_phy2->usb_enable_override,
842 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
846 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
847 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
848 * multi-bit ECC errors which has impact on performance, so software
849 * should disable all ECC reporting from USB1 and USB2.
851 if (IS_SVR_REV(get_svr(), 1, 0)) {
852 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
853 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
854 setbits_be32(&dcfg->ecccr1,
855 (DCSR_DCFG_ECC_DISABLE_USB1 |
856 DCSR_DCFG_ECC_DISABLE_USB2));
860 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
861 struct ccsr_usb_phy __iomem *usb_phy =
862 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
863 setbits_be32(&usb_phy->pllprg[1],
864 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
865 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
866 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
867 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
868 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
869 usb_single_source_clk_configure(usb_phy);
871 setbits_be32(&usb_phy->port1.ctrl,
872 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
873 setbits_be32(&usb_phy->port1.drvvbuscfg,
874 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
875 setbits_be32(&usb_phy->port1.pwrfltcfg,
876 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
877 setbits_be32(&usb_phy->port2.ctrl,
878 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
879 setbits_be32(&usb_phy->port2.drvvbuscfg,
880 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
881 setbits_be32(&usb_phy->port2.pwrfltcfg,
882 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
884 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
885 if (has_erratum_a006261())
886 fsl_erratum_a006261_workaround(usb_phy);
889 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
891 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
892 erratum_a009942_check_cpo();
895 #ifdef CONFIG_FMAN_ENET
896 #ifndef CONFIG_DM_ETH
901 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
903 fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
906 #ifdef CONFIG_FSL_CAAM
907 #if defined(CONFIG_ARCH_C29X)
908 if ((SVR_SOC_VER(svr) == SVR_C292) ||
909 (SVR_SOC_VER(svr) == SVR_C293))
912 if (SVR_SOC_VER(svr) == SVR_C293)
917 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
919 * For P1022/1013 Rev1.0 silicon, after power on SATA host
920 * controller is configured in legacy mode instead of the
921 * expected enterprise mode. Software needs to clear bit[28]
922 * of HControl register to change to enterprise mode from
923 * legacy mode. We assume that the controller is offline.
925 if (IS_SVR_REV(svr, 1, 0) &&
926 ((SVR_SOC_VER(svr) == SVR_P1022) ||
927 (SVR_SOC_VER(svr) == SVR_P1013))) {
930 /* first SATA controller */
931 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
932 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
934 /* second SATA controller */
935 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
936 clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
940 init_used_tlb_cams();
945 #ifdef CONFIG_ARCH_MISC_INIT
946 int arch_misc_init(void)
948 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
952 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
954 printf("Failed to initialize caam_jr: %d\n", ret);
961 void arch_preboot_os(void)
966 * We are changing interrupt offsets and are about to boot the OS so
967 * we need to make sure we disable all async interrupts. EE is already
968 * disabled by the time we get called.
971 msr &= ~(MSR_ME|MSR_CE);
975 int cpu_secondary_init_r(void)
979 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
981 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
991 #ifdef CONFIG_BOARD_LATE_INIT
992 int board_late_init(void)
994 #ifdef CONFIG_CHAIN_OF_TRUST
995 fsl_setenv_chain_of_trust();