2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <asm/cache.h>
37 #include <asm/fsl_law.h>
38 #include <asm/fsl_serdes.h>
41 DECLARE_GLOBAL_DATA_PTR;
44 extern qe_iop_conf_t qe_iop_conf_tab[];
45 extern void qe_config_iopin(u8 port, u8 pin, int dir,
46 int open_drain, int assign);
47 extern void qe_init(uint qe_base);
48 extern void qe_reset(void);
50 static void config_qe_ioports(void)
53 int dir, open_drain, assign;
56 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
57 port = qe_iop_conf_tab[i].port;
58 pin = qe_iop_conf_tab[i].pin;
59 dir = qe_iop_conf_tab[i].dir;
60 open_drain = qe_iop_conf_tab[i].open_drain;
61 assign = qe_iop_conf_tab[i].assign;
62 qe_config_iopin(port, pin, dir, open_drain, assign);
68 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
72 for (portnum = 0; portnum < 4; portnum++) {
79 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
80 iop_conf_t *eiopc = iopc + 32;
85 * index 0 refers to pin 31,
86 * index 31 refers to pin 0
88 while (iopc < eiopc) {
108 volatile ioport_t *iop = ioport_addr (cpm, portnum);
112 * the (somewhat confused) paragraph at the
113 * bottom of page 35-5 warns that there might
114 * be "unknown behaviour" when programming
115 * PSORx and PDIRx, if PPARx = 1, so I
116 * decided this meant I had to disable the
117 * dedicated function first, and enable it
121 iop->psor = (iop->psor & tpmsk) | psor;
122 iop->podr = (iop->podr & tpmsk) | podr;
123 iop->pdat = (iop->pdat & tpmsk) | pdat;
124 iop->pdir = (iop->pdir & tpmsk) | pdir;
131 #ifdef CONFIG_SYS_FSL_CPC
132 static void enable_cpc(void)
137 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
139 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
140 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
141 size += CPC_CFG0_SZ_K(cpccfg0);
143 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
144 /* Read back to sync write */
145 in_be32(&cpc->cpccsr0);
149 printf("Corenet Platform Cache: %d KB enabled\n", size);
152 void invalidate_cpc(void)
155 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
157 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
158 /* Flash invalidate the CPC and clear all the locks */
159 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
160 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
166 #define invalidate_cpc()
167 #endif /* CONFIG_SYS_FSL_CPC */
170 * Breathe some life into the CPU...
172 * Set up the memory map
173 * initialize a bunch of registers
176 #ifdef CONFIG_FSL_CORENET
177 static void corenet_tb_init(void)
179 volatile ccsr_rcpm_t *rcpm =
180 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
181 volatile ccsr_pic_t *pic =
182 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
183 u32 whoami = in_be32(&pic->whoami);
185 /* Enable the timebase register for this core */
186 out_be32(&rcpm->ctbenrl, (1 << whoami));
190 void cpu_init_f (void)
192 extern void m8560_cpm_reset (void);
193 #ifdef CONFIG_MPC8548
194 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
195 uint svr = get_svr();
198 * CPU2 errata workaround: A core hang possible while executing
199 * a msync instruction and a snoopable transaction from an I/O
200 * master tagged to make quick forward progress is present.
201 * Fixed in silicon rev 2.1.
203 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
204 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
211 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
214 init_early_memctl_regs();
216 #if defined(CONFIG_CPM2)
220 /* Config QE ioports */
223 #if defined(CONFIG_FSL_DMA)
226 #ifdef CONFIG_FSL_CORENET
229 init_used_tlb_cams();
231 /* Invalidate the CPC before DDR gets enabled */
237 * Initialize L2 as cache.
239 * The newer 8548, etc, parts have twice as much cache, but
240 * use the same bit-encoding as the older 8555, etc, parts.
245 #ifdef CONFIG_SYS_LBC_LCRR
246 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
249 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
251 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
257 #if defined(CONFIG_L2_CACHE)
258 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
259 volatile uint cache_ctl;
265 ver = SVR_SOC_VER(svr);
268 cache_ctl = l2cache->l2ctl;
270 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
271 if (cache_ctl & MPC85xx_L2CTL_L2E) {
272 /* Clear L2 SRAM memory-mapped base address */
273 out_be32(&l2cache->l2srbar0, 0x0);
274 out_be32(&l2cache->l2srbar1, 0x0);
276 /* set MBECCDIS=0, SBECCDIS=0 */
277 clrbits_be32(&l2cache->l2errdis,
278 (MPC85xx_L2ERRDIS_MBECC |
279 MPC85xx_L2ERRDIS_SBECC));
281 /* set L2E=0, L2SRAM=0 */
282 clrbits_be32(&l2cache->l2ctl,
284 MPC85xx_L2CTL_L2SRAM_ENTIRE));
288 l2siz_field = (cache_ctl >> 28) & 0x3;
290 switch (l2siz_field) {
292 printf(" unknown size (0x%08x)\n", cache_ctl);
296 if (ver == SVR_8540 || ver == SVR_8560 ||
297 ver == SVR_8541 || ver == SVR_8541_E ||
298 ver == SVR_8555 || ver == SVR_8555_E) {
300 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
301 cache_ctl = 0xc4000000;
304 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
308 if (ver == SVR_8540 || ver == SVR_8560 ||
309 ver == SVR_8541 || ver == SVR_8541_E ||
310 ver == SVR_8555 || ver == SVR_8555_E) {
312 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
313 cache_ctl = 0xc8000000;
316 /* set L2E=1, L2I=1, & L2SRAM=0 */
317 cache_ctl = 0xc0000000;
322 /* set L2E=1, L2I=1, & L2SRAM=0 */
323 cache_ctl = 0xc0000000;
327 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
328 puts("already enabled");
329 l2srbar = l2cache->l2srbar0;
330 #ifdef CONFIG_SYS_INIT_L2_ADDR
331 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
332 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
333 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
334 l2cache->l2srbar0 = l2srbar;
335 printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
337 #endif /* CONFIG_SYS_INIT_L2_ADDR */
341 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
345 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
346 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
348 /* invalidate the L2 cache */
349 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
350 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
353 #ifdef CONFIG_SYS_CACHE_STASHING
354 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
355 mtspr(SPRN_L2CSR1, (32 + 1));
358 /* enable the cache */
359 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
361 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
362 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
364 printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
373 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
378 #if defined(CONFIG_SYS_HAS_SERDES)
379 /* needs to be in ram since code uses global static vars */
383 #if defined(CONFIG_MP)
387 #ifdef CONFIG_SYS_LBC_LCRR
389 * Modify the CLKDIV field of LCRR register to improve the writing
390 * speed for NOR flash.
392 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
393 __raw_readl(&lbc->lcrr);
400 extern void setup_ivors(void);
402 void arch_preboot_os(void)
407 * We are changing interrupt offsets and are about to boot the OS so
408 * we need to make sure we disable all async interrupts. EE is already
409 * disabled by the time we get called.
412 msr &= ~(MSR_ME|MSR_CE|MSR_DE);
418 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
419 int sata_initialize(void)
421 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
422 return __sata_initialize();