1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
21 #include <fsl_esdhc.h>
22 #include <asm/cache.h>
23 #include <asm/global_data.h>
27 #include <asm/fsl_law.h>
28 #include <asm/fsl_lbc.h>
30 #include <asm/processor.h>
31 #include <fsl_ddr_sdram.h>
33 #include <linux/delay.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 * Default board reset function
45 void board_reset(void) __attribute__((weak, alias("__board_reset")));
54 char buf1[32], buf2[32];
55 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
56 ccsr_gur_t __iomem *gur =
57 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
61 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
62 * mode. Previous platform use ddr ratio to do the same. This
63 * information is only for display here.
65 #ifdef CONFIG_FSL_CORENET
66 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
67 u32 ddr_sync = 0; /* only async mode is supported */
69 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
70 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
71 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
72 #else /* CONFIG_FSL_CORENET */
73 #ifdef CONFIG_DDR_CLK_FREQ
74 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
75 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
78 #endif /* CONFIG_DDR_CLK_FREQ */
79 #endif /* CONFIG_FSL_CORENET */
81 unsigned int i, core, nr_cores = cpu_numcores();
82 u32 mask = cpu_mask();
84 #ifdef CONFIG_HETROGENOUS_CLUSTERS
85 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
86 u32 dsp_mask = cpu_dsp_mask();
93 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
94 if (SVR_SOC_VER(svr) == SVR_T4080) {
96 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
98 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
99 FSL_CORENET_DEVDISR2_DTSEC1_9);
100 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
101 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
103 /* It needs SW to disable core4~7 as HW design sake on T4080 */
104 for (i = 4; i < 8; i++)
107 /* request core4~7 into PH20 state, prior to entering PCL10
108 * state, all cores in cluster should be placed in PH20 state.
110 setbits_be32(&rcpm->pcph20setr, 0xf0);
112 /* put the 2nd cluster into PCL10 state */
113 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
117 if (cpu_numcores() > 1) {
119 puts("Unicore software on multiprocessor system!!\n"
120 "To enable mutlticore build define CONFIG_MP\n");
122 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
123 printf("CPU%d: ", pic->whoami);
131 if (IS_E_PROCESSOR(svr))
134 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
138 major = PVR_MAJ(pvr);
139 minor = PVR_MIN(pvr);
143 case PVR_VER_E500_V1:
144 case PVR_VER_E500_V2:
161 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
163 if (nr_cores > CONFIG_MAX_CPUS) {
164 panic("\nUnexpected number of cores: %d, max is %d\n",
165 nr_cores, CONFIG_MAX_CPUS);
168 get_sys_info(&sysinfo);
170 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
171 if (sysinfo.diff_sysclk == 1)
172 puts("Single Source Clock Configuration\n");
175 puts("Clock Configuration:");
176 for_each_cpu(i, core, nr_cores, mask) {
179 printf("CPU%d:%-4s MHz, ", core,
180 strmhz(buf1, sysinfo.freq_processor[core]));
183 #ifdef CONFIG_HETROGENOUS_CLUSTERS
184 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
187 printf("DSP CPU%d:%-4s MHz, ", j,
188 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
192 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
195 #ifdef CONFIG_FSL_CORENET
197 printf(" DDR:%-4s MHz (%s MT/s data rate) "
199 strmhz(buf1, sysinfo.freq_ddrbus/2),
200 strmhz(buf2, sysinfo.freq_ddrbus));
202 printf(" DDR:%-4s MHz (%s MT/s data rate) "
204 strmhz(buf1, sysinfo.freq_ddrbus/2),
205 strmhz(buf2, sysinfo.freq_ddrbus));
210 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
211 strmhz(buf1, sysinfo.freq_ddrbus/2),
212 strmhz(buf2, sysinfo.freq_ddrbus));
215 printf(" DDR:%-4s MHz (%s MT/s data rate) "
217 strmhz(buf1, sysinfo.freq_ddrbus/2),
218 strmhz(buf2, sysinfo.freq_ddrbus));
221 printf(" DDR:%-4s MHz (%s MT/s data rate) "
223 strmhz(buf1, sysinfo.freq_ddrbus/2),
224 strmhz(buf2, sysinfo.freq_ddrbus));
229 #if defined(CONFIG_FSL_LBC)
230 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
231 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
233 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
234 sysinfo.freq_localbus);
238 #if defined(CONFIG_FSL_IFC)
239 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
243 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
247 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
250 #if defined(CONFIG_SYS_CPRI)
252 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
255 #if defined(CONFIG_SYS_MAPLE)
257 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
258 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
259 printf("MAPLE-eTVPE:%-4s MHz\n",
260 strmhz(buf1, sysinfo.freq_maple_etvpe));
263 #ifdef CONFIG_SYS_DPAA_FMAN
264 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
265 printf(" FMAN%d: %s MHz\n", i + 1,
266 strmhz(buf1, sysinfo.freq_fman[i]));
270 #ifdef CONFIG_SYS_DPAA_QBMAN
271 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
274 #ifdef CONFIG_SYS_DPAA_PME
275 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
278 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
280 #ifdef CONFIG_FSL_CORENET
281 /* Display the RCW, so that no one gets confused as to what RCW
282 * we're actually using for this boot.
284 puts("Reset Configuration Word (RCW):");
285 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
286 u32 rcw = in_be32(&gur->rcwsr[i]);
289 printf("\n %08x:", i * 4);
290 printf(" %08x", rcw);
299 /* ------------------------------------------------------------------------- */
301 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
303 /* Everything after the first generation of PQ3 parts has RSTCR */
304 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
305 defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
306 unsigned long val, msr;
309 * Initiate hard reset in debug control register DBCR0
310 * Make sure MSR[DE] = 1. This only resets the core.
320 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
322 /* Attempt board-specific reset */
325 /* Next try asserting HRESET_REQ */
326 out_be32(&gur->rstcr, 0x2);
335 * Get timebase clock frequency
337 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
338 #define CONFIG_SYS_FSL_TBCLK_DIV 8
340 __weak unsigned long get_tbclk(void)
342 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
344 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
348 #if defined(CONFIG_WATCHDOG)
349 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
351 init_85xx_watchdog(void)
353 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
354 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
358 reset_85xx_watchdog(void)
361 * Clear TSR(WIS) bit by writing 1
363 mtspr(SPRN_TSR, TSR_WIS);
369 int re_enable = disable_interrupts();
371 reset_85xx_watchdog();
375 #endif /* CONFIG_WATCHDOG */
378 * Initializes on-chip MMC controllers.
379 * to override, implement board_mmc_init()
381 int cpu_mmc_init(struct bd_info *bis)
383 #ifdef CONFIG_FSL_ESDHC
384 return fsl_esdhc_mmc_init(bis);
391 * Print out the state of various machine registers.
392 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
393 * parameters for IFC and TLBs
395 void print_reginfo(void)
398 #ifdef CONFIG_FSL_LAW
401 #if defined(CONFIG_FSL_LBC)
404 #ifdef CONFIG_FSL_IFC
410 /* Common ddr init for non-corenet fsl 85xx platforms */
411 #ifndef CONFIG_FSL_CORENET
412 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
413 !defined(CONFIG_SYS_INIT_L2_ADDR)
416 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
417 defined(CONFIG_ARCH_QEMU_E500)
418 gd->ram_size = fsl_ddr_sdram_size();
420 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
425 #else /* CONFIG_SYS_RAMBOOT */
428 phys_size_t dram_size = 0;
430 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
432 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
437 * Work around to stabilize DDR DLL
439 out_be32(&gur->ddrdllcr, 0x81000000);
440 asm("sync;isync;msync");
442 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
443 setbits_be32(&gur->devdisr, 0x00010000);
444 for (i = 0; i < x; i++)
446 clrbits_be32(&gur->devdisr, 0x00010000);
452 #if defined(CONFIG_SPD_EEPROM) || \
453 defined(CONFIG_DDR_SPD) || \
454 defined(CONFIG_SYS_DDR_RAW_TIMING)
455 dram_size = fsl_ddr_sdram();
457 dram_size = fixed_sdram();
459 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
460 dram_size *= 0x100000;
462 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
464 * Initialize and enable DDR ECC.
466 ddr_enable_ecc(dram_size);
469 #if defined(CONFIG_FSL_LBC)
470 /* Some boards also have sdram on the lbc */
475 gd->ram_size = dram_size;
479 #endif /* CONFIG_SYS_RAMBOOT */
482 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
484 /* Board-specific functions defined in each board's ddr.c */
485 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
486 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
487 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
490 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
492 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
494 static void dump_spd_ddr_reg(void)
499 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
501 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
503 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
504 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
506 puts("SPD data of all dimms (zero value is omitted)...\n");
509 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
510 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
511 printf("Dimm%d ", k++);
514 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
516 printf("%3d (0x%02x) ", k, k);
517 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
518 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
519 p_8 = (u8 *) &spd[i][j];
521 printf("0x%02x ", p_8[k]);
533 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
536 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
538 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
540 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
543 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
545 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
548 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
550 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
554 printf("%s unexpected controller number = %u\n",
559 printf("DDR registers dump for all controllers "
560 "(zero value is omitted)...\n");
561 puts("Offset (hex) ");
562 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
563 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
565 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
567 printf("%6d (0x%04x)", k * 4, k * 4);
568 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
569 p_32 = (u32 *) ddr[i];
571 printf(" 0x%08x", p_32[k]);
584 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
585 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
587 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
589 u32 tsize, valid, ptr;
592 clear_ddr_tlbs_phys(p_addr, size>>20);
594 /* Setup new tlb to cover the physical address */
595 setup_ddr_tlbs_phys(p_addr, size>>20);
598 ddr_esel = find_tlb_idx((void *)ptr, 1);
599 if (ddr_esel != -1) {
600 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
602 printf("TLB error in function %s\n", __func__);
610 * slide the testing window up to test another area
611 * for 32_bit system, the maximum testable memory is limited to
612 * CONFIG_MAX_MEM_MAPPED
614 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
616 phys_addr_t test_cap, p_addr;
617 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
619 #if !defined(CONFIG_PHYS_64BIT) || \
620 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
621 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
624 test_cap = gd->ram_size;
626 p_addr = (*vstart) + (*size) + (*phys_offset);
627 if (p_addr < test_cap - 1) {
628 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
629 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
631 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
632 *size = (u32) p_size;
633 printf("Testing 0x%08llx - 0x%08llx\n",
634 (u64)(*vstart) + (*phys_offset),
635 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
642 /* initialization for testing area */
643 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
645 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
647 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
648 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
651 #if !defined(CONFIG_PHYS_64BIT) || \
652 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
653 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
654 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
655 puts("Cannot test more than ");
656 print_size(CONFIG_MAX_MEM_MAPPED,
657 " without proper 36BIT support.\n");
660 printf("Testing 0x%08llx - 0x%08llx\n",
661 (u64)(*vstart) + (*phys_offset),
662 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
667 /* invalid TLBs for DDR and remap as normal after testing */
668 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
671 u32 tsize, valid, ptr;
675 /* disable the TLBs for this testing */
678 while (ptr < (*vstart) + (*size)) {
679 ddr_esel = find_tlb_idx((void *)ptr, 1);
680 if (ddr_esel != -1) {
681 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
682 disable_tlb(ddr_esel);
684 ptr += TSIZE_TO_BYTES(tsize);
688 setup_ddr_tlbs(gd->ram_size>>20);
694 void arch_memory_failure_handle(void)