2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 DECLARE_GLOBAL_DATA_PTR;
46 char buf1[32], buf2[32];
47 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
49 #endif /* CONFIG_FSL_CORENET */
50 #ifdef CONFIG_DDR_CLK_FREQ
51 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
52 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
54 #ifdef CONFIG_FSL_CORENET
55 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
56 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
59 #endif /* CONFIG_FSL_CORENET */
60 #endif /* CONFIG_DDR_CLK_FREQ */
66 major &= 0x7; /* the msb of this nibble is a mfg code */
70 if (cpu_numcores() > 1) {
72 puts("Unicore software on multiprocessor system!!\n"
73 "To enable mutlticore build define CONFIG_MP\n");
75 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
76 printf("CPU%d: ", pic->whoami);
84 if (IS_E_PROCESSOR(svr))
87 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
97 case PVR_FAM(PVR_85xx):
105 if (PVR_MEM(pvr) == 0x03)
108 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
110 get_sys_info(&sysinfo);
112 puts("Clock Configuration:");
113 for (i = 0; i < cpu_numcores(); i++) {
116 printf("CPU%d:%-4s MHz, ",
117 i,strmhz(buf1, sysinfo.freqProcessor[i]));
119 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
121 #ifdef CONFIG_FSL_CORENET
123 printf(" DDR:%-4s MHz (%s MT/s data rate) "
125 strmhz(buf1, sysinfo.freqDDRBus/2),
126 strmhz(buf2, sysinfo.freqDDRBus));
128 printf(" DDR:%-4s MHz (%s MT/s data rate) "
130 strmhz(buf1, sysinfo.freqDDRBus/2),
131 strmhz(buf2, sysinfo.freqDDRBus));
136 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
137 strmhz(buf1, sysinfo.freqDDRBus/2),
138 strmhz(buf2, sysinfo.freqDDRBus));
141 printf(" DDR:%-4s MHz (%s MT/s data rate) "
143 strmhz(buf1, sysinfo.freqDDRBus/2),
144 strmhz(buf2, sysinfo.freqDDRBus));
147 printf(" DDR:%-4s MHz (%s MT/s data rate) "
149 strmhz(buf1, sysinfo.freqDDRBus/2),
150 strmhz(buf2, sysinfo.freqDDRBus));
155 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
156 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
158 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
159 sysinfo.freqLocalBus);
163 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
167 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
170 #ifdef CONFIG_SYS_DPAA_FMAN
171 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
172 printf(" FMAN%d: %s MHz\n", i,
173 strmhz(buf1, sysinfo.freqFMan[i]));
177 #ifdef CONFIG_SYS_DPAA_PME
178 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
181 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
187 /* ------------------------------------------------------------------------- */
189 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
191 /* Everything after the first generation of PQ3 parts has RSTCR */
192 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
193 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
194 unsigned long val, msr;
197 * Initiate hard reset in debug control register DBCR0
198 * Make sure MSR[DE] = 1. This only resets the core.
208 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
209 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
218 * Get timebase clock frequency
220 unsigned long get_tbclk (void)
222 #ifdef CONFIG_FSL_CORENET
223 return (gd->bus_clk + 8) / 16;
225 return (gd->bus_clk + 4UL)/8UL;
230 #if defined(CONFIG_WATCHDOG)
234 int re_enable = disable_interrupts();
235 reset_85xx_watchdog();
236 if (re_enable) enable_interrupts();
240 reset_85xx_watchdog(void)
243 * Clear TSR(WIS) bit by writing 1
246 val = mfspr(SPRN_TSR);
248 mtspr(SPRN_TSR, val);
250 #endif /* CONFIG_WATCHDOG */
253 * Configures a UPM. The function requires the respective MxMR to be set
254 * before calling this function. "size" is the number or entries, not a sizeof.
256 void upmconfig (uint upm, uint * table, uint size)
258 int i, mdr, mad, old_mad = 0;
260 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
261 volatile u32 *brp,*orp;
262 volatile u8* dummy = NULL;
268 upmmask = BR_MS_UPMA;
272 upmmask = BR_MS_UPMB;
276 upmmask = BR_MS_UPMC;
279 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
283 /* Find the address for the dummy write transaction */
284 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
285 i++, brp += 2, orp += 2) {
287 /* Look for a valid BR with selected UPM */
288 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
289 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
295 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
299 for (i = 0; i < size; i++) {
301 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
303 out_be32(&lbc->mdr, table[i]);
305 mdr = in_be32(&lbc->mdr);
307 *(volatile u8 *)dummy = 0;
310 mad = in_be32(mxmr) & MxMR_MAD_MSK;
311 } while (mad <= old_mad && !(!mad && i == (size-1)));
314 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
318 * Initializes on-chip MMC controllers.
319 * to override, implement board_mmc_init()
321 int cpu_mmc_init(bd_t *bis)
323 #ifdef CONFIG_FSL_ESDHC
324 return fsl_esdhc_mmc_init(bis);