1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
21 #include <fsl_esdhc.h>
22 #include <asm/cache.h>
26 #include <asm/fsl_law.h>
27 #include <asm/fsl_lbc.h>
29 #include <asm/processor.h>
30 #include <fsl_ddr_sdram.h>
32 #include <linux/delay.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 * Default board reset function
44 void board_reset(void) __attribute__((weak, alias("__board_reset")));
53 char buf1[32], buf2[32];
54 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
55 ccsr_gur_t __iomem *gur =
56 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
60 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
61 * mode. Previous platform use ddr ratio to do the same. This
62 * information is only for display here.
64 #ifdef CONFIG_FSL_CORENET
65 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
66 u32 ddr_sync = 0; /* only async mode is supported */
68 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
69 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
70 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
71 #else /* CONFIG_FSL_CORENET */
72 #ifdef CONFIG_DDR_CLK_FREQ
73 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
74 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
77 #endif /* CONFIG_DDR_CLK_FREQ */
78 #endif /* CONFIG_FSL_CORENET */
80 unsigned int i, core, nr_cores = cpu_numcores();
81 u32 mask = cpu_mask();
83 #ifdef CONFIG_HETROGENOUS_CLUSTERS
84 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
85 u32 dsp_mask = cpu_dsp_mask();
92 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
93 if (SVR_SOC_VER(svr) == SVR_T4080) {
95 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
97 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
98 FSL_CORENET_DEVDISR2_DTSEC1_9);
99 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
100 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
102 /* It needs SW to disable core4~7 as HW design sake on T4080 */
103 for (i = 4; i < 8; i++)
106 /* request core4~7 into PH20 state, prior to entering PCL10
107 * state, all cores in cluster should be placed in PH20 state.
109 setbits_be32(&rcpm->pcph20setr, 0xf0);
111 /* put the 2nd cluster into PCL10 state */
112 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
116 if (cpu_numcores() > 1) {
118 puts("Unicore software on multiprocessor system!!\n"
119 "To enable mutlticore build define CONFIG_MP\n");
121 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
122 printf("CPU%d: ", pic->whoami);
130 if (IS_E_PROCESSOR(svr))
133 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
137 major = PVR_MAJ(pvr);
138 minor = PVR_MIN(pvr);
142 case PVR_VER_E500_V1:
143 case PVR_VER_E500_V2:
160 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
162 if (nr_cores > CONFIG_MAX_CPUS) {
163 panic("\nUnexpected number of cores: %d, max is %d\n",
164 nr_cores, CONFIG_MAX_CPUS);
167 get_sys_info(&sysinfo);
169 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
170 if (sysinfo.diff_sysclk == 1)
171 puts("Single Source Clock Configuration\n");
174 puts("Clock Configuration:");
175 for_each_cpu(i, core, nr_cores, mask) {
178 printf("CPU%d:%-4s MHz, ", core,
179 strmhz(buf1, sysinfo.freq_processor[core]));
182 #ifdef CONFIG_HETROGENOUS_CLUSTERS
183 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
186 printf("DSP CPU%d:%-4s MHz, ", j,
187 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
191 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
194 #ifdef CONFIG_FSL_CORENET
196 printf(" DDR:%-4s MHz (%s MT/s data rate) "
198 strmhz(buf1, sysinfo.freq_ddrbus/2),
199 strmhz(buf2, sysinfo.freq_ddrbus));
201 printf(" DDR:%-4s MHz (%s MT/s data rate) "
203 strmhz(buf1, sysinfo.freq_ddrbus/2),
204 strmhz(buf2, sysinfo.freq_ddrbus));
209 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
210 strmhz(buf1, sysinfo.freq_ddrbus/2),
211 strmhz(buf2, sysinfo.freq_ddrbus));
214 printf(" DDR:%-4s MHz (%s MT/s data rate) "
216 strmhz(buf1, sysinfo.freq_ddrbus/2),
217 strmhz(buf2, sysinfo.freq_ddrbus));
220 printf(" DDR:%-4s MHz (%s MT/s data rate) "
222 strmhz(buf1, sysinfo.freq_ddrbus/2),
223 strmhz(buf2, sysinfo.freq_ddrbus));
228 #if defined(CONFIG_FSL_LBC)
229 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
230 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
232 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
233 sysinfo.freq_localbus);
237 #if defined(CONFIG_FSL_IFC)
238 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
242 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
246 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
249 #if defined(CONFIG_SYS_CPRI)
251 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
254 #if defined(CONFIG_SYS_MAPLE)
256 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
257 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
258 printf("MAPLE-eTVPE:%-4s MHz\n",
259 strmhz(buf1, sysinfo.freq_maple_etvpe));
262 #ifdef CONFIG_SYS_DPAA_FMAN
263 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
264 printf(" FMAN%d: %s MHz\n", i + 1,
265 strmhz(buf1, sysinfo.freq_fman[i]));
269 #ifdef CONFIG_SYS_DPAA_QBMAN
270 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
273 #ifdef CONFIG_SYS_DPAA_PME
274 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
277 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
279 #ifdef CONFIG_FSL_CORENET
280 /* Display the RCW, so that no one gets confused as to what RCW
281 * we're actually using for this boot.
283 puts("Reset Configuration Word (RCW):");
284 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
285 u32 rcw = in_be32(&gur->rcwsr[i]);
288 printf("\n %08x:", i * 4);
289 printf(" %08x", rcw);
298 /* ------------------------------------------------------------------------- */
300 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
302 /* Everything after the first generation of PQ3 parts has RSTCR */
303 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
304 defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
305 unsigned long val, msr;
308 * Initiate hard reset in debug control register DBCR0
309 * Make sure MSR[DE] = 1. This only resets the core.
319 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
321 /* Attempt board-specific reset */
324 /* Next try asserting HRESET_REQ */
325 out_be32(&gur->rstcr, 0x2);
334 * Get timebase clock frequency
336 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
337 #define CONFIG_SYS_FSL_TBCLK_DIV 8
339 __weak unsigned long get_tbclk(void)
341 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
343 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
347 #if defined(CONFIG_WATCHDOG)
348 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
350 init_85xx_watchdog(void)
352 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
353 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
357 reset_85xx_watchdog(void)
360 * Clear TSR(WIS) bit by writing 1
362 mtspr(SPRN_TSR, TSR_WIS);
368 int re_enable = disable_interrupts();
370 reset_85xx_watchdog();
374 #endif /* CONFIG_WATCHDOG */
377 * Initializes on-chip MMC controllers.
378 * to override, implement board_mmc_init()
380 int cpu_mmc_init(bd_t *bis)
382 #ifdef CONFIG_FSL_ESDHC
383 return fsl_esdhc_mmc_init(bis);
390 * Print out the state of various machine registers.
391 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
392 * parameters for IFC and TLBs
394 void print_reginfo(void)
398 #if defined(CONFIG_FSL_LBC)
401 #ifdef CONFIG_FSL_IFC
407 /* Common ddr init for non-corenet fsl 85xx platforms */
408 #ifndef CONFIG_FSL_CORENET
409 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
410 !defined(CONFIG_SYS_INIT_L2_ADDR)
413 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
414 defined(CONFIG_ARCH_QEMU_E500)
415 gd->ram_size = fsl_ddr_sdram_size();
417 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
422 #else /* CONFIG_SYS_RAMBOOT */
425 phys_size_t dram_size = 0;
427 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
429 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
434 * Work around to stabilize DDR DLL
436 out_be32(&gur->ddrdllcr, 0x81000000);
437 asm("sync;isync;msync");
439 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
440 setbits_be32(&gur->devdisr, 0x00010000);
441 for (i = 0; i < x; i++)
443 clrbits_be32(&gur->devdisr, 0x00010000);
449 #if defined(CONFIG_SPD_EEPROM) || \
450 defined(CONFIG_DDR_SPD) || \
451 defined(CONFIG_SYS_DDR_RAW_TIMING)
452 dram_size = fsl_ddr_sdram();
454 dram_size = fixed_sdram();
456 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
457 dram_size *= 0x100000;
459 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
461 * Initialize and enable DDR ECC.
463 ddr_enable_ecc(dram_size);
466 #if defined(CONFIG_FSL_LBC)
467 /* Some boards also have sdram on the lbc */
472 gd->ram_size = dram_size;
476 #endif /* CONFIG_SYS_RAMBOOT */
479 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
481 /* Board-specific functions defined in each board's ddr.c */
482 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
483 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
484 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
487 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
489 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
491 static void dump_spd_ddr_reg(void)
496 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
498 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
500 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
501 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
503 puts("SPD data of all dimms (zero value is omitted)...\n");
506 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
507 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
508 printf("Dimm%d ", k++);
511 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
513 printf("%3d (0x%02x) ", k, k);
514 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
515 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
516 p_8 = (u8 *) &spd[i][j];
518 printf("0x%02x ", p_8[k]);
530 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
533 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
535 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
537 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
540 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
542 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
545 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
547 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
551 printf("%s unexpected controller number = %u\n",
556 printf("DDR registers dump for all controllers "
557 "(zero value is omitted)...\n");
558 puts("Offset (hex) ");
559 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
560 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
562 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
564 printf("%6d (0x%04x)", k * 4, k * 4);
565 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
566 p_32 = (u32 *) ddr[i];
568 printf(" 0x%08x", p_32[k]);
581 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
582 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
584 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
586 u32 tsize, valid, ptr;
589 clear_ddr_tlbs_phys(p_addr, size>>20);
591 /* Setup new tlb to cover the physical address */
592 setup_ddr_tlbs_phys(p_addr, size>>20);
595 ddr_esel = find_tlb_idx((void *)ptr, 1);
596 if (ddr_esel != -1) {
597 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
599 printf("TLB error in function %s\n", __func__);
607 * slide the testing window up to test another area
608 * for 32_bit system, the maximum testable memory is limited to
609 * CONFIG_MAX_MEM_MAPPED
611 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
613 phys_addr_t test_cap, p_addr;
614 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
616 #if !defined(CONFIG_PHYS_64BIT) || \
617 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
618 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
621 test_cap = gd->ram_size;
623 p_addr = (*vstart) + (*size) + (*phys_offset);
624 if (p_addr < test_cap - 1) {
625 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
626 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
628 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
629 *size = (u32) p_size;
630 printf("Testing 0x%08llx - 0x%08llx\n",
631 (u64)(*vstart) + (*phys_offset),
632 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
639 /* initialization for testing area */
640 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
642 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
644 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
645 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
648 #if !defined(CONFIG_PHYS_64BIT) || \
649 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
650 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
651 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
652 puts("Cannot test more than ");
653 print_size(CONFIG_MAX_MEM_MAPPED,
654 " without proper 36BIT support.\n");
657 printf("Testing 0x%08llx - 0x%08llx\n",
658 (u64)(*vstart) + (*phys_offset),
659 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
664 /* invalid TLBs for DDR and remap as normal after testing */
665 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
668 u32 tsize, valid, ptr;
672 /* disable the TLBs for this testing */
675 while (ptr < (*vstart) + (*size)) {
676 ddr_esel = find_tlb_idx((void *)ptr, 1);
677 if (ddr_esel != -1) {
678 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
679 disable_tlb(ddr_esel);
681 ptr += TSIZE_TO_BYTES(tsize);
685 setup_ddr_tlbs(gd->ram_size>>20);
691 void arch_memory_failure_handle(void)