1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
14 #include <clock_legacy.h>
22 #include <fsl_esdhc.h>
23 #include <asm/cache.h>
24 #include <asm/global_data.h>
28 #include <asm/fsl_law.h>
29 #include <asm/fsl_lbc.h>
31 #include <asm/processor.h>
32 #include <fsl_ddr_sdram.h>
34 #include <linux/delay.h>
36 DECLARE_GLOBAL_DATA_PTR;
39 * Default board reset function
46 void board_reset(void) __attribute__((weak, alias("__board_reset")));
55 char buf1[32], buf2[32];
56 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
57 defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
58 ccsr_gur_t __iomem *gur =
59 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
63 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
64 * mode. Previous platform use ddr ratio to do the same. This
65 * information is only for display here.
67 #ifdef CONFIG_FSL_CORENET
68 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
69 u32 ddr_sync = 0; /* only async mode is supported */
71 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
72 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
73 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
74 #else /* CONFIG_FSL_CORENET */
75 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
76 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
77 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
80 #endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
81 #endif /* CONFIG_FSL_CORENET */
83 unsigned int i, core, nr_cores = cpu_numcores();
84 u32 mask = cpu_mask();
86 #ifdef CONFIG_HETROGENOUS_CLUSTERS
87 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
88 u32 dsp_mask = cpu_dsp_mask();
95 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
96 if (SVR_SOC_VER(svr) == SVR_T4080) {
98 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
100 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
101 FSL_CORENET_DEVDISR2_DTSEC1_9);
102 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
103 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
105 /* It needs SW to disable core4~7 as HW design sake on T4080 */
106 for (i = 4; i < 8; i++)
109 /* request core4~7 into PH20 state, prior to entering PCL10
110 * state, all cores in cluster should be placed in PH20 state.
112 setbits_be32(&rcpm->pcph20setr, 0xf0);
114 /* put the 2nd cluster into PCL10 state */
115 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
119 if (cpu_numcores() > 1) {
121 puts("Unicore software on multiprocessor system!!\n"
122 "To enable mutlticore build define CONFIG_MP\n");
124 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
125 printf("CPU%d: ", pic->whoami);
133 if (IS_E_PROCESSOR(svr))
136 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
140 major = PVR_MAJ(pvr);
141 minor = PVR_MIN(pvr);
145 case PVR_VER_E500_V1:
146 case PVR_VER_E500_V2:
163 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
165 if (nr_cores > CONFIG_MAX_CPUS) {
166 panic("\nUnexpected number of cores: %d, max is %d\n",
167 nr_cores, CONFIG_MAX_CPUS);
170 get_sys_info(&sysinfo);
172 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
173 if (sysinfo.diff_sysclk == 1)
174 puts("Single Source Clock Configuration\n");
177 puts("Clock Configuration:");
178 for_each_cpu(i, core, nr_cores, mask) {
181 printf("CPU%d:%-4s MHz, ", core,
182 strmhz(buf1, sysinfo.freq_processor[core]));
185 #ifdef CONFIG_HETROGENOUS_CLUSTERS
186 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
189 printf("DSP CPU%d:%-4s MHz, ", j,
190 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
194 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
197 #ifdef CONFIG_FSL_CORENET
199 printf(" DDR:%-4s MHz (%s MT/s data rate) "
201 strmhz(buf1, sysinfo.freq_ddrbus/2),
202 strmhz(buf2, sysinfo.freq_ddrbus));
204 printf(" DDR:%-4s MHz (%s MT/s data rate) "
206 strmhz(buf1, sysinfo.freq_ddrbus/2),
207 strmhz(buf2, sysinfo.freq_ddrbus));
212 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
213 strmhz(buf1, sysinfo.freq_ddrbus/2),
214 strmhz(buf2, sysinfo.freq_ddrbus));
217 printf(" DDR:%-4s MHz (%s MT/s data rate) "
219 strmhz(buf1, sysinfo.freq_ddrbus/2),
220 strmhz(buf2, sysinfo.freq_ddrbus));
223 printf(" DDR:%-4s MHz (%s MT/s data rate) "
225 strmhz(buf1, sysinfo.freq_ddrbus/2),
226 strmhz(buf2, sysinfo.freq_ddrbus));
231 #if defined(CONFIG_FSL_LBC)
232 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
233 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
235 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
236 sysinfo.freq_localbus);
240 #if defined(CONFIG_FSL_IFC)
241 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
245 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
249 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
252 #if defined(CONFIG_SYS_CPRI)
254 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
257 #if defined(CONFIG_SYS_MAPLE)
259 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
260 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
261 printf("MAPLE-eTVPE:%-4s MHz\n",
262 strmhz(buf1, sysinfo.freq_maple_etvpe));
265 #ifdef CONFIG_SYS_DPAA_FMAN
266 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
267 printf(" FMAN%d: %s MHz\n", i + 1,
268 strmhz(buf1, sysinfo.freq_fman[i]));
272 #ifdef CONFIG_SYS_DPAA_QBMAN
273 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
276 #ifdef CONFIG_SYS_DPAA_PME
277 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
280 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
282 #ifdef CONFIG_FSL_CORENET
283 /* Display the RCW, so that no one gets confused as to what RCW
284 * we're actually using for this boot.
286 puts("Reset Configuration Word (RCW):");
287 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
288 u32 rcw = in_be32(&gur->rcwsr[i]);
291 printf("\n %08x:", i * 4);
292 printf(" %08x", rcw);
301 /* ------------------------------------------------------------------------- */
303 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
305 /* Everything after the first generation of PQ3 parts has RSTCR */
306 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
307 unsigned long val, msr;
310 * Initiate hard reset in debug control register DBCR0
311 * Make sure MSR[DE] = 1. This only resets the core.
321 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
323 /* Attempt board-specific reset */
326 /* Next try asserting HRESET_REQ */
327 out_be32(&gur->rstcr, 0x2);
336 * Get timebase clock frequency
338 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
339 #define CONFIG_SYS_FSL_TBCLK_DIV 8
341 __weak unsigned long get_tbclk(void)
343 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
345 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
349 #if defined(CONFIG_WATCHDOG)
350 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
352 init_85xx_watchdog(void)
354 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
355 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
359 reset_85xx_watchdog(void)
362 * Clear TSR(WIS) bit by writing 1
364 mtspr(SPRN_TSR, TSR_WIS);
370 int re_enable = disable_interrupts();
372 reset_85xx_watchdog();
376 #endif /* CONFIG_WATCHDOG */
379 * Initializes on-chip MMC controllers.
380 * to override, implement board_mmc_init()
382 int cpu_mmc_init(struct bd_info *bis)
384 #ifdef CONFIG_FSL_ESDHC
385 return fsl_esdhc_mmc_init(bis);
392 * Print out the state of various machine registers.
393 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
394 * parameters for IFC and TLBs
396 void print_reginfo(void)
399 #ifdef CONFIG_FSL_LAW
402 #if defined(CONFIG_FSL_LBC)
405 #ifdef CONFIG_FSL_IFC
411 /* Common ddr init for non-corenet fsl 85xx platforms */
412 #ifndef CONFIG_FSL_CORENET
413 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
414 !defined(CONFIG_SYS_INIT_L2_ADDR)
417 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
418 defined(CONFIG_ARCH_QEMU_E500)
419 gd->ram_size = fsl_ddr_sdram_size();
421 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
426 #else /* CONFIG_SYS_RAMBOOT */
429 phys_size_t dram_size = 0;
431 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
433 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
438 * Work around to stabilize DDR DLL
440 out_be32(&gur->ddrdllcr, 0x81000000);
441 asm("sync;isync;msync");
443 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
444 setbits_be32(&gur->devdisr, 0x00010000);
445 for (i = 0; i < x; i++)
447 clrbits_be32(&gur->devdisr, 0x00010000);
453 #if defined(CONFIG_SPD_EEPROM) || \
454 defined(CONFIG_DDR_SPD) || \
455 defined(CONFIG_SYS_DDR_RAW_TIMING)
456 dram_size = fsl_ddr_sdram();
458 dram_size = fixed_sdram();
460 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
461 dram_size *= 0x100000;
463 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
465 * Initialize and enable DDR ECC.
467 ddr_enable_ecc(dram_size);
470 #if defined(CONFIG_FSL_LBC)
471 /* Some boards also have sdram on the lbc */
476 gd->ram_size = dram_size;
480 #endif /* CONFIG_SYS_RAMBOOT */
483 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
485 /* Board-specific functions defined in each board's ddr.c */
486 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
487 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
488 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
491 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
493 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
495 static void dump_spd_ddr_reg(void)
500 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
502 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
504 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
505 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
507 puts("SPD data of all dimms (zero value is omitted)...\n");
510 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
511 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
512 printf("Dimm%d ", k++);
515 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
517 printf("%3d (0x%02x) ", k, k);
518 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
519 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
520 p_8 = (u8 *) &spd[i][j];
522 printf("0x%02x ", p_8[k]);
534 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
537 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
539 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
541 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
544 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
546 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
549 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
551 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
555 printf("%s unexpected controller number = %u\n",
560 printf("DDR registers dump for all controllers "
561 "(zero value is omitted)...\n");
562 puts("Offset (hex) ");
563 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
564 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
566 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
568 printf("%6d (0x%04x)", k * 4, k * 4);
569 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
570 p_32 = (u32 *) ddr[i];
572 printf(" 0x%08x", p_32[k]);
585 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
586 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
588 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
590 u32 tsize, valid, ptr;
593 clear_ddr_tlbs_phys(p_addr, size>>20);
595 /* Setup new tlb to cover the physical address */
596 setup_ddr_tlbs_phys(p_addr, size>>20);
599 ddr_esel = find_tlb_idx((void *)ptr, 1);
600 if (ddr_esel != -1) {
601 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
603 printf("TLB error in function %s\n", __func__);
611 * slide the testing window up to test another area
612 * for 32_bit system, the maximum testable memory is limited to
613 * CONFIG_MAX_MEM_MAPPED
615 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
617 phys_addr_t test_cap, p_addr;
618 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
620 #if !defined(CONFIG_PHYS_64BIT) || \
621 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
622 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
625 test_cap = gd->ram_size;
627 p_addr = (*vstart) + (*size) + (*phys_offset);
628 if (p_addr < test_cap - 1) {
629 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
630 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
632 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
633 *size = (u32) p_size;
634 printf("Testing 0x%08llx - 0x%08llx\n",
635 (u64)(*vstart) + (*phys_offset),
636 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
643 /* initialization for testing area */
644 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
646 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
648 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
649 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
652 #if !defined(CONFIG_PHYS_64BIT) || \
653 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
654 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
655 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
656 puts("Cannot test more than ");
657 print_size(CONFIG_MAX_MEM_MAPPED,
658 " without proper 36BIT support.\n");
661 printf("Testing 0x%08llx - 0x%08llx\n",
662 (u64)(*vstart) + (*phys_offset),
663 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
668 /* invalid TLBs for DDR and remap as normal after testing */
669 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
672 u32 tsize, valid, ptr;
676 /* disable the TLBs for this testing */
679 while (ptr < (*vstart) + (*size)) {
680 ddr_esel = find_tlb_idx((void *)ptr, 1);
681 if (ddr_esel != -1) {
682 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
683 disable_tlb(ddr_esel);
685 ptr += TSIZE_TO_BYTES(tsize);
689 setup_ddr_tlbs(gd->ram_size>>20);
695 void arch_memory_failure_handle(void)