2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 #include <asm/fsl_ifc.h>
37 #include <asm/fsl_law.h>
38 #include <asm/fsl_lbc.h>
40 #include <asm/processor.h>
41 #include <asm/fsl_ddr_sdram.h>
43 DECLARE_GLOBAL_DATA_PTR;
53 char buf1[32], buf2[32];
54 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
55 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
56 #endif /* CONFIG_FSL_CORENET */
57 #ifdef CONFIG_DDR_CLK_FREQ
58 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
59 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
61 #ifdef CONFIG_FSL_CORENET
62 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
63 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
66 #endif /* CONFIG_FSL_CORENET */
67 #endif /* CONFIG_DDR_CLK_FREQ */
73 major &= 0x7; /* the msb of this nibble is a mfg code */
77 if (cpu_numcores() > 1) {
79 puts("Unicore software on multiprocessor system!!\n"
80 "To enable mutlticore build define CONFIG_MP\n");
82 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
83 printf("CPU%d: ", pic->whoami);
91 if (IS_E_PROCESSOR(svr))
94 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
100 minor = PVR_MIN(pvr);
103 if (PVR_FAM(PVR_85xx)) {
104 switch(PVR_MEM(pvr)) {
123 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
125 get_sys_info(&sysinfo);
127 puts("Clock Configuration:");
128 for (i = 0; i < cpu_numcores(); i++) {
131 printf("CPU%d:%-4s MHz, ",
132 i,strmhz(buf1, sysinfo.freqProcessor[i]));
134 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
136 #ifdef CONFIG_FSL_CORENET
138 printf(" DDR:%-4s MHz (%s MT/s data rate) "
140 strmhz(buf1, sysinfo.freqDDRBus/2),
141 strmhz(buf2, sysinfo.freqDDRBus));
143 printf(" DDR:%-4s MHz (%s MT/s data rate) "
145 strmhz(buf1, sysinfo.freqDDRBus/2),
146 strmhz(buf2, sysinfo.freqDDRBus));
151 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
152 strmhz(buf1, sysinfo.freqDDRBus/2),
153 strmhz(buf2, sysinfo.freqDDRBus));
156 printf(" DDR:%-4s MHz (%s MT/s data rate) "
158 strmhz(buf1, sysinfo.freqDDRBus/2),
159 strmhz(buf2, sysinfo.freqDDRBus));
162 printf(" DDR:%-4s MHz (%s MT/s data rate) "
164 strmhz(buf1, sysinfo.freqDDRBus/2),
165 strmhz(buf2, sysinfo.freqDDRBus));
170 #if defined(CONFIG_FSL_LBC)
171 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
172 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
174 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
175 sysinfo.freqLocalBus);
180 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
184 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
187 #ifdef CONFIG_SYS_DPAA_FMAN
188 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
189 printf(" FMAN%d: %s MHz\n", i + 1,
190 strmhz(buf1, sysinfo.freqFMan[i]));
194 #ifdef CONFIG_SYS_DPAA_PME
195 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
198 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
204 /* ------------------------------------------------------------------------- */
206 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
208 /* Everything after the first generation of PQ3 parts has RSTCR */
209 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
210 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
211 unsigned long val, msr;
214 * Initiate hard reset in debug control register DBCR0
215 * Make sure MSR[DE] = 1. This only resets the core.
225 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
226 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
235 * Get timebase clock frequency
237 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
238 #define CONFIG_SYS_FSL_TBCLK_DIV 8
240 unsigned long get_tbclk (void)
242 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
244 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
248 #if defined(CONFIG_WATCHDOG)
252 int re_enable = disable_interrupts();
253 reset_85xx_watchdog();
254 if (re_enable) enable_interrupts();
258 reset_85xx_watchdog(void)
261 * Clear TSR(WIS) bit by writing 1
264 val = mfspr(SPRN_TSR);
266 mtspr(SPRN_TSR, val);
268 #endif /* CONFIG_WATCHDOG */
271 * Initializes on-chip MMC controllers.
272 * to override, implement board_mmc_init()
274 int cpu_mmc_init(bd_t *bis)
276 #ifdef CONFIG_FSL_ESDHC
277 return fsl_esdhc_mmc_init(bis);
284 * Print out the state of various machine registers.
285 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
286 * parameters for IFC and TLBs
288 void mpc85xx_reginfo(void)
292 #if defined(CONFIG_FSL_LBC)
295 #ifdef CONFIG_FSL_IFC
301 /* Common ddr init for non-corenet fsl 85xx platforms */
302 #ifndef CONFIG_FSL_CORENET
303 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
304 phys_size_t initdram(int board_type)
306 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
307 return fsl_ddr_sdram_size();
309 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
312 #else /* CONFIG_SYS_RAMBOOT */
313 phys_size_t initdram(int board_type)
315 phys_size_t dram_size = 0;
317 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
319 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
324 * Work around to stabilize DDR DLL
326 out_be32(&gur->ddrdllcr, 0x81000000);
327 asm("sync;isync;msync");
329 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
330 setbits_be32(&gur->devdisr, 0x00010000);
331 for (i = 0; i < x; i++)
333 clrbits_be32(&gur->devdisr, 0x00010000);
339 #if defined(CONFIG_SPD_EEPROM) || \
340 defined(CONFIG_DDR_SPD) || \
341 defined(CONFIG_SYS_DDR_RAW_TIMING)
342 dram_size = fsl_ddr_sdram();
344 dram_size = fixed_sdram();
346 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
347 dram_size *= 0x100000;
349 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
351 * Initialize and enable DDR ECC.
353 ddr_enable_ecc(dram_size);
356 #if defined(CONFIG_FSL_LBC)
357 /* Some boards also have sdram on the lbc */
364 #endif /* CONFIG_SYS_RAMBOOT */
367 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
369 /* Board-specific functions defined in each board's ddr.c */
370 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
371 unsigned int ctrl_num);
372 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
375 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
377 static void dump_spd_ddr_reg(void)
382 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
384 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
386 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
387 fsl_ddr_get_spd(spd[i], i);
389 puts("SPD data of all dimms (zero vaule is omitted)...\n");
392 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
393 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
394 printf("Dimm%d ", k++);
397 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
399 printf("%3d (0x%02x) ", k, k);
400 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
401 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
402 p_8 = (u8 *) &spd[i][j];
404 printf("0x%02x ", p_8[k]);
416 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
419 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
421 #ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
423 ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
427 printf("%s unexpected controller number = %u\n",
432 printf("DDR registers dump for all controllers "
433 "(zero vaule is omitted)...\n");
434 puts("Offset (hex) ");
435 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
436 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
438 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
440 printf("%6d (0x%04x)", k * 4, k * 4);
441 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
442 p_32 = (u32 *) ddr[i];
444 printf(" 0x%08x", p_32[k]);
457 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
458 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
460 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
462 u32 tsize, valid, ptr;
468 while (ptr < (vstart + size)) {
469 ddr_esel = find_tlb_idx((void *)ptr, 1);
470 if (ddr_esel != -1) {
471 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
472 disable_tlb(ddr_esel);
474 ptr += TSIZE_TO_BYTES(tsize);
477 /* Setup new tlb to cover the physical address */
478 setup_ddr_tlbs_phys(p_addr, size>>20);
481 ddr_esel = find_tlb_idx((void *)ptr, 1);
482 if (ddr_esel != -1) {
483 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
485 printf("TLB error in function %s\n", __func__);
493 * slide the testing window up to test another area
494 * for 32_bit system, the maximum testable memory is limited to
495 * CONFIG_MAX_MEM_MAPPED
497 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
499 phys_addr_t test_cap, p_addr;
500 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
502 #if !defined(CONFIG_PHYS_64BIT) || \
503 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
504 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
507 test_cap = gd->ram_size;
509 p_addr = (*vstart) + (*size) + (*phys_offset);
510 if (p_addr < test_cap - 1) {
511 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
512 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
514 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
515 *size = (u32) p_size;
516 printf("Testing 0x%08llx - 0x%08llx\n",
517 (u64)(*vstart) + (*phys_offset),
518 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
525 /* initialization for testing area */
526 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
528 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
530 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
531 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
534 #if !defined(CONFIG_PHYS_64BIT) || \
535 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
536 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
537 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
538 puts("Cannot test more than ");
539 print_size(CONFIG_MAX_MEM_MAPPED,
540 " without proper 36BIT support.\n");
543 printf("Testing 0x%08llx - 0x%08llx\n",
544 (u64)(*vstart) + (*phys_offset),
545 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
550 /* invalid TLBs for DDR and remap as normal after testing */
551 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
554 u32 tsize, valid, ptr;
558 /* disable the TLBs for this testing */
561 while (ptr < (*vstart) + (*size)) {
562 ddr_esel = find_tlb_idx((void *)ptr, 1);
563 if (ddr_esel != -1) {
564 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
565 disable_tlb(ddr_esel);
567 ptr += TSIZE_TO_BYTES(tsize);
571 setup_ddr_tlbs(gd->ram_size>>20);
577 void arch_memory_failure_handle(void)