1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
14 #include <clock_legacy.h>
15 #include <display_options.h>
23 #include <fsl_esdhc.h>
24 #include <asm/cache.h>
25 #include <asm/global_data.h>
29 #include <asm/fsl_law.h>
30 #include <asm/fsl_lbc.h>
32 #include <asm/processor.h>
33 #include <fsl_ddr_sdram.h>
35 #include <linux/delay.h>
37 DECLARE_GLOBAL_DATA_PTR;
40 * Default board reset function
47 void board_reset(void) __attribute__((weak, alias("__board_reset")));
56 char buf1[32], buf2[32];
57 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \
58 defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
59 ccsr_gur_t __iomem *gur =
60 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
64 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
65 * mode. Previous platform use ddr ratio to do the same. This
66 * information is only for display here.
68 #ifdef CONFIG_FSL_CORENET
69 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
70 u32 ddr_sync = 0; /* only async mode is supported */
72 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
73 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
74 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
75 #else /* CONFIG_FSL_CORENET */
76 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
77 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
78 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
81 #endif /* CONFIG_DYNAMIC_DDR_CLK_FREQ || CONFIG_STATIC_DDR_CLK_FREQ */
82 #endif /* CONFIG_FSL_CORENET */
84 unsigned int i, core, nr_cores = cpu_numcores();
85 u32 mask = cpu_mask();
87 #ifdef CONFIG_HETROGENOUS_CLUSTERS
88 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
89 u32 dsp_mask = cpu_dsp_mask();
96 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
97 if (SVR_SOC_VER(svr) == SVR_T4080) {
99 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
101 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
102 FSL_CORENET_DEVDISR2_DTSEC1_9);
103 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
104 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
106 /* It needs SW to disable core4~7 as HW design sake on T4080 */
107 for (i = 4; i < 8; i++)
110 /* request core4~7 into PH20 state, prior to entering PCL10
111 * state, all cores in cluster should be placed in PH20 state.
113 setbits_be32(&rcpm->pcph20setr, 0xf0);
115 /* put the 2nd cluster into PCL10 state */
116 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
120 if (cpu_numcores() > 1) {
122 puts("Unicore software on multiprocessor system!!\n"
123 "To enable mutlticore build define CONFIG_MP\n");
125 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
126 printf("CPU%d: ", pic->whoami);
134 if (IS_E_PROCESSOR(svr))
137 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
141 major = PVR_MAJ(pvr);
142 minor = PVR_MIN(pvr);
146 case PVR_VER_E500_V1:
149 case PVR_VER_E500_V2:
166 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
168 if (nr_cores > CONFIG_MAX_CPUS) {
169 panic("\nUnexpected number of cores: %d, max is %d\n",
170 nr_cores, CONFIG_MAX_CPUS);
173 get_sys_info(&sysinfo);
175 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
176 if (sysinfo.diff_sysclk == 1)
177 puts("Single Source Clock Configuration\n");
180 puts("Clock Configuration:");
181 for_each_cpu(i, core, nr_cores, mask) {
184 printf("CPU%d:%-4s MHz, ", core,
185 strmhz(buf1, sysinfo.freq_processor[core]));
188 #ifdef CONFIG_HETROGENOUS_CLUSTERS
189 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
192 printf("DSP CPU%d:%-4s MHz, ", j,
193 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
197 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
200 #ifdef CONFIG_FSL_CORENET
202 printf(" DDR:%-4s MHz (%s MT/s data rate) "
204 strmhz(buf1, sysinfo.freq_ddrbus/2),
205 strmhz(buf2, sysinfo.freq_ddrbus));
207 printf(" DDR:%-4s MHz (%s MT/s data rate) "
209 strmhz(buf1, sysinfo.freq_ddrbus/2),
210 strmhz(buf2, sysinfo.freq_ddrbus));
215 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
216 strmhz(buf1, sysinfo.freq_ddrbus/2),
217 strmhz(buf2, sysinfo.freq_ddrbus));
220 printf(" DDR:%-4s MHz (%s MT/s data rate) "
222 strmhz(buf1, sysinfo.freq_ddrbus/2),
223 strmhz(buf2, sysinfo.freq_ddrbus));
226 printf(" DDR:%-4s MHz (%s MT/s data rate) "
228 strmhz(buf1, sysinfo.freq_ddrbus/2),
229 strmhz(buf2, sysinfo.freq_ddrbus));
234 #if defined(CONFIG_FSL_LBC)
235 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
236 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
238 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
239 sysinfo.freq_localbus);
243 #if defined(CONFIG_FSL_IFC)
244 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
248 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
251 #if defined(CONFIG_SYS_CPRI)
253 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
256 #if defined(CONFIG_SYS_MAPLE)
258 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
259 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
260 printf("MAPLE-eTVPE:%-4s MHz\n",
261 strmhz(buf1, sysinfo.freq_maple_etvpe));
264 #ifdef CONFIG_SYS_DPAA_FMAN
265 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
266 printf(" FMAN%d: %s MHz\n", i + 1,
267 strmhz(buf1, sysinfo.freq_fman[i]));
271 #ifdef CONFIG_SYS_DPAA_QBMAN
272 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
275 #ifdef CONFIG_SYS_DPAA_PME
276 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
279 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
281 #ifdef CONFIG_FSL_CORENET
282 /* Display the RCW, so that no one gets confused as to what RCW
283 * we're actually using for this boot.
285 puts("Reset Configuration Word (RCW):");
286 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
287 u32 rcw = in_be32(&gur->rcwsr[i]);
290 printf("\n %08x:", i * 4);
291 printf(" %08x", rcw);
300 /* ------------------------------------------------------------------------- */
302 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
304 /* Everything after the first generation of PQ3 parts has RSTCR */
305 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
306 unsigned long val, msr;
309 * Initiate hard reset in debug control register DBCR0
310 * Make sure MSR[DE] = 1. This only resets the core.
320 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
322 /* Attempt board-specific reset */
325 /* Next try asserting HRESET_REQ */
326 out_be32(&gur->rstcr, 0x2);
335 * Get timebase clock frequency
337 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
338 #define CONFIG_SYS_FSL_TBCLK_DIV 8
340 __weak unsigned long get_tbclk(void)
342 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
344 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
349 #if defined(CONFIG_WATCHDOG)
350 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
352 init_85xx_watchdog(void)
354 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
355 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
359 reset_85xx_watchdog(void)
362 * Clear TSR(WIS) bit by writing 1
364 mtspr(SPRN_TSR, TSR_WIS);
370 int re_enable = disable_interrupts();
372 reset_85xx_watchdog();
376 #endif /* CONFIG_WATCHDOG */
380 * Initializes on-chip MMC controllers.
381 * to override, implement board_mmc_init()
383 int cpu_mmc_init(struct bd_info *bis)
385 #ifdef CONFIG_FSL_ESDHC
386 return fsl_esdhc_mmc_init(bis);
393 * Print out the state of various machine registers.
394 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
395 * parameters for IFC and TLBs
397 void print_reginfo(void)
400 #ifdef CONFIG_FSL_LAW
403 #if defined(CONFIG_FSL_LBC)
406 #ifdef CONFIG_FSL_IFC
412 /* Common ddr init for non-corenet fsl 85xx platforms */
413 #ifndef CONFIG_FSL_CORENET
414 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
415 !defined(CONFIG_SYS_INIT_L2_ADDR)
418 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
419 defined(CONFIG_ARCH_QEMU_E500)
420 gd->ram_size = fsl_ddr_sdram_size();
422 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
427 #else /* CONFIG_SYS_RAMBOOT */
430 phys_size_t dram_size = 0;
432 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
434 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
439 * Work around to stabilize DDR DLL
441 out_be32(&gur->ddrdllcr, 0x81000000);
442 asm("sync;isync;msync");
444 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
445 setbits_be32(&gur->devdisr, 0x00010000);
446 for (i = 0; i < x; i++)
448 clrbits_be32(&gur->devdisr, 0x00010000);
454 #if defined(CONFIG_SPD_EEPROM) || \
455 defined(CONFIG_DDR_SPD) || \
456 defined(CONFIG_SYS_DDR_RAW_TIMING)
457 dram_size = fsl_ddr_sdram();
459 dram_size = fixed_sdram();
461 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
462 dram_size *= 0x100000;
464 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
466 * Initialize and enable DDR ECC.
468 ddr_enable_ecc(dram_size);
471 #if defined(CONFIG_FSL_LBC)
472 /* Some boards also have sdram on the lbc */
477 gd->ram_size = dram_size;
481 #endif /* CONFIG_SYS_RAMBOOT */
484 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
486 /* Board-specific functions defined in each board's ddr.c */
487 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
488 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
489 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
492 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
494 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
496 static void dump_spd_ddr_reg(void)
501 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
503 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
505 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
506 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
508 puts("SPD data of all dimms (zero value is omitted)...\n");
511 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
512 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
513 printf("Dimm%d ", k++);
516 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
518 printf("%3d (0x%02x) ", k, k);
519 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
520 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
521 p_8 = (u8 *) &spd[i][j];
523 printf("0x%02x ", p_8[k]);
535 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
538 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
540 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
542 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
545 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
547 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
550 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
552 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
556 printf("%s unexpected controller number = %u\n",
561 printf("DDR registers dump for all controllers "
562 "(zero value is omitted)...\n");
563 puts("Offset (hex) ");
564 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
565 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
567 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
569 printf("%6d (0x%04x)", k * 4, k * 4);
570 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
571 p_32 = (u32 *) ddr[i];
573 printf(" 0x%08x", p_32[k]);
586 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
587 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
589 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
591 u32 tsize, valid, ptr;
594 clear_ddr_tlbs_phys(p_addr, size>>20);
596 /* Setup new tlb to cover the physical address */
597 setup_ddr_tlbs_phys(p_addr, size>>20);
600 ddr_esel = find_tlb_idx((void *)ptr, 1);
601 if (ddr_esel != -1) {
602 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
604 printf("TLB error in function %s\n", __func__);
612 * slide the testing window up to test another area
613 * for 32_bit system, the maximum testable memory is limited to
614 * CONFIG_MAX_MEM_MAPPED
616 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
618 phys_addr_t test_cap, p_addr;
619 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
621 #if !defined(CONFIG_PHYS_64BIT) || \
622 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
623 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
626 test_cap = gd->ram_size;
628 p_addr = (*vstart) + (*size) + (*phys_offset);
629 if (p_addr < test_cap - 1) {
630 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
631 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
633 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
634 *size = (u32) p_size;
635 printf("Testing 0x%08llx - 0x%08llx\n",
636 (u64)(*vstart) + (*phys_offset),
637 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
644 /* initialization for testing area */
645 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
647 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
649 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
650 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
653 #if !defined(CONFIG_PHYS_64BIT) || \
654 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
655 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
656 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
657 puts("Cannot test more than ");
658 print_size(CONFIG_MAX_MEM_MAPPED,
659 " without proper 36BIT support.\n");
662 printf("Testing 0x%08llx - 0x%08llx\n",
663 (u64)(*vstart) + (*phys_offset),
664 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
669 /* invalid TLBs for DDR and remap as normal after testing */
670 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
673 u32 tsize, valid, ptr;
677 /* disable the TLBs for this testing */
680 while (ptr < (*vstart) + (*size)) {
681 ddr_esel = find_tlb_idx((void *)ptr, 1);
682 if (ddr_esel != -1) {
683 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
684 disable_tlb(ddr_esel);
686 ptr += TSIZE_TO_BYTES(tsize);
690 setup_ddr_tlbs(gd->ram_size>>20);
696 void arch_memory_failure_handle(void)