2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
16 #include <fsl_esdhc.h>
17 #include <asm/cache.h>
20 #include <asm/fsl_ifc.h>
21 #include <asm/fsl_law.h>
22 #include <asm/fsl_lbc.h>
24 #include <asm/processor.h>
25 #include <asm/fsl_ddr_sdram.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 * Default board reset function
37 void board_reset(void) __attribute__((weak, alias("__board_reset")));
46 char buf1[32], buf2[32];
47 #if (defined(CONFIG_DDR_CLK_FREQ) || \
48 defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 #endif /* CONFIG_FSL_CORENET */
53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 * mode. Previous platform use ddr ratio to do the same. This
55 * information is only for display here.
57 #ifdef CONFIG_FSL_CORENET
58 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 u32 ddr_sync = 0; /* only async mode is supported */
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64 #else /* CONFIG_FSL_CORENET */
65 #ifdef CONFIG_DDR_CLK_FREQ
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
70 #endif /* CONFIG_DDR_CLK_FREQ */
71 #endif /* CONFIG_FSL_CORENET */
73 unsigned int i, core, nr_cores = cpu_numcores();
74 u32 mask = cpu_mask();
80 if (cpu_numcores() > 1) {
82 puts("Unicore software on multiprocessor system!!\n"
83 "To enable mutlticore build define CONFIG_MP\n");
85 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
86 printf("CPU%d: ", pic->whoami);
94 if (IS_E_PROCESSOR(svr))
97 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
101 major = PVR_MAJ(pvr);
102 minor = PVR_MIN(pvr);
106 case PVR_VER_E500_V1:
107 case PVR_VER_E500_V2:
124 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
126 if (nr_cores > CONFIG_MAX_CPUS) {
127 panic("\nUnexpected number of cores: %d, max is %d\n",
128 nr_cores, CONFIG_MAX_CPUS);
131 get_sys_info(&sysinfo);
133 puts("Clock Configuration:");
134 for_each_cpu(i, core, nr_cores, mask) {
137 printf("CPU%d:%-4s MHz, ", core,
138 strmhz(buf1, sysinfo.freqProcessor[core]));
140 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
142 #ifdef CONFIG_FSL_CORENET
144 printf(" DDR:%-4s MHz (%s MT/s data rate) "
146 strmhz(buf1, sysinfo.freqDDRBus/2),
147 strmhz(buf2, sysinfo.freqDDRBus));
149 printf(" DDR:%-4s MHz (%s MT/s data rate) "
151 strmhz(buf1, sysinfo.freqDDRBus/2),
152 strmhz(buf2, sysinfo.freqDDRBus));
157 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
158 strmhz(buf1, sysinfo.freqDDRBus/2),
159 strmhz(buf2, sysinfo.freqDDRBus));
162 printf(" DDR:%-4s MHz (%s MT/s data rate) "
164 strmhz(buf1, sysinfo.freqDDRBus/2),
165 strmhz(buf2, sysinfo.freqDDRBus));
168 printf(" DDR:%-4s MHz (%s MT/s data rate) "
170 strmhz(buf1, sysinfo.freqDDRBus/2),
171 strmhz(buf2, sysinfo.freqDDRBus));
176 #if defined(CONFIG_FSL_LBC)
177 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
178 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
180 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
181 sysinfo.freqLocalBus);
185 #if defined(CONFIG_FSL_IFC)
186 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
190 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
194 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
197 #ifdef CONFIG_SYS_DPAA_FMAN
198 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
199 printf(" FMAN%d: %s MHz\n", i + 1,
200 strmhz(buf1, sysinfo.freqFMan[i]));
204 #ifdef CONFIG_SYS_DPAA_QBMAN
205 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
208 #ifdef CONFIG_SYS_DPAA_PME
209 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
212 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
218 /* ------------------------------------------------------------------------- */
220 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
222 /* Everything after the first generation of PQ3 parts has RSTCR */
223 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
224 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
225 unsigned long val, msr;
228 * Initiate hard reset in debug control register DBCR0
229 * Make sure MSR[DE] = 1. This only resets the core.
239 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
241 /* Attempt board-specific reset */
244 /* Next try asserting HRESET_REQ */
245 out_be32(&gur->rstcr, 0x2);
254 * Get timebase clock frequency
256 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
257 #define CONFIG_SYS_FSL_TBCLK_DIV 8
259 unsigned long get_tbclk (void)
261 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
263 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
267 #if defined(CONFIG_WATCHDOG)
269 reset_85xx_watchdog(void)
272 * Clear TSR(WIS) bit by writing 1
274 mtspr(SPRN_TSR, TSR_WIS);
280 int re_enable = disable_interrupts();
282 reset_85xx_watchdog();
286 #endif /* CONFIG_WATCHDOG */
289 * Initializes on-chip MMC controllers.
290 * to override, implement board_mmc_init()
292 int cpu_mmc_init(bd_t *bis)
294 #ifdef CONFIG_FSL_ESDHC
295 return fsl_esdhc_mmc_init(bis);
302 * Print out the state of various machine registers.
303 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
304 * parameters for IFC and TLBs
306 void mpc85xx_reginfo(void)
310 #if defined(CONFIG_FSL_LBC)
313 #ifdef CONFIG_FSL_IFC
319 /* Common ddr init for non-corenet fsl 85xx platforms */
320 #ifndef CONFIG_FSL_CORENET
321 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
322 !defined(CONFIG_SYS_INIT_L2_ADDR)
323 phys_size_t initdram(int board_type)
325 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
326 return fsl_ddr_sdram_size();
328 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
331 #else /* CONFIG_SYS_RAMBOOT */
332 phys_size_t initdram(int board_type)
334 phys_size_t dram_size = 0;
336 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
338 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
343 * Work around to stabilize DDR DLL
345 out_be32(&gur->ddrdllcr, 0x81000000);
346 asm("sync;isync;msync");
348 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
349 setbits_be32(&gur->devdisr, 0x00010000);
350 for (i = 0; i < x; i++)
352 clrbits_be32(&gur->devdisr, 0x00010000);
358 #if defined(CONFIG_SPD_EEPROM) || \
359 defined(CONFIG_DDR_SPD) || \
360 defined(CONFIG_SYS_DDR_RAW_TIMING)
361 dram_size = fsl_ddr_sdram();
363 dram_size = fixed_sdram();
365 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
366 dram_size *= 0x100000;
368 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
370 * Initialize and enable DDR ECC.
372 ddr_enable_ecc(dram_size);
375 #if defined(CONFIG_FSL_LBC)
376 /* Some boards also have sdram on the lbc */
383 #endif /* CONFIG_SYS_RAMBOOT */
386 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
388 /* Board-specific functions defined in each board's ddr.c */
389 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
390 unsigned int ctrl_num);
391 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
394 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
396 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
398 static void dump_spd_ddr_reg(void)
403 ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
405 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
407 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
408 fsl_ddr_get_spd(spd[i], i);
410 puts("SPD data of all dimms (zero vaule is omitted)...\n");
413 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
414 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
415 printf("Dimm%d ", k++);
418 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
420 printf("%3d (0x%02x) ", k, k);
421 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
422 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
423 p_8 = (u8 *) &spd[i][j];
425 printf("0x%02x ", p_8[k]);
437 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
440 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
442 #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
444 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
447 #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
449 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
452 #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
454 ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
458 printf("%s unexpected controller number = %u\n",
463 printf("DDR registers dump for all controllers "
464 "(zero vaule is omitted)...\n");
465 puts("Offset (hex) ");
466 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
467 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
469 for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
471 printf("%6d (0x%04x)", k * 4, k * 4);
472 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
473 p_32 = (u32 *) ddr[i];
475 printf(" 0x%08x", p_32[k]);
488 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
489 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
491 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
493 u32 tsize, valid, ptr;
496 clear_ddr_tlbs_phys(p_addr, size>>20);
498 /* Setup new tlb to cover the physical address */
499 setup_ddr_tlbs_phys(p_addr, size>>20);
502 ddr_esel = find_tlb_idx((void *)ptr, 1);
503 if (ddr_esel != -1) {
504 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
506 printf("TLB error in function %s\n", __func__);
514 * slide the testing window up to test another area
515 * for 32_bit system, the maximum testable memory is limited to
516 * CONFIG_MAX_MEM_MAPPED
518 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
520 phys_addr_t test_cap, p_addr;
521 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
523 #if !defined(CONFIG_PHYS_64BIT) || \
524 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
525 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
528 test_cap = gd->ram_size;
530 p_addr = (*vstart) + (*size) + (*phys_offset);
531 if (p_addr < test_cap - 1) {
532 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
533 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
535 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
536 *size = (u32) p_size;
537 printf("Testing 0x%08llx - 0x%08llx\n",
538 (u64)(*vstart) + (*phys_offset),
539 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
546 /* initialization for testing area */
547 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
549 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
551 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
552 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
555 #if !defined(CONFIG_PHYS_64BIT) || \
556 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
557 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
558 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
559 puts("Cannot test more than ");
560 print_size(CONFIG_MAX_MEM_MAPPED,
561 " without proper 36BIT support.\n");
564 printf("Testing 0x%08llx - 0x%08llx\n",
565 (u64)(*vstart) + (*phys_offset),
566 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
571 /* invalid TLBs for DDR and remap as normal after testing */
572 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
575 u32 tsize, valid, ptr;
579 /* disable the TLBs for this testing */
582 while (ptr < (*vstart) + (*size)) {
583 ddr_esel = find_tlb_idx((void *)ptr, 1);
584 if (ddr_esel != -1) {
585 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
586 disable_tlb(ddr_esel);
588 ptr += TSIZE_TO_BYTES(tsize);
592 setup_ddr_tlbs(gd->ram_size>>20);
598 void arch_memory_failure_handle(void)