1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
21 #include <fsl_esdhc.h>
22 #include <asm/cache.h>
26 #include <asm/fsl_law.h>
27 #include <asm/fsl_lbc.h>
29 #include <asm/processor.h>
30 #include <fsl_ddr_sdram.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 * Default board reset function
43 void board_reset(void) __attribute__((weak, alias("__board_reset")));
52 char buf1[32], buf2[32];
53 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
54 ccsr_gur_t __iomem *gur =
55 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
59 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
60 * mode. Previous platform use ddr ratio to do the same. This
61 * information is only for display here.
63 #ifdef CONFIG_FSL_CORENET
64 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
65 u32 ddr_sync = 0; /* only async mode is supported */
67 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
68 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
69 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
70 #else /* CONFIG_FSL_CORENET */
71 #ifdef CONFIG_DDR_CLK_FREQ
72 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
73 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
76 #endif /* CONFIG_DDR_CLK_FREQ */
77 #endif /* CONFIG_FSL_CORENET */
79 unsigned int i, core, nr_cores = cpu_numcores();
80 u32 mask = cpu_mask();
82 #ifdef CONFIG_HETROGENOUS_CLUSTERS
83 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
84 u32 dsp_mask = cpu_dsp_mask();
91 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
92 if (SVR_SOC_VER(svr) == SVR_T4080) {
94 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
96 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
97 FSL_CORENET_DEVDISR2_DTSEC1_9);
98 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
99 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
101 /* It needs SW to disable core4~7 as HW design sake on T4080 */
102 for (i = 4; i < 8; i++)
105 /* request core4~7 into PH20 state, prior to entering PCL10
106 * state, all cores in cluster should be placed in PH20 state.
108 setbits_be32(&rcpm->pcph20setr, 0xf0);
110 /* put the 2nd cluster into PCL10 state */
111 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
115 if (cpu_numcores() > 1) {
117 puts("Unicore software on multiprocessor system!!\n"
118 "To enable mutlticore build define CONFIG_MP\n");
120 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
121 printf("CPU%d: ", pic->whoami);
129 if (IS_E_PROCESSOR(svr))
132 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
136 major = PVR_MAJ(pvr);
137 minor = PVR_MIN(pvr);
141 case PVR_VER_E500_V1:
142 case PVR_VER_E500_V2:
159 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
161 if (nr_cores > CONFIG_MAX_CPUS) {
162 panic("\nUnexpected number of cores: %d, max is %d\n",
163 nr_cores, CONFIG_MAX_CPUS);
166 get_sys_info(&sysinfo);
168 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
169 if (sysinfo.diff_sysclk == 1)
170 puts("Single Source Clock Configuration\n");
173 puts("Clock Configuration:");
174 for_each_cpu(i, core, nr_cores, mask) {
177 printf("CPU%d:%-4s MHz, ", core,
178 strmhz(buf1, sysinfo.freq_processor[core]));
181 #ifdef CONFIG_HETROGENOUS_CLUSTERS
182 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
185 printf("DSP CPU%d:%-4s MHz, ", j,
186 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
190 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
193 #ifdef CONFIG_FSL_CORENET
195 printf(" DDR:%-4s MHz (%s MT/s data rate) "
197 strmhz(buf1, sysinfo.freq_ddrbus/2),
198 strmhz(buf2, sysinfo.freq_ddrbus));
200 printf(" DDR:%-4s MHz (%s MT/s data rate) "
202 strmhz(buf1, sysinfo.freq_ddrbus/2),
203 strmhz(buf2, sysinfo.freq_ddrbus));
208 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
209 strmhz(buf1, sysinfo.freq_ddrbus/2),
210 strmhz(buf2, sysinfo.freq_ddrbus));
213 printf(" DDR:%-4s MHz (%s MT/s data rate) "
215 strmhz(buf1, sysinfo.freq_ddrbus/2),
216 strmhz(buf2, sysinfo.freq_ddrbus));
219 printf(" DDR:%-4s MHz (%s MT/s data rate) "
221 strmhz(buf1, sysinfo.freq_ddrbus/2),
222 strmhz(buf2, sysinfo.freq_ddrbus));
227 #if defined(CONFIG_FSL_LBC)
228 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
229 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
231 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
232 sysinfo.freq_localbus);
236 #if defined(CONFIG_FSL_IFC)
237 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
241 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
245 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
248 #if defined(CONFIG_SYS_CPRI)
250 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
253 #if defined(CONFIG_SYS_MAPLE)
255 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
256 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
257 printf("MAPLE-eTVPE:%-4s MHz\n",
258 strmhz(buf1, sysinfo.freq_maple_etvpe));
261 #ifdef CONFIG_SYS_DPAA_FMAN
262 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
263 printf(" FMAN%d: %s MHz\n", i + 1,
264 strmhz(buf1, sysinfo.freq_fman[i]));
268 #ifdef CONFIG_SYS_DPAA_QBMAN
269 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
272 #ifdef CONFIG_SYS_DPAA_PME
273 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
276 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
278 #ifdef CONFIG_FSL_CORENET
279 /* Display the RCW, so that no one gets confused as to what RCW
280 * we're actually using for this boot.
282 puts("Reset Configuration Word (RCW):");
283 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
284 u32 rcw = in_be32(&gur->rcwsr[i]);
287 printf("\n %08x:", i * 4);
288 printf(" %08x", rcw);
297 /* ------------------------------------------------------------------------- */
299 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
301 /* Everything after the first generation of PQ3 parts has RSTCR */
302 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
303 defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
304 unsigned long val, msr;
307 * Initiate hard reset in debug control register DBCR0
308 * Make sure MSR[DE] = 1. This only resets the core.
318 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
320 /* Attempt board-specific reset */
323 /* Next try asserting HRESET_REQ */
324 out_be32(&gur->rstcr, 0x2);
333 * Get timebase clock frequency
335 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
336 #define CONFIG_SYS_FSL_TBCLK_DIV 8
338 __weak unsigned long get_tbclk(void)
340 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
342 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
346 #if defined(CONFIG_WATCHDOG)
347 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
349 init_85xx_watchdog(void)
351 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
352 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
356 reset_85xx_watchdog(void)
359 * Clear TSR(WIS) bit by writing 1
361 mtspr(SPRN_TSR, TSR_WIS);
367 int re_enable = disable_interrupts();
369 reset_85xx_watchdog();
373 #endif /* CONFIG_WATCHDOG */
376 * Initializes on-chip MMC controllers.
377 * to override, implement board_mmc_init()
379 int cpu_mmc_init(bd_t *bis)
381 #ifdef CONFIG_FSL_ESDHC
382 return fsl_esdhc_mmc_init(bis);
389 * Print out the state of various machine registers.
390 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
391 * parameters for IFC and TLBs
393 void print_reginfo(void)
397 #if defined(CONFIG_FSL_LBC)
400 #ifdef CONFIG_FSL_IFC
406 /* Common ddr init for non-corenet fsl 85xx platforms */
407 #ifndef CONFIG_FSL_CORENET
408 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
409 !defined(CONFIG_SYS_INIT_L2_ADDR)
412 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
413 defined(CONFIG_ARCH_QEMU_E500)
414 gd->ram_size = fsl_ddr_sdram_size();
416 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
421 #else /* CONFIG_SYS_RAMBOOT */
424 phys_size_t dram_size = 0;
426 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
428 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
433 * Work around to stabilize DDR DLL
435 out_be32(&gur->ddrdllcr, 0x81000000);
436 asm("sync;isync;msync");
438 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
439 setbits_be32(&gur->devdisr, 0x00010000);
440 for (i = 0; i < x; i++)
442 clrbits_be32(&gur->devdisr, 0x00010000);
448 #if defined(CONFIG_SPD_EEPROM) || \
449 defined(CONFIG_DDR_SPD) || \
450 defined(CONFIG_SYS_DDR_RAW_TIMING)
451 dram_size = fsl_ddr_sdram();
453 dram_size = fixed_sdram();
455 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
456 dram_size *= 0x100000;
458 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
460 * Initialize and enable DDR ECC.
462 ddr_enable_ecc(dram_size);
465 #if defined(CONFIG_FSL_LBC)
466 /* Some boards also have sdram on the lbc */
471 gd->ram_size = dram_size;
475 #endif /* CONFIG_SYS_RAMBOOT */
478 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
480 /* Board-specific functions defined in each board's ddr.c */
481 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
482 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
483 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
486 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
488 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
490 static void dump_spd_ddr_reg(void)
495 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
497 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
499 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
500 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
502 puts("SPD data of all dimms (zero value is omitted)...\n");
505 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
506 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
507 printf("Dimm%d ", k++);
510 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
512 printf("%3d (0x%02x) ", k, k);
513 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
514 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
515 p_8 = (u8 *) &spd[i][j];
517 printf("0x%02x ", p_8[k]);
529 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
532 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
534 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
536 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
539 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
541 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
544 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
546 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
550 printf("%s unexpected controller number = %u\n",
555 printf("DDR registers dump for all controllers "
556 "(zero value is omitted)...\n");
557 puts("Offset (hex) ");
558 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
559 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
561 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
563 printf("%6d (0x%04x)", k * 4, k * 4);
564 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
565 p_32 = (u32 *) ddr[i];
567 printf(" 0x%08x", p_32[k]);
580 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
581 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
583 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
585 u32 tsize, valid, ptr;
588 clear_ddr_tlbs_phys(p_addr, size>>20);
590 /* Setup new tlb to cover the physical address */
591 setup_ddr_tlbs_phys(p_addr, size>>20);
594 ddr_esel = find_tlb_idx((void *)ptr, 1);
595 if (ddr_esel != -1) {
596 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
598 printf("TLB error in function %s\n", __func__);
606 * slide the testing window up to test another area
607 * for 32_bit system, the maximum testable memory is limited to
608 * CONFIG_MAX_MEM_MAPPED
610 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
612 phys_addr_t test_cap, p_addr;
613 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
615 #if !defined(CONFIG_PHYS_64BIT) || \
616 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
617 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
620 test_cap = gd->ram_size;
622 p_addr = (*vstart) + (*size) + (*phys_offset);
623 if (p_addr < test_cap - 1) {
624 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
625 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
627 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
628 *size = (u32) p_size;
629 printf("Testing 0x%08llx - 0x%08llx\n",
630 (u64)(*vstart) + (*phys_offset),
631 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
638 /* initialization for testing area */
639 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
641 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
643 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
644 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
647 #if !defined(CONFIG_PHYS_64BIT) || \
648 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
649 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
650 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
651 puts("Cannot test more than ");
652 print_size(CONFIG_MAX_MEM_MAPPED,
653 " without proper 36BIT support.\n");
656 printf("Testing 0x%08llx - 0x%08llx\n",
657 (u64)(*vstart) + (*phys_offset),
658 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
663 /* invalid TLBs for DDR and remap as normal after testing */
664 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
667 u32 tsize, valid, ptr;
671 /* disable the TLBs for this testing */
674 while (ptr < (*vstart) + (*size)) {
675 ddr_esel = find_tlb_idx((void *)ptr, 1);
676 if (ddr_esel != -1) {
677 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
678 disable_tlb(ddr_esel);
680 ptr += TSIZE_TO_BYTES(tsize);
684 setup_ddr_tlbs(gd->ram_size>>20);
690 void arch_memory_failure_handle(void)