2 * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <fsl_esdhc.h>
33 #include <asm/cache.h>
36 #include <asm/fsl_law.h>
38 DECLARE_GLOBAL_DATA_PTR;
48 char buf1[32], buf2[32];
49 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51 #endif /* CONFIG_FSL_CORENET */
52 #ifdef CONFIG_DDR_CLK_FREQ
53 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
54 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
56 #ifdef CONFIG_FSL_CORENET
57 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
58 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
61 #endif /* CONFIG_FSL_CORENET */
62 #endif /* CONFIG_DDR_CLK_FREQ */
68 major &= 0x7; /* the msb of this nibble is a mfg code */
72 if (cpu_numcores() > 1) {
74 puts("Unicore software on multiprocessor system!!\n"
75 "To enable mutlticore build define CONFIG_MP\n");
77 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
78 printf("CPU%d: ", pic->whoami);
86 if (IS_E_PROCESSOR(svr))
89 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
98 if (PVR_FAM(PVR_85xx)) {
99 switch(PVR_MEM(pvr)) {
118 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
120 get_sys_info(&sysinfo);
122 puts("Clock Configuration:");
123 for (i = 0; i < cpu_numcores(); i++) {
126 printf("CPU%d:%-4s MHz, ",
127 i,strmhz(buf1, sysinfo.freqProcessor[i]));
129 printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
131 #ifdef CONFIG_FSL_CORENET
133 printf(" DDR:%-4s MHz (%s MT/s data rate) "
135 strmhz(buf1, sysinfo.freqDDRBus/2),
136 strmhz(buf2, sysinfo.freqDDRBus));
138 printf(" DDR:%-4s MHz (%s MT/s data rate) "
140 strmhz(buf1, sysinfo.freqDDRBus/2),
141 strmhz(buf2, sysinfo.freqDDRBus));
146 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
147 strmhz(buf1, sysinfo.freqDDRBus/2),
148 strmhz(buf2, sysinfo.freqDDRBus));
151 printf(" DDR:%-4s MHz (%s MT/s data rate) "
153 strmhz(buf1, sysinfo.freqDDRBus/2),
154 strmhz(buf2, sysinfo.freqDDRBus));
157 printf(" DDR:%-4s MHz (%s MT/s data rate) "
159 strmhz(buf1, sysinfo.freqDDRBus/2),
160 strmhz(buf2, sysinfo.freqDDRBus));
165 if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
166 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
168 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
169 sysinfo.freqLocalBus);
173 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
177 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
180 #ifdef CONFIG_SYS_DPAA_FMAN
181 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
182 printf(" FMAN%d: %s MHz\n", i + 1,
183 strmhz(buf1, sysinfo.freqFMan[i]));
187 #ifdef CONFIG_SYS_DPAA_PME
188 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
191 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
197 /* ------------------------------------------------------------------------- */
199 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
201 /* Everything after the first generation of PQ3 parts has RSTCR */
202 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
203 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
204 unsigned long val, msr;
207 * Initiate hard reset in debug control register DBCR0
208 * Make sure MSR[DE] = 1. This only resets the core.
218 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
219 out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
228 * Get timebase clock frequency
230 unsigned long get_tbclk (void)
232 #ifdef CONFIG_FSL_CORENET
233 return (gd->bus_clk + 8) / 16;
235 return (gd->bus_clk + 4UL)/8UL;
240 #if defined(CONFIG_WATCHDOG)
244 int re_enable = disable_interrupts();
245 reset_85xx_watchdog();
246 if (re_enable) enable_interrupts();
250 reset_85xx_watchdog(void)
253 * Clear TSR(WIS) bit by writing 1
256 val = mfspr(SPRN_TSR);
258 mtspr(SPRN_TSR, val);
260 #endif /* CONFIG_WATCHDOG */
263 * Initializes on-chip MMC controllers.
264 * to override, implement board_mmc_init()
266 int cpu_mmc_init(bd_t *bis)
268 #ifdef CONFIG_FSL_ESDHC
269 return fsl_esdhc_mmc_init(bis);
276 * Print out the state of various machine registers.
277 * Currently prints out LAWs, BR0/OR0, and TLBs
279 void mpc85xx_reginfo(void)