2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/compiler.h>
26 #include <asm/processor.h>
27 #include "fsl_corenet_serdes.h"
29 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
31 * This work-around is implemented in PBI, so just check to see if the
32 * work-around was actually applied. To do this, we check for specific data
33 * at specific addresses in DCSR.
35 * Array offsets[] contains a list of offsets within DCSR. According to the
36 * erratum document, the value at each offset should be 2.
38 static void check_erratum_a4849(uint32_t svr)
40 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
43 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
44 static const uint8_t offsets[] = {
45 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
48 #ifdef CONFIG_PPC_P4080
49 static const uint8_t offsets[] = {
50 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
53 uint32_t x108; /* The value that should be at offset 0x108 */
55 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
56 if (in_be32(dcsr + offsets[i]) != 2) {
57 printf("Work-around for Erratum A004849 is not enabled\n");
62 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
66 #ifdef CONFIG_PPC_P4080
68 * For P4080, the erratum document says that the value at offset 0x108
69 * should be 0x12 on rev2, or 0x1c on rev3.
71 if (SVR_MAJ(svr) == 2)
73 if (SVR_MAJ(svr) == 3)
77 if (in_be32(dcsr + 0x108) != x108) {
78 printf("Work-around for Erratum A004849 is not enabled\n");
82 /* Everything matches, so the erratum work-around was applied */
84 printf("Work-around for Erratum A004849 enabled\n");
88 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
90 * This work-around is implemented in PBI, so just check to see if the
91 * work-around was actually applied. To do this, we check for specific data
92 * at specific addresses in the SerDes register block.
94 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
95 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
98 static void check_erratum_a4580(uint32_t svr)
100 const serdes_corenet_t __iomem *srds_regs =
101 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
104 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
105 if (serdes_lane_enabled(lane)) {
106 const struct serdes_lane __iomem *srds_lane =
107 &srds_regs->lane[serdes_get_lane_idx(lane)];
110 * Verify that the values we were supposed to write in
111 * the PBI are actually there. Also, the lower 15
112 * bits of res4[3] should be the same as the upper 15
115 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
116 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
117 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
118 printf("Work-around for Erratum A004580 is "
125 /* Everything matches, so the erratum work-around was applied */
127 printf("Work-around for Erratum A004580 enabled\n");
131 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
133 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
134 extern int enable_cpu_a011_workaround;
136 __maybe_unused u32 svr = get_svr();
138 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
139 if (IS_SVR_REV(svr, 1, 0)) {
140 switch (SVR_SOC_VER(svr)) {
143 puts("Work-around for Erratum SATA A001 enabled\n");
148 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
149 puts("Work-around for Erratum SERDES8 enabled\n");
151 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
152 puts("Work-around for Erratum SERDES9 enabled\n");
154 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
155 puts("Work-around for Erratum SERDES-A005 enabled\n");
157 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
158 if (SVR_MAJ(svr) < 3)
159 puts("Work-around for Erratum CPU22 enabled\n");
161 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
163 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
164 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
165 * The SVR has been checked by cpu_init_r().
167 if (enable_cpu_a011_workaround)
168 puts("Work-around for Erratum CPU-A011 enabled\n");
170 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
171 puts("Work-around for Erratum CPU-A003999 enabled\n");
173 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
174 puts("Work-around for Erratum DDR-A003473 enabled\n");
176 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
177 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
179 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
180 puts("Work-around for Erratum ESDHC111 enabled\n");
182 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
183 puts("Work-around for Erratum A004468 enabled\n");
185 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
186 puts("Work-around for Erratum ESDHC135 enabled\n");
188 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
189 if (SVR_MAJ(svr) < 3)
190 puts("Work-around for Erratum ESDHC13 enabled\n");
192 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
193 puts("Work-around for Erratum ESDHC-A001 enabled\n");
195 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
196 puts("Work-around for Erratum CPC-A002 enabled\n");
198 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
199 puts("Work-around for Erratum CPC-A003 enabled\n");
201 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
202 puts("Work-around for Erratum ELBC-A001 enabled\n");
204 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
205 puts("Work-around for Erratum DDR-A003 enabled\n");
207 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
208 puts("Work-around for Erratum DDR115 enabled\n");
210 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
211 puts("Work-around for Erratum DDR111 enabled\n");
212 puts("Work-around for Erratum DDR134 enabled\n");
214 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
215 puts("Work-around for Erratum IFC-A002769 enabled\n");
217 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
218 puts("Work-around for Erratum P1010-A003549 enabled\n");
220 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
221 puts("Work-around for Erratum IFC A-003399 enabled\n");
223 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
224 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
225 puts("Work-around for Erratum NMG DDR120 enabled\n");
227 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
228 puts("Work-around for Erratum NMG_LBC103 enabled\n");
230 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
231 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
232 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
234 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
235 puts("Work-around for Erratum A004510 enabled\n");
237 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
238 puts("Work-around for Erratum SRIO-A004034 enabled\n");
240 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
241 puts("Work-around for Erratum A004934 enabled\n");
243 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
244 if (IS_SVR_REV(svr, 1, 0))
245 puts("Work-around for Erratum A005871 enabled\n");
247 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
248 /* This work-around is implemented in PBI, so just check for it */
249 check_erratum_a4849(svr);
251 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
252 /* This work-around is implemented in PBI, so just check for it */
253 check_erratum_a4580(svr);
255 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
256 puts("Work-around for Erratum PCIe-A003 enabled\n");
258 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
259 puts("Work-around for Erratum USB14 enabled\n");
265 errata, 1, 0, do_errata,
266 "Report errata workarounds",