2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/fsl_serdes.h>
25 #include <asm/processor.h>
27 #include "fsl_corenet2_serdes.h"
29 struct serdes_config {
31 u8 lanes[SRDS_MAX_LANES];
34 static struct serdes_config serdes1_cfg_tbl[] = {
36 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
37 CPRI4, CPRI3, CPRI2, CPRI1}},
38 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
39 CPRI4, CPRI3, CPRI2, CPRI1}},
40 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
41 CPRI4, CPRI3, CPRI2, CPRI1}},
42 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
43 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
44 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
45 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
46 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
47 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
48 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
49 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
50 {0x30, {AURORA, AURORA,
51 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
52 CPRI4, CPRI3, CPRI2, CPRI1}},
53 {0x32, {AURORA, AURORA,
54 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
55 CPRI4, CPRI3, CPRI2, CPRI1}},
56 {0x33, {AURORA, AURORA,
57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
58 CPRI4, CPRI3, CPRI2, CPRI1}},
59 {0x34, {AURORA, AURORA,
60 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
61 CPRI4, CPRI3, CPRI2, CPRI1}},
62 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
63 CPRI4, CPRI3, CPRI2, CPRI1}},
66 static struct serdes_config serdes2_cfg_tbl[] = {
68 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
69 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
70 AURORA, AURORA, SRIO1, SRIO1}},
71 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
72 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
73 AURORA, AURORA, SRIO1, SRIO1}},
74 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
76 AURORA, AURORA, SRIO1, SRIO1}},
77 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
81 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
82 SGMII_FM1_DTSEC3, AURORA,
83 SRIO1, SRIO1, SRIO1, SRIO1}},
84 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
85 SGMII_FM1_DTSEC3, AURORA,
86 SRIO1, SRIO1, SRIO1, SRIO1}},
87 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
88 SGMII_FM1_DTSEC3, AURORA,
89 SRIO1, SRIO1, SRIO1, SRIO1}},
90 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
91 SGMII_FM1_DTSEC3, AURORA,
92 SRIO1, SRIO1, SRIO1, SRIO1}},
93 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
94 SRIO1, SRIO1, SRIO1, SRIO1}},
95 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
96 SRIO2, SRIO2, AURORA, AURORA,
97 XFI_FM1_MAC9, XFI_FM1_MAC10}},
98 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
99 SRIO2, SRIO2, AURORA, AURORA,
100 XFI_FM1_MAC9, XFI_FM1_MAC10}},
101 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
103 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
104 XFI_FM1_MAC9, XFI_FM1_MAC10}},
105 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
106 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
107 XFI_FM1_MAC9, XFI_FM1_MAC10}},
108 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
109 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
110 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
111 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
112 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
113 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
114 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
115 {0x9A, {PCIE1, PCIE1,
116 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
117 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
118 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
119 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
120 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
121 XFI_FM1_MAC9, XFI_FM1_MAC10}},
122 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
123 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
124 SRIO1, SRIO1, SRIO1, SRIO1}},
125 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
126 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
127 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
128 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
131 static struct serdes_config *serdes_cfg_tbl[] = {
136 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
138 struct serdes_config *ptr;
140 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
143 ptr = serdes_cfg_tbl[serdes];
144 while (ptr->protocol) {
145 if (ptr->protocol == cfg)
146 return ptr->lanes[lane];
153 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
156 struct serdes_config *ptr;
158 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
161 ptr = serdes_cfg_tbl[serdes];
162 while (ptr->protocol) {
163 if (ptr->protocol == prtcl)
171 for (i = 0; i < SRDS_MAX_LANES; i++) {
172 if (ptr->lanes[i] != NONE)