8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
51 select SYS_CACHE_SHIFT_5
53 config TARGET_P1010RDB_PA
54 bool "Support P1010RDB_PA"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 config TARGET_P1010RDB_PB
64 bool "Support P1010RDB_PB"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 config TARGET_P1020RDB_PC
74 bool "Support P1020RDB-PC"
82 config TARGET_P1020RDB_PD
83 bool "Support P1020RDB-PD"
91 config TARGET_P2020RDB
92 bool "Support P2020RDB-PC"
100 config TARGET_P2041RDB
101 bool "Support P2041RDB"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_QEMU_PPCE500
109 bool "Support qemu-ppce500"
110 select ARCH_QEMU_E500
112 imply OF_HAS_PRIOR_STAGE
114 config TARGET_T1024RDB
115 bool "Support T1024RDB"
117 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 select FSL_DDR_INTERACTIVE
124 config TARGET_T1042RDB
125 bool "Support T1042RDB"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
131 config TARGET_T1042D4RDB
132 bool "Support T1042D4RDB"
134 select BOARD_LATE_INIT if CHAIN_OF_TRUST
139 config TARGET_T1042RDB_PI
140 bool "Support T1042RDB_PI"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_T2080QDS
148 bool "Support T2080QDS"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
153 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
154 select FSL_DDR_INTERACTIVE
157 config TARGET_T2080RDB
158 bool "Support T2080RDB"
160 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_T4240RDB
167 bool "Support T4240RDB"
171 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
175 config TARGET_KMP204X
176 bool "Support kmp204x"
179 config TARGET_KMCENT2
180 bool "Support kmcent2"
190 select SYS_FSL_DDR_VER_47
191 select SYS_FSL_ERRATUM_A004477
192 select SYS_FSL_ERRATUM_A005871
193 select SYS_FSL_ERRATUM_A006379
194 select SYS_FSL_ERRATUM_A006384
195 select SYS_FSL_ERRATUM_A006475
196 select SYS_FSL_ERRATUM_A006593
197 select SYS_FSL_ERRATUM_A007075
198 select SYS_FSL_ERRATUM_A007186
199 select SYS_FSL_ERRATUM_A007212
200 select SYS_FSL_ERRATUM_A009942
201 select SYS_FSL_HAS_DDR3
202 select SYS_FSL_HAS_SEC
203 select SYS_FSL_QORIQ_CHASSIS2
204 select SYS_FSL_SEC_BE
205 select SYS_FSL_SEC_COMPAT_4
217 select SYS_FSL_DDR_VER_47
218 select SYS_FSL_ERRATUM_A004477
219 select SYS_FSL_ERRATUM_A005871
220 select SYS_FSL_ERRATUM_A006379
221 select SYS_FSL_ERRATUM_A006384
222 select SYS_FSL_ERRATUM_A006475
223 select SYS_FSL_ERRATUM_A006593
224 select SYS_FSL_ERRATUM_A007075
225 select SYS_FSL_ERRATUM_A007186
226 select SYS_FSL_ERRATUM_A007212
227 select SYS_FSL_ERRATUM_A007907
228 select SYS_FSL_ERRATUM_A009942
229 select SYS_FSL_HAS_DDR3
230 select SYS_FSL_HAS_SEC
231 select SYS_FSL_QORIQ_CHASSIS2
232 select SYS_FSL_SEC_BE
233 select SYS_FSL_SEC_COMPAT_4
243 select SYS_FSL_DDR_VER_44
244 select SYS_FSL_ERRATUM_A004477
245 select SYS_FSL_ERRATUM_A005125
246 select SYS_FSL_ERRATUM_ESDHC111
247 select SYS_FSL_HAS_DDR3
248 select SYS_FSL_HAS_SEC
249 select SYS_FSL_SEC_BE
250 select SYS_FSL_SEC_COMPAT_4
259 select SYS_FSL_DDR_VER_46
260 select SYS_FSL_ERRATUM_A004477
261 select SYS_FSL_ERRATUM_A005125
262 select SYS_FSL_ERRATUM_A005434
263 select SYS_FSL_ERRATUM_ESDHC111
264 select SYS_FSL_ERRATUM_I2C_A004447
265 select SYS_FSL_ERRATUM_IFC_A002769
266 select FSL_PCIE_RESET
267 select SYS_FSL_HAS_DDR3
268 select SYS_FSL_HAS_SEC
269 select SYS_FSL_SEC_BE
270 select SYS_FSL_SEC_COMPAT_4
271 select SYS_PPC_E500_USE_DEBUG_TLB
282 select SYS_FSL_DDR_VER_46
283 select SYS_FSL_ERRATUM_A005125
284 select SYS_FSL_ERRATUM_ESDHC111
285 select FSL_PCIE_RESET
286 select SYS_FSL_HAS_DDR3
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_6
290 select SYS_PPC_E500_USE_DEBUG_TLB
299 select SYS_FSL_ERRATUM_A004508
300 select SYS_FSL_ERRATUM_A005125
301 select FSL_PCIE_RESET
302 select SYS_FSL_HAS_DDR2
303 select SYS_FSL_HAS_DDR3
304 select SYS_FSL_HAS_SEC
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_2
307 select SYS_PPC_E500_USE_DEBUG_TLB
316 select SYS_FSL_HAS_DDR1
322 select SYS_CACHE_SHIFT_5
323 select SYS_FSL_ERRATUM_A005125
324 select FSL_PCIE_RESET
325 select SYS_FSL_HAS_DDR2
326 select SYS_FSL_HAS_SEC
327 select SYS_FSL_SEC_BE
328 select SYS_FSL_SEC_COMPAT_2
329 select SYS_PPC_E500_USE_DEBUG_TLB
336 select SYS_FSL_ERRATUM_A005125
337 select SYS_FSL_ERRATUM_NMG_DDR120
338 select SYS_FSL_ERRATUM_NMG_LBC103
339 select SYS_FSL_ERRATUM_NMG_ETSEC129
340 select SYS_FSL_ERRATUM_I2C_A004447
341 select FSL_PCIE_RESET
342 select SYS_FSL_HAS_DDR2
343 select SYS_FSL_HAS_DDR1
344 select SYS_FSL_HAS_SEC
345 select SYS_FSL_SEC_BE
346 select SYS_FSL_SEC_COMPAT_2
347 select SYS_PPC_E500_USE_DEBUG_TLB
353 select SYS_FSL_HAS_DDR1
359 select SYS_CACHE_SHIFT_5
360 select SYS_HAS_SERDES
361 select SYS_FSL_ERRATUM_A004477
362 select SYS_FSL_ERRATUM_A004508
363 select SYS_FSL_ERRATUM_A005125
364 select SYS_FSL_ERRATUM_A005275
365 select SYS_FSL_ERRATUM_A006261
366 select SYS_FSL_ERRATUM_A007075
367 select SYS_FSL_ERRATUM_ESDHC111
368 select SYS_FSL_ERRATUM_I2C_A004447
369 select SYS_FSL_ERRATUM_IFC_A002769
370 select SYS_FSL_ERRATUM_P1010_A003549
371 select SYS_FSL_ERRATUM_SEC_A003571
372 select SYS_FSL_ERRATUM_IFC_A003399
373 select FSL_PCIE_RESET
374 select SYS_FSL_HAS_DDR3
375 select SYS_FSL_HAS_SEC
376 select SYS_FSL_SEC_BE
377 select SYS_FSL_SEC_COMPAT_4
378 select SYS_PPC_E500_USE_DEBUG_TLB
392 select SYS_FSL_ERRATUM_A004508
393 select SYS_FSL_ERRATUM_A005125
394 select SYS_FSL_ERRATUM_ELBC_A001
395 select SYS_FSL_ERRATUM_ESDHC111
396 select FSL_PCIE_DISABLE_ASPM
397 select SYS_FSL_HAS_DDR3
398 select SYS_FSL_HAS_SEC
399 select SYS_FSL_SEC_BE
400 select SYS_FSL_SEC_COMPAT_2
401 select SYS_PPC_E500_USE_DEBUG_TLB
408 select SYS_CACHE_SHIFT_5
409 select SYS_FSL_ERRATUM_A004508
410 select SYS_FSL_ERRATUM_A005125
411 select SYS_FSL_ERRATUM_ELBC_A001
412 select SYS_FSL_ERRATUM_ESDHC111
413 select FSL_PCIE_DISABLE_ASPM
414 select FSL_PCIE_RESET
415 select SYS_FSL_HAS_DDR3
416 select SYS_FSL_HAS_SEC
417 select SYS_FSL_SEC_BE
418 select SYS_FSL_SEC_COMPAT_2
419 select SYS_PPC_E500_USE_DEBUG_TLB
430 select SYS_FSL_ERRATUM_A004508
431 select SYS_FSL_ERRATUM_A005125
432 select SYS_FSL_ERRATUM_ELBC_A001
433 select SYS_FSL_ERRATUM_ESDHC111
434 select FSL_PCIE_DISABLE_ASPM
435 select FSL_PCIE_RESET
436 select SYS_FSL_HAS_DDR3
437 select SYS_FSL_HAS_SEC
438 select SYS_FSL_SEC_BE
439 select SYS_FSL_SEC_COMPAT_2
440 select SYS_PPC_E500_USE_DEBUG_TLB
451 select SYS_FSL_ERRATUM_A004508
452 select SYS_FSL_ERRATUM_A005125
453 select SYS_FSL_ERRATUM_I2C_A004447
454 select FSL_PCIE_RESET
455 select SYS_FSL_HAS_DDR3
456 select SYS_FSL_HAS_SEC
457 select SYS_FSL_SEC_BE
458 select SYS_FSL_SEC_COMPAT_4
464 select SYS_FSL_ERRATUM_A004508
465 select SYS_FSL_ERRATUM_A005125
466 select SYS_FSL_ERRATUM_ELBC_A001
467 select SYS_FSL_ERRATUM_ESDHC111
468 select FSL_PCIE_DISABLE_ASPM
469 select FSL_PCIE_RESET
470 select SYS_FSL_HAS_DDR3
471 select SYS_FSL_HAS_SEC
472 select SYS_FSL_SEC_BE
473 select SYS_FSL_SEC_COMPAT_2
474 select SYS_PPC_E500_USE_DEBUG_TLB
486 select SYS_FSL_ERRATUM_A004508
487 select SYS_FSL_ERRATUM_A005125
488 select SYS_FSL_ERRATUM_ELBC_A001
489 select SYS_FSL_ERRATUM_ESDHC111
490 select FSL_PCIE_DISABLE_ASPM
491 select FSL_PCIE_RESET
492 select SYS_FSL_HAS_DDR3
493 select SYS_FSL_HAS_SEC
494 select SYS_FSL_SEC_BE
495 select SYS_FSL_SEC_COMPAT_2
496 select SYS_PPC_E500_USE_DEBUG_TLB
505 select SYS_CACHE_SHIFT_5
506 select SYS_FSL_ERRATUM_A004477
507 select SYS_FSL_ERRATUM_A004508
508 select SYS_FSL_ERRATUM_A005125
509 select SYS_FSL_ERRATUM_ESDHC111
510 select SYS_FSL_ERRATUM_ESDHC_A001
511 select FSL_PCIE_RESET
512 select SYS_FSL_HAS_DDR3
513 select SYS_FSL_HAS_SEC
514 select SYS_FSL_SEC_BE
515 select SYS_FSL_SEC_COMPAT_2
516 select SYS_PPC_E500_USE_DEBUG_TLB
527 select SYS_CACHE_SHIFT_6
528 select SYS_FSL_ERRATUM_A004510
529 select SYS_FSL_ERRATUM_A004849
530 select SYS_FSL_ERRATUM_A005275
531 select SYS_FSL_ERRATUM_A006261
532 select SYS_FSL_ERRATUM_CPU_A003999
533 select SYS_FSL_ERRATUM_DDR_A003
534 select SYS_FSL_ERRATUM_DDR_A003474
535 select SYS_FSL_ERRATUM_ESDHC111
536 select SYS_FSL_ERRATUM_I2C_A004447
537 select SYS_FSL_ERRATUM_NMG_CPU_A011
538 select SYS_FSL_ERRATUM_SRIO_A004034
539 select SYS_FSL_ERRATUM_USB14
540 select SYS_FSL_HAS_DDR3
541 select SYS_FSL_HAS_SEC
542 select SYS_FSL_QORIQ_CHASSIS1
543 select SYS_FSL_SEC_BE
544 select SYS_FSL_SEC_COMPAT_4
552 select SYS_CACHE_SHIFT_6
553 select SYS_FSL_DDR_VER_44
554 select SYS_FSL_ERRATUM_A004510
555 select SYS_FSL_ERRATUM_A004849
556 select SYS_FSL_ERRATUM_A005275
557 select SYS_FSL_ERRATUM_A005812
558 select SYS_FSL_ERRATUM_A006261
559 select SYS_FSL_ERRATUM_CPU_A003999
560 select SYS_FSL_ERRATUM_DDR_A003
561 select SYS_FSL_ERRATUM_DDR_A003474
562 select SYS_FSL_ERRATUM_ESDHC111
563 select SYS_FSL_ERRATUM_I2C_A004447
564 select SYS_FSL_ERRATUM_NMG_CPU_A011
565 select SYS_FSL_ERRATUM_SRIO_A004034
566 select SYS_FSL_ERRATUM_USB14
567 select SYS_FSL_HAS_DDR3
568 select SYS_FSL_HAS_SEC
569 select SYS_FSL_QORIQ_CHASSIS1
570 select SYS_FSL_SEC_BE
571 select SYS_FSL_SEC_COMPAT_4
582 select SYS_CACHE_SHIFT_6
583 select SYS_FSL_DDR_VER_44
584 select SYS_FSL_ERRATUM_A004510
585 select SYS_FSL_ERRATUM_A004580
586 select SYS_FSL_ERRATUM_A004849
587 select SYS_FSL_ERRATUM_A005812
588 select SYS_FSL_ERRATUM_A007075
589 select SYS_FSL_ERRATUM_CPC_A002
590 select SYS_FSL_ERRATUM_CPC_A003
591 select SYS_FSL_ERRATUM_CPU_A003999
592 select SYS_FSL_ERRATUM_DDR_A003
593 select SYS_FSL_ERRATUM_DDR_A003474
594 select SYS_FSL_ERRATUM_ELBC_A001
595 select SYS_FSL_ERRATUM_ESDHC111
596 select SYS_FSL_ERRATUM_ESDHC13
597 select SYS_FSL_ERRATUM_ESDHC135
598 select SYS_FSL_ERRATUM_I2C_A004447
599 select SYS_FSL_ERRATUM_NMG_CPU_A011
600 select SYS_FSL_ERRATUM_SRIO_A004034
601 select SYS_P4080_ERRATUM_CPU22
602 select SYS_P4080_ERRATUM_PCIE_A003
603 select SYS_P4080_ERRATUM_SERDES8
604 select SYS_P4080_ERRATUM_SERDES9
605 select SYS_P4080_ERRATUM_SERDES_A001
606 select SYS_P4080_ERRATUM_SERDES_A005
607 select SYS_FSL_HAS_DDR3
608 select SYS_FSL_HAS_SEC
609 select SYS_FSL_QORIQ_CHASSIS1
610 select SYS_FSL_SEC_BE
611 select SYS_FSL_SEC_COMPAT_4
621 select SYS_CACHE_SHIFT_6
622 select SYS_FSL_DDR_VER_44
623 select SYS_FSL_ERRATUM_A004510
624 select SYS_FSL_ERRATUM_A004699
625 select SYS_FSL_ERRATUM_A005275
626 select SYS_FSL_ERRATUM_A005812
627 select SYS_FSL_ERRATUM_A006261
628 select SYS_FSL_ERRATUM_DDR_A003
629 select SYS_FSL_ERRATUM_DDR_A003474
630 select SYS_FSL_ERRATUM_ESDHC111
631 select SYS_FSL_ERRATUM_USB14
632 select SYS_FSL_HAS_DDR3
633 select SYS_FSL_HAS_SEC
634 select SYS_FSL_QORIQ_CHASSIS1
635 select SYS_FSL_SEC_BE
636 select SYS_FSL_SEC_COMPAT_4
643 config ARCH_QEMU_E500
645 select SYS_CACHE_SHIFT_5
651 select SYS_CACHE_SHIFT_6
652 select SYS_FSL_DDR_VER_50
653 select SYS_FSL_ERRATUM_A008378
654 select SYS_FSL_ERRATUM_A008109
655 select SYS_FSL_ERRATUM_A009663
656 select SYS_FSL_ERRATUM_A009942
657 select SYS_FSL_ERRATUM_ESDHC111
658 select SYS_FSL_HAS_DDR3
659 select SYS_FSL_HAS_DDR4
660 select SYS_FSL_HAS_SEC
661 select SYS_FSL_QORIQ_CHASSIS2
662 select SYS_FSL_SEC_BE
663 select SYS_FSL_SEC_COMPAT_5
674 select SYS_CACHE_SHIFT_6
675 select SYS_FSL_DDR_VER_50
676 select SYS_FSL_ERRATUM_A008044
677 select SYS_FSL_ERRATUM_A008378
678 select SYS_FSL_ERRATUM_A008109
679 select SYS_FSL_ERRATUM_A009663
680 select SYS_FSL_ERRATUM_A009942
681 select SYS_FSL_ERRATUM_ESDHC111
682 select SYS_FSL_HAS_DDR3
683 select SYS_FSL_HAS_DDR4
684 select SYS_FSL_HAS_SEC
685 select SYS_FSL_QORIQ_CHASSIS2
686 select SYS_FSL_SEC_BE
687 select SYS_FSL_SEC_COMPAT_5
697 select SYS_CACHE_SHIFT_6
698 select SYS_FSL_DDR_VER_50
699 select SYS_FSL_ERRATUM_A008044
700 select SYS_FSL_ERRATUM_A008378
701 select SYS_FSL_ERRATUM_A008109
702 select SYS_FSL_ERRATUM_A009663
703 select SYS_FSL_ERRATUM_A009942
704 select SYS_FSL_ERRATUM_ESDHC111
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_DDR4
707 select SYS_FSL_HAS_SEC
708 select SYS_FSL_QORIQ_CHASSIS2
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_5
721 select SYS_CACHE_SHIFT_6
722 select SYS_FSL_DDR_VER_47
723 select SYS_FSL_ERRATUM_A006379
724 select SYS_FSL_ERRATUM_A006593
725 select SYS_FSL_ERRATUM_A007186
726 select SYS_FSL_ERRATUM_A007212
727 select SYS_FSL_ERRATUM_A007815
728 select SYS_FSL_ERRATUM_A007907
729 select SYS_FSL_ERRATUM_A008109
730 select SYS_FSL_ERRATUM_A009942
731 select SYS_FSL_ERRATUM_ESDHC111
732 select FSL_PCIE_RESET
733 select SYS_FSL_HAS_DDR3
734 select SYS_FSL_HAS_SEC
735 select SYS_FSL_QORIQ_CHASSIS2
736 select SYS_FSL_SEC_BE
737 select SYS_FSL_SEC_COMPAT_4
751 select SYS_CACHE_SHIFT_6
752 select SYS_FSL_DDR_VER_47
753 select SYS_FSL_ERRATUM_A004468
754 select SYS_FSL_ERRATUM_A005871
755 select SYS_FSL_ERRATUM_A006261
756 select SYS_FSL_ERRATUM_A006379
757 select SYS_FSL_ERRATUM_A006593
758 select SYS_FSL_ERRATUM_A007186
759 select SYS_FSL_ERRATUM_A007798
760 select SYS_FSL_ERRATUM_A007815
761 select SYS_FSL_ERRATUM_A007907
762 select SYS_FSL_ERRATUM_A008109
763 select SYS_FSL_ERRATUM_A009942
764 select SYS_FSL_HAS_DDR3
765 select SYS_FSL_HAS_SEC
766 select SYS_FSL_QORIQ_CHASSIS2
767 select SYS_FSL_SEC_BE
768 select SYS_FSL_SEC_COMPAT_4
776 config MPC85XX_HAVE_RESET_VECTOR
777 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
781 bool "toggle branch predition"
791 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
798 Enble PowerPC E500MC core
804 Enable PowerPC E6500 core
809 Use Freescale common code for Local Access Window
814 Enable Freescale Secure Boot feature. Normally selected
815 by defconfig. If unsure, do not change.
818 int "Maximum number of CPUs permitted for MPC85xx"
819 default 12 if ARCH_T4240
820 default 8 if ARCH_P4080
821 default 4 if ARCH_B4860 || \
828 default 2 if ARCH_B4420 || \
839 Set this number to the maximum number of possible CPUs in the SoC.
840 SoCs may have multiple clusters with each cluster may have multiple
841 ports. If some ports are reserved but higher ports are used for
842 cores, count the reserved ports. This will allocate enough memory
843 in spin table to properly handle all cores.
845 config SYS_CCSRBAR_DEFAULT
846 hex "Default CCSRBAR address"
847 default 0xff700000 if ARCH_BSC9131 || \
862 default 0xff600000 if ARCH_P1023
863 default 0xfe000000 if ARCH_B4420 || \
874 default 0xe0000000 if ARCH_QEMU_E500
876 Default value of CCSRBAR comes from power-on-reset. It
877 is fixed on each SoC. Some SoCs can have different value
878 if changed by pre-boot regime. The value here must match
879 the current value in SoC. If not sure, do not change.
881 config SYS_FSL_ERRATUM_A004468
884 config SYS_FSL_ERRATUM_A004477
887 config SYS_FSL_ERRATUM_A004508
890 config SYS_FSL_ERRATUM_A004580
893 config SYS_FSL_ERRATUM_A004699
896 config SYS_FSL_ERRATUM_A004849
899 config SYS_FSL_ERRATUM_A004510
902 config SYS_FSL_ERRATUM_A004510_SVR_REV
904 depends on SYS_FSL_ERRATUM_A004510
905 default 0x20 if ARCH_P4080
908 config SYS_FSL_ERRATUM_A004510_SVR_REV2
910 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
913 config SYS_FSL_ERRATUM_A005125
916 config SYS_FSL_ERRATUM_A005434
919 config SYS_FSL_ERRATUM_A005812
922 config SYS_FSL_ERRATUM_A005871
925 config SYS_FSL_ERRATUM_A005275
928 config SYS_FSL_ERRATUM_A006261
931 config SYS_FSL_ERRATUM_A006379
934 config SYS_FSL_ERRATUM_A006384
937 config SYS_FSL_ERRATUM_A006475
940 config SYS_FSL_ERRATUM_A006593
943 config SYS_FSL_ERRATUM_A007075
946 config SYS_FSL_ERRATUM_A007186
949 config SYS_FSL_ERRATUM_A007212
952 config SYS_FSL_ERRATUM_A007815
955 config SYS_FSL_ERRATUM_A007798
958 config SYS_FSL_ERRATUM_A007907
961 config SYS_FSL_ERRATUM_A008044
964 config SYS_FSL_ERRATUM_CPC_A002
967 config SYS_FSL_ERRATUM_CPC_A003
970 config SYS_FSL_ERRATUM_CPU_A003999
973 config SYS_FSL_ERRATUM_ELBC_A001
976 config SYS_FSL_ERRATUM_I2C_A004447
979 config SYS_FSL_A004447_SVR_REV
981 depends on SYS_FSL_ERRATUM_I2C_A004447
982 default 0x00 if ARCH_MPC8548
983 default 0x10 if ARCH_P1010
984 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
985 default 0x20 if ARCH_P3041 || ARCH_P4080
987 config SYS_FSL_ERRATUM_IFC_A002769
990 config SYS_FSL_ERRATUM_IFC_A003399
993 config SYS_FSL_ERRATUM_NMG_CPU_A011
996 config SYS_FSL_ERRATUM_NMG_ETSEC129
999 config SYS_FSL_ERRATUM_NMG_LBC103
1002 config SYS_FSL_ERRATUM_P1010_A003549
1005 config SYS_FSL_ERRATUM_SATA_A001
1008 config SYS_FSL_ERRATUM_SEC_A003571
1011 config SYS_FSL_ERRATUM_SRIO_A004034
1014 config SYS_FSL_ERRATUM_USB14
1017 config SYS_HAS_SERDES
1020 config SYS_P4080_ERRATUM_CPU22
1023 config SYS_P4080_ERRATUM_PCIE_A003
1026 config SYS_P4080_ERRATUM_SERDES8
1029 config SYS_P4080_ERRATUM_SERDES9
1032 config SYS_P4080_ERRATUM_SERDES_A001
1035 config SYS_P4080_ERRATUM_SERDES_A005
1038 config FSL_PCIE_DISABLE_ASPM
1041 config FSL_PCIE_RESET
1044 config SYS_FSL_QORIQ_CHASSIS1
1047 config SYS_FSL_QORIQ_CHASSIS2
1050 config SYS_FSL_NUM_LAWS
1051 int "Number of local access windows"
1053 default 32 if ARCH_B4420 || \
1061 default 16 if ARCH_T1024 || \
1064 default 12 if ARCH_BSC9131 || \
1076 default 10 if ARCH_MPC8544 || \
1078 default 8 if ARCH_MPC8540 || \
1081 Number of local access windows. This is fixed per SoC.
1082 If not sure, do not change.
1084 config SYS_FSL_THREADS_PER_CORE
1089 config SYS_NUM_TLBCAMS
1090 int "Number of TLB CAM entries"
1091 default 64 if E500MC
1094 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1095 16 for other E500 SoCs.
1100 config SYS_PPC_E500_USE_DEBUG_TLB
1106 config SYS_PPC_E500_DEBUG_TLB
1107 int "Temporary TLB entry for external debugger"
1108 depends on SYS_PPC_E500_USE_DEBUG_TLB
1109 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1110 default 1 if ARCH_MPC8536
1111 default 2 if ARCH_P1011 || \
1117 default 3 if ARCH_P1010 || \
1121 Select a temporary TLB entry to be used during boot to work
1122 around limitations in e500v1 and e500v2 external debugger
1123 support. This reduces the portions of the boot code where
1124 breakpoints and single stepping do not work. The value of this
1125 symbol should be set to the TLB1 entry to be used for this
1126 purpose. If unsure, do not change.
1128 config SYS_FSL_IFC_CLK_DIV
1129 int "Divider of platform clock"
1131 default 2 if ARCH_B4420 || \
1139 Defines divider of platform clock(clock input to
1142 config SYS_FSL_LBC_CLK_DIV
1143 int "Divider of platform clock"
1144 depends on FSL_ELBC || ARCH_MPC8540 || \
1148 default 2 if ARCH_P2041 || \
1155 Defines divider of platform clock(clock input to
1161 source "board/emulation/qemu-ppce500/Kconfig"
1162 source "board/freescale/corenet_ds/Kconfig"
1163 source "board/freescale/mpc8548cds/Kconfig"
1164 source "board/freescale/p1010rdb/Kconfig"
1165 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1166 source "board/freescale/p2041rdb/Kconfig"
1167 source "board/freescale/t102xrdb/Kconfig"
1168 source "board/freescale/t104xrdb/Kconfig"
1169 source "board/freescale/t208xqds/Kconfig"
1170 source "board/freescale/t208xrdb/Kconfig"
1171 source "board/freescale/t4rdb/Kconfig"
1172 source "board/keymile/Kconfig"
1173 source "board/socrates/Kconfig"