8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
27 config TARGET_B4420QDS
28 bool "Support B4420QDS"
34 config TARGET_B4860QDS
35 bool "Support B4860QDS"
37 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 select FSL_DDR_INTERACTIVE if !SPL_BUILD
43 config TARGET_BSC9131RDB
44 bool "Support BSC9131RDB"
47 select BOARD_EARLY_INIT_F
49 config TARGET_BSC9132QDS
50 bool "Support BSC9132QDS"
52 select BOARD_LATE_INIT if CHAIN_OF_TRUST
54 select BOARD_EARLY_INIT_F
55 select FSL_DDR_INTERACTIVE
57 config TARGET_C29XPCIE
58 bool "Support C29XPCIE"
60 select BOARD_LATE_INIT if CHAIN_OF_TRUST
67 bool "Support P3041DS"
70 select BOARD_LATE_INIT if CHAIN_OF_TRUST
75 bool "Support P4080DS"
78 select BOARD_LATE_INIT if CHAIN_OF_TRUST
83 bool "Support P5020DS"
86 select BOARD_LATE_INIT if CHAIN_OF_TRUST
91 bool "Support P5040DS"
94 select BOARD_LATE_INIT if CHAIN_OF_TRUST
98 config TARGET_MPC8536DS
99 bool "Support MPC8536DS"
101 # Use DDR3 controller with DDR2 DIMMs on this board
102 select SYS_FSL_DDRC_GEN3
106 config TARGET_MPC8541CDS
107 bool "Support MPC8541CDS"
110 config TARGET_MPC8544DS
111 bool "Support MPC8544DS"
115 config TARGET_MPC8548CDS
116 bool "Support MPC8548CDS"
119 config TARGET_MPC8555CDS
120 bool "Support MPC8555CDS"
123 config TARGET_MPC8568MDS
124 bool "Support MPC8568MDS"
127 config TARGET_MPC8569MDS
128 bool "Support MPC8569MDS"
131 config TARGET_MPC8572DS
132 bool "Support MPC8572DS"
134 # Use DDR3 controller with DDR2 DIMMs on this board
135 select SYS_FSL_DDRC_GEN3
139 config TARGET_P1010RDB_PA
140 bool "Support P1010RDB_PA"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
149 config TARGET_P1010RDB_PB
150 bool "Support P1010RDB_PB"
152 select BOARD_LATE_INIT if CHAIN_OF_TRUST
159 config TARGET_P1022DS
160 bool "Support P1022DS"
167 config TARGET_P1023RDB
168 bool "Support P1023RDB"
170 select FSL_DDR_INTERACTIVE
174 config TARGET_P1020MBG
175 bool "Support P1020MBG-PC"
183 config TARGET_P1020RDB_PC
184 bool "Support P1020RDB-PC"
192 config TARGET_P1020RDB_PD
193 bool "Support P1020RDB-PD"
201 config TARGET_P1020UTM
202 bool "Support P1020UTM"
210 config TARGET_P1021RDB
211 bool "Support P1021RDB"
219 config TARGET_P1024RDB
220 bool "Support P1024RDB"
228 config TARGET_P1025RDB
229 bool "Support P1025RDB"
237 config TARGET_P2020RDB
238 bool "Support P2020RDB-PC"
247 bool "Support p1_twr"
250 config TARGET_P2041RDB
251 bool "Support P2041RDB"
253 select BOARD_LATE_INIT if CHAIN_OF_TRUST
258 config TARGET_QEMU_PPCE500
259 bool "Support qemu-ppce500"
260 select ARCH_QEMU_E500
263 config TARGET_T1024QDS
264 bool "Support T1024QDS"
266 select BOARD_LATE_INIT if CHAIN_OF_TRUST
273 config TARGET_T1023RDB
274 bool "Support T1023RDB"
276 select BOARD_LATE_INIT if CHAIN_OF_TRUST
279 select FSL_DDR_INTERACTIVE
283 config TARGET_T1024RDB
284 bool "Support T1024RDB"
286 select BOARD_LATE_INIT if CHAIN_OF_TRUST
289 select FSL_DDR_INTERACTIVE
293 config TARGET_T1040QDS
294 bool "Support T1040QDS"
296 select BOARD_LATE_INIT if CHAIN_OF_TRUST
298 select FSL_DDR_INTERACTIVE
303 config TARGET_T1040RDB
304 bool "Support T1040RDB"
306 select BOARD_LATE_INIT if CHAIN_OF_TRUST
312 config TARGET_T1040D4RDB
313 bool "Support T1040D4RDB"
315 select BOARD_LATE_INIT if CHAIN_OF_TRUST
321 config TARGET_T1042RDB
322 bool "Support T1042RDB"
324 select BOARD_LATE_INIT if CHAIN_OF_TRUST
329 config TARGET_T1042D4RDB
330 bool "Support T1042D4RDB"
332 select BOARD_LATE_INIT if CHAIN_OF_TRUST
338 config TARGET_T1042RDB_PI
339 bool "Support T1042RDB_PI"
341 select BOARD_LATE_INIT if CHAIN_OF_TRUST
347 config TARGET_T2080QDS
348 bool "Support T2080QDS"
350 select BOARD_LATE_INIT if CHAIN_OF_TRUST
353 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
354 select FSL_DDR_INTERACTIVE
356 config TARGET_T2080RDB
357 bool "Support T2080RDB"
359 select BOARD_LATE_INIT if CHAIN_OF_TRUST
366 config TARGET_T2081QDS
367 bool "Support T2081QDS"
371 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
372 select FSL_DDR_INTERACTIVE
374 config TARGET_T4160QDS
375 bool "Support T4160QDS"
377 select BOARD_LATE_INIT if CHAIN_OF_TRUST
383 config TARGET_T4160RDB
384 bool "Support T4160RDB"
390 config TARGET_T4240QDS
391 bool "Support T4240QDS"
393 select BOARD_LATE_INIT if CHAIN_OF_TRUST
396 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
400 config TARGET_T4240RDB
401 bool "Support T4240RDB"
405 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
409 config TARGET_CONTROLCENTERD
410 bool "Support controlcenterd"
413 config TARGET_KMP204X
414 bool "Support kmp204x"
417 select FSL_DDR_INTERACTIVE
421 config TARGET_XPEDITE520X
422 bool "Support xpedite520x"
425 config TARGET_XPEDITE537X
426 bool "Support xpedite537x"
428 # Use DDR3 controller with DDR2 DIMMs on this board
429 select SYS_FSL_DDRC_GEN3
431 config TARGET_XPEDITE550X
432 bool "Support xpedite550x"
435 config TARGET_UCP1020
436 bool "Support uCP1020"
441 config TARGET_CYRUS_P5020
442 bool "Support Varisys Cyrus P5020"
447 config TARGET_CYRUS_P5040
448 bool "Support Varisys Cyrus P5040"
460 select SYS_FSL_DDR_VER_47
461 select SYS_FSL_ERRATUM_A004477
462 select SYS_FSL_ERRATUM_A005871
463 select SYS_FSL_ERRATUM_A006379
464 select SYS_FSL_ERRATUM_A006384
465 select SYS_FSL_ERRATUM_A006475
466 select SYS_FSL_ERRATUM_A006593
467 select SYS_FSL_ERRATUM_A007075
468 select SYS_FSL_ERRATUM_A007186
469 select SYS_FSL_ERRATUM_A007212
470 select SYS_FSL_ERRATUM_A009942
471 select SYS_FSL_HAS_DDR3
472 select SYS_FSL_HAS_SEC
473 select SYS_FSL_QORIQ_CHASSIS2
474 select SYS_FSL_SEC_BE
475 select SYS_FSL_SEC_COMPAT_4
487 select SYS_FSL_DDR_VER_47
488 select SYS_FSL_ERRATUM_A004477
489 select SYS_FSL_ERRATUM_A005871
490 select SYS_FSL_ERRATUM_A006379
491 select SYS_FSL_ERRATUM_A006384
492 select SYS_FSL_ERRATUM_A006475
493 select SYS_FSL_ERRATUM_A006593
494 select SYS_FSL_ERRATUM_A007075
495 select SYS_FSL_ERRATUM_A007186
496 select SYS_FSL_ERRATUM_A007212
497 select SYS_FSL_ERRATUM_A007907
498 select SYS_FSL_ERRATUM_A009942
499 select SYS_FSL_HAS_DDR3
500 select SYS_FSL_HAS_SEC
501 select SYS_FSL_QORIQ_CHASSIS2
502 select SYS_FSL_SEC_BE
503 select SYS_FSL_SEC_COMPAT_4
513 select SYS_FSL_DDR_VER_44
514 select SYS_FSL_ERRATUM_A004477
515 select SYS_FSL_ERRATUM_A005125
516 select SYS_FSL_ERRATUM_ESDHC111
517 select SYS_FSL_HAS_DDR3
518 select SYS_FSL_HAS_SEC
519 select SYS_FSL_SEC_BE
520 select SYS_FSL_SEC_COMPAT_4
529 select SYS_FSL_DDR_VER_46
530 select SYS_FSL_ERRATUM_A004477
531 select SYS_FSL_ERRATUM_A005125
532 select SYS_FSL_ERRATUM_A005434
533 select SYS_FSL_ERRATUM_ESDHC111
534 select SYS_FSL_ERRATUM_I2C_A004447
535 select SYS_FSL_ERRATUM_IFC_A002769
536 select FSL_PCIE_RESET
537 select SYS_FSL_HAS_DDR3
538 select SYS_FSL_HAS_SEC
539 select SYS_FSL_SEC_BE
540 select SYS_FSL_SEC_COMPAT_4
541 select SYS_PPC_E500_USE_DEBUG_TLB
552 select SYS_FSL_DDR_VER_46
553 select SYS_FSL_ERRATUM_A005125
554 select SYS_FSL_ERRATUM_ESDHC111
555 select FSL_PCIE_RESET
556 select SYS_FSL_HAS_DDR3
557 select SYS_FSL_HAS_SEC
558 select SYS_FSL_SEC_BE
559 select SYS_FSL_SEC_COMPAT_6
560 select SYS_PPC_E500_USE_DEBUG_TLB
569 select SYS_FSL_ERRATUM_A004508
570 select SYS_FSL_ERRATUM_A005125
571 select FSL_PCIE_RESET
572 select SYS_FSL_HAS_DDR2
573 select SYS_FSL_HAS_DDR3
574 select SYS_FSL_HAS_SEC
575 select SYS_FSL_SEC_BE
576 select SYS_FSL_SEC_COMPAT_2
577 select SYS_PPC_E500_USE_DEBUG_TLB
586 select SYS_FSL_HAS_DDR1
591 select SYS_FSL_HAS_DDR1
592 select SYS_FSL_HAS_SEC
593 select SYS_FSL_SEC_BE
594 select SYS_FSL_SEC_COMPAT_2
599 select SYS_FSL_ERRATUM_A005125
600 select FSL_PCIE_RESET
601 select SYS_FSL_HAS_DDR2
602 select SYS_FSL_HAS_SEC
603 select SYS_FSL_SEC_BE
604 select SYS_FSL_SEC_COMPAT_2
605 select SYS_PPC_E500_USE_DEBUG_TLB
611 select SYS_FSL_ERRATUM_A005125
612 select SYS_FSL_ERRATUM_NMG_DDR120
613 select SYS_FSL_ERRATUM_NMG_LBC103
614 select SYS_FSL_ERRATUM_NMG_ETSEC129
615 select SYS_FSL_ERRATUM_I2C_A004447
616 select FSL_PCIE_RESET
617 select SYS_FSL_HAS_DDR2
618 select SYS_FSL_HAS_DDR1
619 select SYS_FSL_HAS_SEC
620 select SYS_FSL_SEC_BE
621 select SYS_FSL_SEC_COMPAT_2
622 select SYS_PPC_E500_USE_DEBUG_TLB
628 select SYS_FSL_HAS_DDR1
629 select SYS_FSL_HAS_SEC
630 select SYS_FSL_SEC_BE
631 select SYS_FSL_SEC_COMPAT_2
636 select SYS_FSL_HAS_DDR1
641 select FSL_PCIE_RESET
642 select SYS_FSL_HAS_DDR2
643 select SYS_FSL_HAS_SEC
644 select SYS_FSL_SEC_BE
645 select SYS_FSL_SEC_COMPAT_2
650 select SYS_FSL_ERRATUM_A004508
651 select SYS_FSL_ERRATUM_A005125
652 select FSL_PCIE_RESET
653 select SYS_FSL_HAS_DDR3
654 select SYS_FSL_HAS_SEC
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_2
663 select SYS_FSL_ERRATUM_A004508
664 select SYS_FSL_ERRATUM_A005125
665 select SYS_FSL_ERRATUM_DDR_115
666 select SYS_FSL_ERRATUM_DDR111_DDR134
667 select FSL_PCIE_RESET
668 select SYS_FSL_HAS_DDR2
669 select SYS_FSL_HAS_DDR3
670 select SYS_FSL_HAS_SEC
671 select SYS_FSL_SEC_BE
672 select SYS_FSL_SEC_COMPAT_2
673 select SYS_PPC_E500_USE_DEBUG_TLB
680 select SYS_FSL_ERRATUM_A004477
681 select SYS_FSL_ERRATUM_A004508
682 select SYS_FSL_ERRATUM_A005125
683 select SYS_FSL_ERRATUM_A005275
684 select SYS_FSL_ERRATUM_A006261
685 select SYS_FSL_ERRATUM_A007075
686 select SYS_FSL_ERRATUM_ESDHC111
687 select SYS_FSL_ERRATUM_I2C_A004447
688 select SYS_FSL_ERRATUM_IFC_A002769
689 select SYS_FSL_ERRATUM_P1010_A003549
690 select SYS_FSL_ERRATUM_SEC_A003571
691 select SYS_FSL_ERRATUM_IFC_A003399
692 select FSL_PCIE_RESET
693 select SYS_FSL_HAS_DDR3
694 select SYS_FSL_HAS_SEC
695 select SYS_FSL_SEC_BE
696 select SYS_FSL_SEC_COMPAT_4
697 select SYS_PPC_E500_USE_DEBUG_TLB
710 select SYS_FSL_ERRATUM_A004508
711 select SYS_FSL_ERRATUM_A005125
712 select SYS_FSL_ERRATUM_ELBC_A001
713 select SYS_FSL_ERRATUM_ESDHC111
714 select FSL_PCIE_DISABLE_ASPM
715 select SYS_FSL_HAS_DDR3
716 select SYS_FSL_HAS_SEC
717 select SYS_FSL_SEC_BE
718 select SYS_FSL_SEC_COMPAT_2
719 select SYS_PPC_E500_USE_DEBUG_TLB
725 select SYS_FSL_ERRATUM_A004508
726 select SYS_FSL_ERRATUM_A005125
727 select SYS_FSL_ERRATUM_ELBC_A001
728 select SYS_FSL_ERRATUM_ESDHC111
729 select FSL_PCIE_DISABLE_ASPM
730 select FSL_PCIE_RESET
731 select SYS_FSL_HAS_DDR3
732 select SYS_FSL_HAS_SEC
733 select SYS_FSL_SEC_BE
734 select SYS_FSL_SEC_COMPAT_2
735 select SYS_PPC_E500_USE_DEBUG_TLB
746 select SYS_FSL_ERRATUM_A004508
747 select SYS_FSL_ERRATUM_A005125
748 select SYS_FSL_ERRATUM_ELBC_A001
749 select SYS_FSL_ERRATUM_ESDHC111
750 select FSL_PCIE_DISABLE_ASPM
751 select FSL_PCIE_RESET
752 select SYS_FSL_HAS_DDR3
753 select SYS_FSL_HAS_SEC
754 select SYS_FSL_SEC_BE
755 select SYS_FSL_SEC_COMPAT_2
756 select SYS_PPC_E500_USE_DEBUG_TLB
767 select SYS_FSL_ERRATUM_A004477
768 select SYS_FSL_ERRATUM_A004508
769 select SYS_FSL_ERRATUM_A005125
770 select SYS_FSL_ERRATUM_ELBC_A001
771 select SYS_FSL_ERRATUM_ESDHC111
772 select SYS_FSL_ERRATUM_SATA_A001
773 select FSL_PCIE_RESET
774 select SYS_FSL_HAS_DDR3
775 select SYS_FSL_HAS_SEC
776 select SYS_FSL_SEC_BE
777 select SYS_FSL_SEC_COMPAT_2
778 select SYS_PPC_E500_USE_DEBUG_TLB
784 select SYS_FSL_ERRATUM_A004508
785 select SYS_FSL_ERRATUM_A005125
786 select SYS_FSL_ERRATUM_I2C_A004447
787 select FSL_PCIE_RESET
788 select SYS_FSL_HAS_DDR3
789 select SYS_FSL_HAS_SEC
790 select SYS_FSL_SEC_BE
791 select SYS_FSL_SEC_COMPAT_4
797 select SYS_FSL_ERRATUM_A004508
798 select SYS_FSL_ERRATUM_A005125
799 select SYS_FSL_ERRATUM_ELBC_A001
800 select SYS_FSL_ERRATUM_ESDHC111
801 select FSL_PCIE_DISABLE_ASPM
802 select FSL_PCIE_RESET
803 select SYS_FSL_HAS_DDR3
804 select SYS_FSL_HAS_SEC
805 select SYS_FSL_SEC_BE
806 select SYS_FSL_SEC_COMPAT_2
807 select SYS_PPC_E500_USE_DEBUG_TLB
819 select SYS_FSL_ERRATUM_A004508
820 select SYS_FSL_ERRATUM_A005125
821 select SYS_FSL_ERRATUM_ELBC_A001
822 select SYS_FSL_ERRATUM_ESDHC111
823 select FSL_PCIE_DISABLE_ASPM
824 select FSL_PCIE_RESET
825 select SYS_FSL_HAS_DDR3
826 select SYS_FSL_HAS_SEC
827 select SYS_FSL_SEC_BE
828 select SYS_FSL_SEC_COMPAT_2
829 select SYS_PPC_E500_USE_DEBUG_TLB
837 select SYS_FSL_ERRATUM_A004477
838 select SYS_FSL_ERRATUM_A004508
839 select SYS_FSL_ERRATUM_A005125
840 select SYS_FSL_ERRATUM_ESDHC111
841 select SYS_FSL_ERRATUM_ESDHC_A001
842 select FSL_PCIE_RESET
843 select SYS_FSL_HAS_DDR3
844 select SYS_FSL_HAS_SEC
845 select SYS_FSL_SEC_BE
846 select SYS_FSL_SEC_COMPAT_2
847 select SYS_PPC_E500_USE_DEBUG_TLB
857 select SYS_FSL_ERRATUM_A004510
858 select SYS_FSL_ERRATUM_A004849
859 select SYS_FSL_ERRATUM_A005275
860 select SYS_FSL_ERRATUM_A006261
861 select SYS_FSL_ERRATUM_CPU_A003999
862 select SYS_FSL_ERRATUM_DDR_A003
863 select SYS_FSL_ERRATUM_DDR_A003474
864 select SYS_FSL_ERRATUM_ESDHC111
865 select SYS_FSL_ERRATUM_I2C_A004447
866 select SYS_FSL_ERRATUM_NMG_CPU_A011
867 select SYS_FSL_ERRATUM_SRIO_A004034
868 select SYS_FSL_ERRATUM_USB14
869 select SYS_FSL_HAS_DDR3
870 select SYS_FSL_HAS_SEC
871 select SYS_FSL_QORIQ_CHASSIS1
872 select SYS_FSL_SEC_BE
873 select SYS_FSL_SEC_COMPAT_4
881 select SYS_FSL_DDR_VER_44
882 select SYS_FSL_ERRATUM_A004510
883 select SYS_FSL_ERRATUM_A004849
884 select SYS_FSL_ERRATUM_A005275
885 select SYS_FSL_ERRATUM_A005812
886 select SYS_FSL_ERRATUM_A006261
887 select SYS_FSL_ERRATUM_CPU_A003999
888 select SYS_FSL_ERRATUM_DDR_A003
889 select SYS_FSL_ERRATUM_DDR_A003474
890 select SYS_FSL_ERRATUM_ESDHC111
891 select SYS_FSL_ERRATUM_I2C_A004447
892 select SYS_FSL_ERRATUM_NMG_CPU_A011
893 select SYS_FSL_ERRATUM_SRIO_A004034
894 select SYS_FSL_ERRATUM_USB14
895 select SYS_FSL_HAS_DDR3
896 select SYS_FSL_HAS_SEC
897 select SYS_FSL_QORIQ_CHASSIS1
898 select SYS_FSL_SEC_BE
899 select SYS_FSL_SEC_COMPAT_4
910 select SYS_FSL_DDR_VER_44
911 select SYS_FSL_ERRATUM_A004510
912 select SYS_FSL_ERRATUM_A004580
913 select SYS_FSL_ERRATUM_A004849
914 select SYS_FSL_ERRATUM_A005812
915 select SYS_FSL_ERRATUM_A007075
916 select SYS_FSL_ERRATUM_CPC_A002
917 select SYS_FSL_ERRATUM_CPC_A003
918 select SYS_FSL_ERRATUM_CPU_A003999
919 select SYS_FSL_ERRATUM_DDR_A003
920 select SYS_FSL_ERRATUM_DDR_A003474
921 select SYS_FSL_ERRATUM_ELBC_A001
922 select SYS_FSL_ERRATUM_ESDHC111
923 select SYS_FSL_ERRATUM_ESDHC13
924 select SYS_FSL_ERRATUM_ESDHC135
925 select SYS_FSL_ERRATUM_I2C_A004447
926 select SYS_FSL_ERRATUM_NMG_CPU_A011
927 select SYS_FSL_ERRATUM_SRIO_A004034
928 select SYS_P4080_ERRATUM_CPU22
929 select SYS_P4080_ERRATUM_PCIE_A003
930 select SYS_P4080_ERRATUM_SERDES8
931 select SYS_P4080_ERRATUM_SERDES9
932 select SYS_P4080_ERRATUM_SERDES_A001
933 select SYS_P4080_ERRATUM_SERDES_A005
934 select SYS_FSL_HAS_DDR3
935 select SYS_FSL_HAS_SEC
936 select SYS_FSL_QORIQ_CHASSIS1
937 select SYS_FSL_SEC_BE
938 select SYS_FSL_SEC_COMPAT_4
948 select SYS_FSL_DDR_VER_44
949 select SYS_FSL_ERRATUM_A004510
950 select SYS_FSL_ERRATUM_A005275
951 select SYS_FSL_ERRATUM_A006261
952 select SYS_FSL_ERRATUM_DDR_A003
953 select SYS_FSL_ERRATUM_DDR_A003474
954 select SYS_FSL_ERRATUM_ESDHC111
955 select SYS_FSL_ERRATUM_I2C_A004447
956 select SYS_FSL_ERRATUM_SRIO_A004034
957 select SYS_FSL_ERRATUM_USB14
958 select SYS_FSL_HAS_DDR3
959 select SYS_FSL_HAS_SEC
960 select SYS_FSL_QORIQ_CHASSIS1
961 select SYS_FSL_SEC_BE
962 select SYS_FSL_SEC_COMPAT_4
973 select SYS_FSL_DDR_VER_44
974 select SYS_FSL_ERRATUM_A004510
975 select SYS_FSL_ERRATUM_A004699
976 select SYS_FSL_ERRATUM_A005275
977 select SYS_FSL_ERRATUM_A005812
978 select SYS_FSL_ERRATUM_A006261
979 select SYS_FSL_ERRATUM_DDR_A003
980 select SYS_FSL_ERRATUM_DDR_A003474
981 select SYS_FSL_ERRATUM_ESDHC111
982 select SYS_FSL_ERRATUM_USB14
983 select SYS_FSL_HAS_DDR3
984 select SYS_FSL_HAS_SEC
985 select SYS_FSL_QORIQ_CHASSIS1
986 select SYS_FSL_SEC_BE
987 select SYS_FSL_SEC_COMPAT_4
994 config ARCH_QEMU_E500
1001 select SYS_FSL_DDR_VER_50
1002 select SYS_FSL_ERRATUM_A008378
1003 select SYS_FSL_ERRATUM_A009663
1004 select SYS_FSL_ERRATUM_A009942
1005 select SYS_FSL_ERRATUM_ESDHC111
1006 select SYS_FSL_HAS_DDR3
1007 select SYS_FSL_HAS_DDR4
1008 select SYS_FSL_HAS_SEC
1009 select SYS_FSL_QORIQ_CHASSIS2
1010 select SYS_FSL_SEC_BE
1011 select SYS_FSL_SEC_COMPAT_5
1021 select SYS_FSL_DDR_VER_50
1022 select SYS_FSL_ERRATUM_A008378
1023 select SYS_FSL_ERRATUM_A009663
1024 select SYS_FSL_ERRATUM_A009942
1025 select SYS_FSL_ERRATUM_ESDHC111
1026 select SYS_FSL_HAS_DDR3
1027 select SYS_FSL_HAS_DDR4
1028 select SYS_FSL_HAS_SEC
1029 select SYS_FSL_QORIQ_CHASSIS2
1030 select SYS_FSL_SEC_BE
1031 select SYS_FSL_SEC_COMPAT_5
1042 select SYS_FSL_DDR_VER_50
1043 select SYS_FSL_ERRATUM_A008044
1044 select SYS_FSL_ERRATUM_A008378
1045 select SYS_FSL_ERRATUM_A009663
1046 select SYS_FSL_ERRATUM_A009942
1047 select SYS_FSL_ERRATUM_ESDHC111
1048 select SYS_FSL_HAS_DDR3
1049 select SYS_FSL_HAS_DDR4
1050 select SYS_FSL_HAS_SEC
1051 select SYS_FSL_QORIQ_CHASSIS2
1052 select SYS_FSL_SEC_BE
1053 select SYS_FSL_SEC_COMPAT_5
1065 select SYS_FSL_DDR_VER_50
1066 select SYS_FSL_ERRATUM_A008044
1067 select SYS_FSL_ERRATUM_A008378
1068 select SYS_FSL_ERRATUM_A009663
1069 select SYS_FSL_ERRATUM_A009942
1070 select SYS_FSL_ERRATUM_ESDHC111
1071 select SYS_FSL_HAS_DDR3
1072 select SYS_FSL_HAS_DDR4
1073 select SYS_FSL_HAS_SEC
1074 select SYS_FSL_QORIQ_CHASSIS2
1075 select SYS_FSL_SEC_BE
1076 select SYS_FSL_SEC_COMPAT_5
1089 select SYS_FSL_DDR_VER_47
1090 select SYS_FSL_ERRATUM_A006379
1091 select SYS_FSL_ERRATUM_A006593
1092 select SYS_FSL_ERRATUM_A007186
1093 select SYS_FSL_ERRATUM_A007212
1094 select SYS_FSL_ERRATUM_A007815
1095 select SYS_FSL_ERRATUM_A007907
1096 select SYS_FSL_ERRATUM_A009942
1097 select SYS_FSL_ERRATUM_ESDHC111
1098 select FSL_PCIE_RESET
1099 select SYS_FSL_HAS_DDR3
1100 select SYS_FSL_HAS_SEC
1101 select SYS_FSL_QORIQ_CHASSIS2
1102 select SYS_FSL_SEC_BE
1103 select SYS_FSL_SEC_COMPAT_4
1114 select SYS_FSL_DDR_VER_47
1115 select SYS_FSL_ERRATUM_A006379
1116 select SYS_FSL_ERRATUM_A006593
1117 select SYS_FSL_ERRATUM_A007186
1118 select SYS_FSL_ERRATUM_A007212
1119 select SYS_FSL_ERRATUM_A009942
1120 select SYS_FSL_ERRATUM_ESDHC111
1121 select FSL_PCIE_RESET
1122 select SYS_FSL_HAS_DDR3
1123 select SYS_FSL_HAS_SEC
1124 select SYS_FSL_QORIQ_CHASSIS2
1125 select SYS_FSL_SEC_BE
1126 select SYS_FSL_SEC_COMPAT_4
1137 select SYS_FSL_DDR_VER_47
1138 select SYS_FSL_ERRATUM_A004468
1139 select SYS_FSL_ERRATUM_A005871
1140 select SYS_FSL_ERRATUM_A006379
1141 select SYS_FSL_ERRATUM_A006593
1142 select SYS_FSL_ERRATUM_A007186
1143 select SYS_FSL_ERRATUM_A007798
1144 select SYS_FSL_ERRATUM_A009942
1145 select SYS_FSL_HAS_DDR3
1146 select SYS_FSL_HAS_SEC
1147 select SYS_FSL_QORIQ_CHASSIS2
1148 select SYS_FSL_SEC_BE
1149 select SYS_FSL_SEC_COMPAT_4
1162 select SYS_FSL_DDR_VER_47
1163 select SYS_FSL_ERRATUM_A004468
1164 select SYS_FSL_ERRATUM_A005871
1165 select SYS_FSL_ERRATUM_A006261
1166 select SYS_FSL_ERRATUM_A006379
1167 select SYS_FSL_ERRATUM_A006593
1168 select SYS_FSL_ERRATUM_A007186
1169 select SYS_FSL_ERRATUM_A007798
1170 select SYS_FSL_ERRATUM_A007815
1171 select SYS_FSL_ERRATUM_A007907
1172 select SYS_FSL_ERRATUM_A009942
1173 select SYS_FSL_HAS_DDR3
1174 select SYS_FSL_HAS_SEC
1175 select SYS_FSL_QORIQ_CHASSIS2
1176 select SYS_FSL_SEC_BE
1177 select SYS_FSL_SEC_COMPAT_4
1185 config MPC85XX_HAVE_RESET_VECTOR
1186 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1197 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1203 Enble PowerPC E500MC core
1208 Enable PowerPC E6500 core
1213 Use Freescale common code for Local Access Window
1218 Enable Freescale Secure Boot feature. Normally selected
1219 by defconfig. If unsure, do not change.
1222 int "Maximum number of CPUs permitted for MPC85xx"
1223 default 12 if ARCH_T4240
1224 default 8 if ARCH_P4080 || \
1226 default 4 if ARCH_B4860 || \
1234 default 2 if ARCH_B4420 || \
1249 Set this number to the maximum number of possible CPUs in the SoC.
1250 SoCs may have multiple clusters with each cluster may have multiple
1251 ports. If some ports are reserved but higher ports are used for
1252 cores, count the reserved ports. This will allocate enough memory
1253 in spin table to properly handle all cores.
1255 config SYS_CCSRBAR_DEFAULT
1256 hex "Default CCSRBAR address"
1257 default 0xff700000 if ARCH_BSC9131 || \
1278 default 0xff600000 if ARCH_P1023
1279 default 0xfe000000 if ARCH_B4420 || \
1294 default 0xe0000000 if ARCH_QEMU_E500
1296 Default value of CCSRBAR comes from power-on-reset. It
1297 is fixed on each SoC. Some SoCs can have different value
1298 if changed by pre-boot regime. The value here must match
1299 the current value in SoC. If not sure, do not change.
1301 config SYS_FSL_ERRATUM_A004468
1304 config SYS_FSL_ERRATUM_A004477
1307 config SYS_FSL_ERRATUM_A004508
1310 config SYS_FSL_ERRATUM_A004580
1313 config SYS_FSL_ERRATUM_A004699
1316 config SYS_FSL_ERRATUM_A004849
1319 config SYS_FSL_ERRATUM_A004510
1322 config SYS_FSL_ERRATUM_A004510_SVR_REV
1324 depends on SYS_FSL_ERRATUM_A004510
1325 default 0x20 if ARCH_P4080
1328 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1330 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1333 config SYS_FSL_ERRATUM_A005125
1336 config SYS_FSL_ERRATUM_A005434
1339 config SYS_FSL_ERRATUM_A005812
1342 config SYS_FSL_ERRATUM_A005871
1345 config SYS_FSL_ERRATUM_A005275
1348 config SYS_FSL_ERRATUM_A006261
1351 config SYS_FSL_ERRATUM_A006379
1354 config SYS_FSL_ERRATUM_A006384
1357 config SYS_FSL_ERRATUM_A006475
1360 config SYS_FSL_ERRATUM_A006593
1363 config SYS_FSL_ERRATUM_A007075
1366 config SYS_FSL_ERRATUM_A007186
1369 config SYS_FSL_ERRATUM_A007212
1372 config SYS_FSL_ERRATUM_A007815
1375 config SYS_FSL_ERRATUM_A007798
1378 config SYS_FSL_ERRATUM_A007907
1381 config SYS_FSL_ERRATUM_A008044
1384 config SYS_FSL_ERRATUM_CPC_A002
1387 config SYS_FSL_ERRATUM_CPC_A003
1390 config SYS_FSL_ERRATUM_CPU_A003999
1393 config SYS_FSL_ERRATUM_ELBC_A001
1396 config SYS_FSL_ERRATUM_I2C_A004447
1399 config SYS_FSL_A004447_SVR_REV
1401 depends on SYS_FSL_ERRATUM_I2C_A004447
1402 default 0x00 if ARCH_MPC8548
1403 default 0x10 if ARCH_P1010
1404 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1405 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1407 config SYS_FSL_ERRATUM_IFC_A002769
1410 config SYS_FSL_ERRATUM_IFC_A003399
1413 config SYS_FSL_ERRATUM_NMG_CPU_A011
1416 config SYS_FSL_ERRATUM_NMG_ETSEC129
1419 config SYS_FSL_ERRATUM_NMG_LBC103
1422 config SYS_FSL_ERRATUM_P1010_A003549
1425 config SYS_FSL_ERRATUM_SATA_A001
1428 config SYS_FSL_ERRATUM_SEC_A003571
1431 config SYS_FSL_ERRATUM_SRIO_A004034
1434 config SYS_FSL_ERRATUM_USB14
1437 config SYS_P4080_ERRATUM_CPU22
1440 config SYS_P4080_ERRATUM_PCIE_A003
1443 config SYS_P4080_ERRATUM_SERDES8
1446 config SYS_P4080_ERRATUM_SERDES9
1449 config SYS_P4080_ERRATUM_SERDES_A001
1452 config SYS_P4080_ERRATUM_SERDES_A005
1455 config FSL_PCIE_DISABLE_ASPM
1458 config FSL_PCIE_RESET
1461 config SYS_FSL_QORIQ_CHASSIS1
1464 config SYS_FSL_QORIQ_CHASSIS2
1467 config SYS_FSL_NUM_LAWS
1468 int "Number of local access windows"
1470 default 32 if ARCH_B4420 || \
1481 default 16 if ARCH_T1023 || \
1485 default 12 if ARCH_BSC9131 || \
1499 default 10 if ARCH_MPC8544 || \
1503 default 8 if ARCH_MPC8540 || \
1508 Number of local access windows. This is fixed per SoC.
1509 If not sure, do not change.
1511 config SYS_FSL_THREADS_PER_CORE
1516 config SYS_NUM_TLBCAMS
1517 int "Number of TLB CAM entries"
1518 default 64 if E500MC
1521 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1522 16 for other E500 SoCs.
1527 config SYS_PPC_E500_USE_DEBUG_TLB
1536 config SYS_PPC_E500_DEBUG_TLB
1537 int "Temporary TLB entry for external debugger"
1538 depends on SYS_PPC_E500_USE_DEBUG_TLB
1539 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1540 default 1 if ARCH_MPC8536
1541 default 2 if ARCH_MPC8572 || \
1549 default 3 if ARCH_P1010 || \
1553 Select a temporary TLB entry to be used during boot to work
1554 around limitations in e500v1 and e500v2 external debugger
1555 support. This reduces the portions of the boot code where
1556 breakpoints and single stepping do not work. The value of this
1557 symbol should be set to the TLB1 entry to be used for this
1558 purpose. If unsure, do not change.
1560 config SYS_FSL_IFC_CLK_DIV
1561 int "Divider of platform clock"
1563 default 2 if ARCH_B4420 || \
1573 Defines divider of platform clock(clock input to
1576 config SYS_FSL_LBC_CLK_DIV
1577 int "Divider of platform clock"
1578 depends on FSL_ELBC || ARCH_MPC8540 || \
1579 ARCH_MPC8548 || ARCH_MPC8541 || \
1580 ARCH_MPC8555 || ARCH_MPC8560 || \
1583 default 2 if ARCH_P2041 || \
1591 Defines divider of platform clock(clock input to
1594 source "board/freescale/b4860qds/Kconfig"
1595 source "board/freescale/bsc9131rdb/Kconfig"
1596 source "board/freescale/bsc9132qds/Kconfig"
1597 source "board/freescale/c29xpcie/Kconfig"
1598 source "board/freescale/corenet_ds/Kconfig"
1599 source "board/freescale/mpc8536ds/Kconfig"
1600 source "board/freescale/mpc8541cds/Kconfig"
1601 source "board/freescale/mpc8544ds/Kconfig"
1602 source "board/freescale/mpc8548cds/Kconfig"
1603 source "board/freescale/mpc8555cds/Kconfig"
1604 source "board/freescale/mpc8568mds/Kconfig"
1605 source "board/freescale/mpc8569mds/Kconfig"
1606 source "board/freescale/mpc8572ds/Kconfig"
1607 source "board/freescale/p1010rdb/Kconfig"
1608 source "board/freescale/p1022ds/Kconfig"
1609 source "board/freescale/p1023rdb/Kconfig"
1610 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1611 source "board/freescale/p1_twr/Kconfig"
1612 source "board/freescale/p2041rdb/Kconfig"
1613 source "board/freescale/qemu-ppce500/Kconfig"
1614 source "board/freescale/t102xqds/Kconfig"
1615 source "board/freescale/t102xrdb/Kconfig"
1616 source "board/freescale/t1040qds/Kconfig"
1617 source "board/freescale/t104xrdb/Kconfig"
1618 source "board/freescale/t208xqds/Kconfig"
1619 source "board/freescale/t208xrdb/Kconfig"
1620 source "board/freescale/t4qds/Kconfig"
1621 source "board/freescale/t4rdb/Kconfig"
1622 source "board/gdsys/p1022/Kconfig"
1623 source "board/keymile/kmp204x/Kconfig"
1624 source "board/sbc8548/Kconfig"
1625 source "board/socrates/Kconfig"
1626 source "board/varisys/cyrus/Kconfig"
1627 source "board/xes/xpedite520x/Kconfig"
1628 source "board/xes/xpedite537x/Kconfig"
1629 source "board/xes/xpedite550x/Kconfig"
1630 source "board/Arcturus/ucp1020/Kconfig"