8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
51 select SYS_CACHE_SHIFT_5
53 config TARGET_P1010RDB_PA
54 bool "Support P1010RDB_PA"
56 select BOARD_LATE_INIT if CHAIN_OF_TRUST
63 config TARGET_P1010RDB_PB
64 bool "Support P1010RDB_PB"
66 select BOARD_LATE_INIT if CHAIN_OF_TRUST
73 config TARGET_P1020RDB_PC
74 bool "Support P1020RDB-PC"
82 config TARGET_P1020RDB_PD
83 bool "Support P1020RDB-PD"
91 config TARGET_P2020RDB
92 bool "Support P2020RDB-PC"
100 config TARGET_P2041RDB
101 bool "Support P2041RDB"
103 select BOARD_LATE_INIT if CHAIN_OF_TRUST
108 config TARGET_QEMU_PPCE500
109 bool "Support qemu-ppce500"
110 select ARCH_QEMU_E500
112 imply OF_HAS_PRIOR_STAGE
114 config TARGET_T1024RDB
115 bool "Support T1024RDB"
117 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 select FSL_DDR_INTERACTIVE
124 config TARGET_T1042RDB
125 bool "Support T1042RDB"
127 select BOARD_LATE_INIT if CHAIN_OF_TRUST
131 config TARGET_T1042D4RDB
132 bool "Support T1042D4RDB"
134 select BOARD_LATE_INIT if CHAIN_OF_TRUST
139 config TARGET_T1042RDB_PI
140 bool "Support T1042RDB_PI"
142 select BOARD_LATE_INIT if CHAIN_OF_TRUST
147 config TARGET_T2080QDS
148 bool "Support T2080QDS"
150 select BOARD_LATE_INIT if CHAIN_OF_TRUST
153 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
154 select FSL_DDR_INTERACTIVE
157 config TARGET_T2080RDB
158 bool "Support T2080RDB"
160 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_T4240RDB
167 bool "Support T4240RDB"
171 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
175 config TARGET_KMP204X
176 bool "Support kmp204x"
179 config TARGET_KMCENT2
180 bool "Support kmcent2"
190 select SYS_FSL_DDR_VER_47
191 select SYS_FSL_ERRATUM_A004477
192 select SYS_FSL_ERRATUM_A005871
193 select SYS_FSL_ERRATUM_A006379
194 select SYS_FSL_ERRATUM_A006384
195 select SYS_FSL_ERRATUM_A006475
196 select SYS_FSL_ERRATUM_A006593
197 select SYS_FSL_ERRATUM_A007075
198 select SYS_FSL_ERRATUM_A007186
199 select SYS_FSL_ERRATUM_A007212
200 select SYS_FSL_ERRATUM_A009942
201 select SYS_FSL_HAS_DDR3
202 select SYS_FSL_HAS_SEC
203 select SYS_FSL_QORIQ_CHASSIS2
204 select SYS_FSL_SEC_BE
205 select SYS_FSL_SEC_COMPAT_4
217 select SYS_FSL_DDR_VER_47
218 select SYS_FSL_ERRATUM_A004477
219 select SYS_FSL_ERRATUM_A005871
220 select SYS_FSL_ERRATUM_A006379
221 select SYS_FSL_ERRATUM_A006384
222 select SYS_FSL_ERRATUM_A006475
223 select SYS_FSL_ERRATUM_A006593
224 select SYS_FSL_ERRATUM_A007075
225 select SYS_FSL_ERRATUM_A007186
226 select SYS_FSL_ERRATUM_A007212
227 select SYS_FSL_ERRATUM_A007907
228 select SYS_FSL_ERRATUM_A009942
229 select SYS_FSL_HAS_DDR3
230 select SYS_FSL_HAS_SEC
231 select SYS_FSL_QORIQ_CHASSIS2
232 select SYS_FSL_SEC_BE
233 select SYS_FSL_SEC_COMPAT_4
243 select SYS_FSL_DDR_VER_44
244 select SYS_FSL_ERRATUM_A004477
245 select SYS_FSL_ERRATUM_A005125
246 select SYS_FSL_ERRATUM_ESDHC111
247 select SYS_FSL_HAS_DDR3
248 select SYS_FSL_HAS_SEC
249 select SYS_FSL_SEC_BE
250 select SYS_FSL_SEC_COMPAT_4
259 select SYS_FSL_DDR_VER_46
260 select SYS_FSL_ERRATUM_A004477
261 select SYS_FSL_ERRATUM_A005125
262 select SYS_FSL_ERRATUM_A005434
263 select SYS_FSL_ERRATUM_ESDHC111
264 select SYS_FSL_ERRATUM_I2C_A004447
265 select SYS_FSL_ERRATUM_IFC_A002769
266 select FSL_PCIE_RESET
267 select SYS_FSL_HAS_DDR3
268 select SYS_FSL_HAS_SEC
269 select SYS_FSL_SEC_BE
270 select SYS_FSL_SEC_COMPAT_4
271 select SYS_PPC_E500_USE_DEBUG_TLB
282 select SYS_FSL_DDR_VER_46
283 select SYS_FSL_ERRATUM_A005125
284 select SYS_FSL_ERRATUM_ESDHC111
285 select FSL_PCIE_RESET
286 select SYS_FSL_HAS_DDR3
287 select SYS_FSL_HAS_SEC
288 select SYS_FSL_SEC_BE
289 select SYS_FSL_SEC_COMPAT_6
290 select SYS_PPC_E500_USE_DEBUG_TLB
299 select SYS_FSL_ERRATUM_A004508
300 select SYS_FSL_ERRATUM_A005125
301 select FSL_PCIE_RESET
302 select SYS_FSL_HAS_DDR2
303 select SYS_FSL_HAS_DDR3
304 select SYS_FSL_HAS_SEC
305 select SYS_FSL_SEC_BE
306 select SYS_FSL_SEC_COMPAT_2
307 select SYS_PPC_E500_USE_DEBUG_TLB
316 select SYS_FSL_HAS_DDR1
321 select SYS_CACHE_SHIFT_5
322 select SYS_FSL_ERRATUM_A005125
323 select FSL_PCIE_RESET
324 select SYS_FSL_HAS_DDR2
325 select SYS_FSL_HAS_SEC
326 select SYS_FSL_SEC_BE
327 select SYS_FSL_SEC_COMPAT_2
328 select SYS_PPC_E500_USE_DEBUG_TLB
334 select SYS_FSL_ERRATUM_A005125
335 select SYS_FSL_ERRATUM_NMG_DDR120
336 select SYS_FSL_ERRATUM_NMG_LBC103
337 select SYS_FSL_ERRATUM_NMG_ETSEC129
338 select SYS_FSL_ERRATUM_I2C_A004447
339 select FSL_PCIE_RESET
340 select SYS_FSL_HAS_DDR2
341 select SYS_FSL_HAS_DDR1
342 select SYS_FSL_HAS_SEC
343 select SYS_FSL_SEC_BE
344 select SYS_FSL_SEC_COMPAT_2
345 select SYS_PPC_E500_USE_DEBUG_TLB
351 select SYS_FSL_HAS_DDR1
356 select SYS_CACHE_SHIFT_5
357 select SYS_HAS_SERDES
358 select SYS_FSL_ERRATUM_A004477
359 select SYS_FSL_ERRATUM_A004508
360 select SYS_FSL_ERRATUM_A005125
361 select SYS_FSL_ERRATUM_A005275
362 select SYS_FSL_ERRATUM_A006261
363 select SYS_FSL_ERRATUM_A007075
364 select SYS_FSL_ERRATUM_ESDHC111
365 select SYS_FSL_ERRATUM_I2C_A004447
366 select SYS_FSL_ERRATUM_IFC_A002769
367 select SYS_FSL_ERRATUM_P1010_A003549
368 select SYS_FSL_ERRATUM_SEC_A003571
369 select SYS_FSL_ERRATUM_IFC_A003399
370 select FSL_PCIE_RESET
371 select SYS_FSL_HAS_DDR3
372 select SYS_FSL_HAS_SEC
373 select SYS_FSL_SEC_BE
374 select SYS_FSL_SEC_COMPAT_4
375 select SYS_PPC_E500_USE_DEBUG_TLB
389 select SYS_FSL_ERRATUM_A004508
390 select SYS_FSL_ERRATUM_A005125
391 select SYS_FSL_ERRATUM_ELBC_A001
392 select SYS_FSL_ERRATUM_ESDHC111
393 select FSL_PCIE_DISABLE_ASPM
394 select SYS_FSL_HAS_DDR3
395 select SYS_FSL_HAS_SEC
396 select SYS_FSL_SEC_BE
397 select SYS_FSL_SEC_COMPAT_2
398 select SYS_PPC_E500_USE_DEBUG_TLB
404 select SYS_CACHE_SHIFT_5
405 select SYS_FSL_ERRATUM_A004508
406 select SYS_FSL_ERRATUM_A005125
407 select SYS_FSL_ERRATUM_ELBC_A001
408 select SYS_FSL_ERRATUM_ESDHC111
409 select FSL_PCIE_DISABLE_ASPM
410 select FSL_PCIE_RESET
411 select SYS_FSL_HAS_DDR3
412 select SYS_FSL_HAS_SEC
413 select SYS_FSL_SEC_BE
414 select SYS_FSL_SEC_COMPAT_2
415 select SYS_PPC_E500_USE_DEBUG_TLB
426 select SYS_FSL_ERRATUM_A004508
427 select SYS_FSL_ERRATUM_A005125
428 select SYS_FSL_ERRATUM_ELBC_A001
429 select SYS_FSL_ERRATUM_ESDHC111
430 select FSL_PCIE_DISABLE_ASPM
431 select FSL_PCIE_RESET
432 select SYS_FSL_HAS_DDR3
433 select SYS_FSL_HAS_SEC
434 select SYS_FSL_SEC_BE
435 select SYS_FSL_SEC_COMPAT_2
436 select SYS_PPC_E500_USE_DEBUG_TLB
447 select SYS_FSL_ERRATUM_A004508
448 select SYS_FSL_ERRATUM_A005125
449 select SYS_FSL_ERRATUM_I2C_A004447
450 select FSL_PCIE_RESET
451 select SYS_FSL_HAS_DDR3
452 select SYS_FSL_HAS_SEC
453 select SYS_FSL_SEC_BE
454 select SYS_FSL_SEC_COMPAT_4
460 select SYS_FSL_ERRATUM_A004508
461 select SYS_FSL_ERRATUM_A005125
462 select SYS_FSL_ERRATUM_ELBC_A001
463 select SYS_FSL_ERRATUM_ESDHC111
464 select FSL_PCIE_DISABLE_ASPM
465 select FSL_PCIE_RESET
466 select SYS_FSL_HAS_DDR3
467 select SYS_FSL_HAS_SEC
468 select SYS_FSL_SEC_BE
469 select SYS_FSL_SEC_COMPAT_2
470 select SYS_PPC_E500_USE_DEBUG_TLB
482 select SYS_FSL_ERRATUM_A004508
483 select SYS_FSL_ERRATUM_A005125
484 select SYS_FSL_ERRATUM_ELBC_A001
485 select SYS_FSL_ERRATUM_ESDHC111
486 select FSL_PCIE_DISABLE_ASPM
487 select FSL_PCIE_RESET
488 select SYS_FSL_HAS_DDR3
489 select SYS_FSL_HAS_SEC
490 select SYS_FSL_SEC_BE
491 select SYS_FSL_SEC_COMPAT_2
492 select SYS_PPC_E500_USE_DEBUG_TLB
500 select SYS_CACHE_SHIFT_5
501 select SYS_FSL_ERRATUM_A004477
502 select SYS_FSL_ERRATUM_A004508
503 select SYS_FSL_ERRATUM_A005125
504 select SYS_FSL_ERRATUM_ESDHC111
505 select SYS_FSL_ERRATUM_ESDHC_A001
506 select FSL_PCIE_RESET
507 select SYS_FSL_HAS_DDR3
508 select SYS_FSL_HAS_SEC
509 select SYS_FSL_SEC_BE
510 select SYS_FSL_SEC_COMPAT_2
511 select SYS_PPC_E500_USE_DEBUG_TLB
522 select SYS_CACHE_SHIFT_6
523 select SYS_FSL_ERRATUM_A004510
524 select SYS_FSL_ERRATUM_A004849
525 select SYS_FSL_ERRATUM_A005275
526 select SYS_FSL_ERRATUM_A006261
527 select SYS_FSL_ERRATUM_CPU_A003999
528 select SYS_FSL_ERRATUM_DDR_A003
529 select SYS_FSL_ERRATUM_DDR_A003474
530 select SYS_FSL_ERRATUM_ESDHC111
531 select SYS_FSL_ERRATUM_I2C_A004447
532 select SYS_FSL_ERRATUM_NMG_CPU_A011
533 select SYS_FSL_ERRATUM_SRIO_A004034
534 select SYS_FSL_ERRATUM_USB14
535 select SYS_FSL_HAS_DDR3
536 select SYS_FSL_HAS_SEC
537 select SYS_FSL_QORIQ_CHASSIS1
538 select SYS_FSL_SEC_BE
539 select SYS_FSL_SEC_COMPAT_4
547 select SYS_CACHE_SHIFT_6
548 select SYS_FSL_DDR_VER_44
549 select SYS_FSL_ERRATUM_A004510
550 select SYS_FSL_ERRATUM_A004849
551 select SYS_FSL_ERRATUM_A005275
552 select SYS_FSL_ERRATUM_A005812
553 select SYS_FSL_ERRATUM_A006261
554 select SYS_FSL_ERRATUM_CPU_A003999
555 select SYS_FSL_ERRATUM_DDR_A003
556 select SYS_FSL_ERRATUM_DDR_A003474
557 select SYS_FSL_ERRATUM_ESDHC111
558 select SYS_FSL_ERRATUM_I2C_A004447
559 select SYS_FSL_ERRATUM_NMG_CPU_A011
560 select SYS_FSL_ERRATUM_SRIO_A004034
561 select SYS_FSL_ERRATUM_USB14
562 select SYS_FSL_HAS_DDR3
563 select SYS_FSL_HAS_SEC
564 select SYS_FSL_QORIQ_CHASSIS1
565 select SYS_FSL_SEC_BE
566 select SYS_FSL_SEC_COMPAT_4
577 select SYS_CACHE_SHIFT_6
578 select SYS_FSL_DDR_VER_44
579 select SYS_FSL_ERRATUM_A004510
580 select SYS_FSL_ERRATUM_A004580
581 select SYS_FSL_ERRATUM_A004849
582 select SYS_FSL_ERRATUM_A005812
583 select SYS_FSL_ERRATUM_A007075
584 select SYS_FSL_ERRATUM_CPC_A002
585 select SYS_FSL_ERRATUM_CPC_A003
586 select SYS_FSL_ERRATUM_CPU_A003999
587 select SYS_FSL_ERRATUM_DDR_A003
588 select SYS_FSL_ERRATUM_DDR_A003474
589 select SYS_FSL_ERRATUM_ELBC_A001
590 select SYS_FSL_ERRATUM_ESDHC111
591 select SYS_FSL_ERRATUM_ESDHC13
592 select SYS_FSL_ERRATUM_ESDHC135
593 select SYS_FSL_ERRATUM_I2C_A004447
594 select SYS_FSL_ERRATUM_NMG_CPU_A011
595 select SYS_FSL_ERRATUM_SRIO_A004034
596 select SYS_P4080_ERRATUM_CPU22
597 select SYS_P4080_ERRATUM_PCIE_A003
598 select SYS_P4080_ERRATUM_SERDES8
599 select SYS_P4080_ERRATUM_SERDES9
600 select SYS_P4080_ERRATUM_SERDES_A001
601 select SYS_P4080_ERRATUM_SERDES_A005
602 select SYS_FSL_HAS_DDR3
603 select SYS_FSL_HAS_SEC
604 select SYS_FSL_QORIQ_CHASSIS1
605 select SYS_FSL_SEC_BE
606 select SYS_FSL_SEC_COMPAT_4
616 select SYS_CACHE_SHIFT_6
617 select SYS_FSL_DDR_VER_44
618 select SYS_FSL_ERRATUM_A004510
619 select SYS_FSL_ERRATUM_A004699
620 select SYS_FSL_ERRATUM_A005275
621 select SYS_FSL_ERRATUM_A005812
622 select SYS_FSL_ERRATUM_A006261
623 select SYS_FSL_ERRATUM_DDR_A003
624 select SYS_FSL_ERRATUM_DDR_A003474
625 select SYS_FSL_ERRATUM_ESDHC111
626 select SYS_FSL_ERRATUM_USB14
627 select SYS_FSL_HAS_DDR3
628 select SYS_FSL_HAS_SEC
629 select SYS_FSL_QORIQ_CHASSIS1
630 select SYS_FSL_SEC_BE
631 select SYS_FSL_SEC_COMPAT_4
638 config ARCH_QEMU_E500
640 select SYS_CACHE_SHIFT_5
646 select SYS_CACHE_SHIFT_6
647 select SYS_FSL_DDR_VER_50
648 select SYS_FSL_ERRATUM_A008378
649 select SYS_FSL_ERRATUM_A008109
650 select SYS_FSL_ERRATUM_A009663
651 select SYS_FSL_ERRATUM_A009942
652 select SYS_FSL_ERRATUM_ESDHC111
653 select SYS_FSL_HAS_DDR3
654 select SYS_FSL_HAS_DDR4
655 select SYS_FSL_HAS_SEC
656 select SYS_FSL_QORIQ_CHASSIS2
657 select SYS_FSL_SEC_BE
658 select SYS_FSL_SEC_COMPAT_5
669 select SYS_CACHE_SHIFT_6
670 select SYS_FSL_DDR_VER_50
671 select SYS_FSL_ERRATUM_A008044
672 select SYS_FSL_ERRATUM_A008378
673 select SYS_FSL_ERRATUM_A008109
674 select SYS_FSL_ERRATUM_A009663
675 select SYS_FSL_ERRATUM_A009942
676 select SYS_FSL_ERRATUM_ESDHC111
677 select SYS_FSL_HAS_DDR3
678 select SYS_FSL_HAS_DDR4
679 select SYS_FSL_HAS_SEC
680 select SYS_FSL_QORIQ_CHASSIS2
681 select SYS_FSL_SEC_BE
682 select SYS_FSL_SEC_COMPAT_5
692 select SYS_CACHE_SHIFT_6
693 select SYS_FSL_DDR_VER_50
694 select SYS_FSL_ERRATUM_A008044
695 select SYS_FSL_ERRATUM_A008378
696 select SYS_FSL_ERRATUM_A008109
697 select SYS_FSL_ERRATUM_A009663
698 select SYS_FSL_ERRATUM_A009942
699 select SYS_FSL_ERRATUM_ESDHC111
700 select SYS_FSL_HAS_DDR3
701 select SYS_FSL_HAS_DDR4
702 select SYS_FSL_HAS_SEC
703 select SYS_FSL_QORIQ_CHASSIS2
704 select SYS_FSL_SEC_BE
705 select SYS_FSL_SEC_COMPAT_5
716 select SYS_CACHE_SHIFT_6
717 select SYS_FSL_DDR_VER_47
718 select SYS_FSL_ERRATUM_A006379
719 select SYS_FSL_ERRATUM_A006593
720 select SYS_FSL_ERRATUM_A007186
721 select SYS_FSL_ERRATUM_A007212
722 select SYS_FSL_ERRATUM_A007815
723 select SYS_FSL_ERRATUM_A007907
724 select SYS_FSL_ERRATUM_A008109
725 select SYS_FSL_ERRATUM_A009942
726 select SYS_FSL_ERRATUM_ESDHC111
727 select FSL_PCIE_RESET
728 select SYS_FSL_HAS_DDR3
729 select SYS_FSL_HAS_SEC
730 select SYS_FSL_QORIQ_CHASSIS2
731 select SYS_FSL_SEC_BE
732 select SYS_FSL_SEC_COMPAT_4
746 select SYS_CACHE_SHIFT_6
747 select SYS_FSL_DDR_VER_47
748 select SYS_FSL_ERRATUM_A004468
749 select SYS_FSL_ERRATUM_A005871
750 select SYS_FSL_ERRATUM_A006261
751 select SYS_FSL_ERRATUM_A006379
752 select SYS_FSL_ERRATUM_A006593
753 select SYS_FSL_ERRATUM_A007186
754 select SYS_FSL_ERRATUM_A007798
755 select SYS_FSL_ERRATUM_A007815
756 select SYS_FSL_ERRATUM_A007907
757 select SYS_FSL_ERRATUM_A008109
758 select SYS_FSL_ERRATUM_A009942
759 select SYS_FSL_HAS_DDR3
760 select SYS_FSL_HAS_SEC
761 select SYS_FSL_QORIQ_CHASSIS2
762 select SYS_FSL_SEC_BE
763 select SYS_FSL_SEC_COMPAT_4
771 config MPC85XX_HAVE_RESET_VECTOR
772 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
783 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
789 Enble PowerPC E500MC core
794 Enable PowerPC E6500 core
799 Use Freescale common code for Local Access Window
804 Enable Freescale Secure Boot feature. Normally selected
805 by defconfig. If unsure, do not change.
808 int "Maximum number of CPUs permitted for MPC85xx"
809 default 12 if ARCH_T4240
810 default 8 if ARCH_P4080
811 default 4 if ARCH_B4860 || \
818 default 2 if ARCH_B4420 || \
829 Set this number to the maximum number of possible CPUs in the SoC.
830 SoCs may have multiple clusters with each cluster may have multiple
831 ports. If some ports are reserved but higher ports are used for
832 cores, count the reserved ports. This will allocate enough memory
833 in spin table to properly handle all cores.
835 config SYS_CCSRBAR_DEFAULT
836 hex "Default CCSRBAR address"
837 default 0xff700000 if ARCH_BSC9131 || \
852 default 0xff600000 if ARCH_P1023
853 default 0xfe000000 if ARCH_B4420 || \
864 default 0xe0000000 if ARCH_QEMU_E500
866 Default value of CCSRBAR comes from power-on-reset. It
867 is fixed on each SoC. Some SoCs can have different value
868 if changed by pre-boot regime. The value here must match
869 the current value in SoC. If not sure, do not change.
871 config SYS_FSL_ERRATUM_A004468
874 config SYS_FSL_ERRATUM_A004477
877 config SYS_FSL_ERRATUM_A004508
880 config SYS_FSL_ERRATUM_A004580
883 config SYS_FSL_ERRATUM_A004699
886 config SYS_FSL_ERRATUM_A004849
889 config SYS_FSL_ERRATUM_A004510
892 config SYS_FSL_ERRATUM_A004510_SVR_REV
894 depends on SYS_FSL_ERRATUM_A004510
895 default 0x20 if ARCH_P4080
898 config SYS_FSL_ERRATUM_A004510_SVR_REV2
900 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
903 config SYS_FSL_ERRATUM_A005125
906 config SYS_FSL_ERRATUM_A005434
909 config SYS_FSL_ERRATUM_A005812
912 config SYS_FSL_ERRATUM_A005871
915 config SYS_FSL_ERRATUM_A005275
918 config SYS_FSL_ERRATUM_A006261
921 config SYS_FSL_ERRATUM_A006379
924 config SYS_FSL_ERRATUM_A006384
927 config SYS_FSL_ERRATUM_A006475
930 config SYS_FSL_ERRATUM_A006593
933 config SYS_FSL_ERRATUM_A007075
936 config SYS_FSL_ERRATUM_A007186
939 config SYS_FSL_ERRATUM_A007212
942 config SYS_FSL_ERRATUM_A007815
945 config SYS_FSL_ERRATUM_A007798
948 config SYS_FSL_ERRATUM_A007907
951 config SYS_FSL_ERRATUM_A008044
954 config SYS_FSL_ERRATUM_CPC_A002
957 config SYS_FSL_ERRATUM_CPC_A003
960 config SYS_FSL_ERRATUM_CPU_A003999
963 config SYS_FSL_ERRATUM_ELBC_A001
966 config SYS_FSL_ERRATUM_I2C_A004447
969 config SYS_FSL_A004447_SVR_REV
971 depends on SYS_FSL_ERRATUM_I2C_A004447
972 default 0x00 if ARCH_MPC8548
973 default 0x10 if ARCH_P1010
974 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
975 default 0x20 if ARCH_P3041 || ARCH_P4080
977 config SYS_FSL_ERRATUM_IFC_A002769
980 config SYS_FSL_ERRATUM_IFC_A003399
983 config SYS_FSL_ERRATUM_NMG_CPU_A011
986 config SYS_FSL_ERRATUM_NMG_ETSEC129
989 config SYS_FSL_ERRATUM_NMG_LBC103
992 config SYS_FSL_ERRATUM_P1010_A003549
995 config SYS_FSL_ERRATUM_SATA_A001
998 config SYS_FSL_ERRATUM_SEC_A003571
1001 config SYS_FSL_ERRATUM_SRIO_A004034
1004 config SYS_FSL_ERRATUM_USB14
1007 config SYS_HAS_SERDES
1010 config SYS_P4080_ERRATUM_CPU22
1013 config SYS_P4080_ERRATUM_PCIE_A003
1016 config SYS_P4080_ERRATUM_SERDES8
1019 config SYS_P4080_ERRATUM_SERDES9
1022 config SYS_P4080_ERRATUM_SERDES_A001
1025 config SYS_P4080_ERRATUM_SERDES_A005
1028 config FSL_PCIE_DISABLE_ASPM
1031 config FSL_PCIE_RESET
1034 config SYS_FSL_QORIQ_CHASSIS1
1037 config SYS_FSL_QORIQ_CHASSIS2
1040 config SYS_FSL_NUM_LAWS
1041 int "Number of local access windows"
1043 default 32 if ARCH_B4420 || \
1051 default 16 if ARCH_T1024 || \
1054 default 12 if ARCH_BSC9131 || \
1066 default 10 if ARCH_MPC8544 || \
1068 default 8 if ARCH_MPC8540 || \
1071 Number of local access windows. This is fixed per SoC.
1072 If not sure, do not change.
1074 config SYS_FSL_THREADS_PER_CORE
1079 config SYS_NUM_TLBCAMS
1080 int "Number of TLB CAM entries"
1081 default 64 if E500MC
1084 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1085 16 for other E500 SoCs.
1090 config SYS_PPC_E500_USE_DEBUG_TLB
1096 config SYS_PPC_E500_DEBUG_TLB
1097 int "Temporary TLB entry for external debugger"
1098 depends on SYS_PPC_E500_USE_DEBUG_TLB
1099 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1100 default 1 if ARCH_MPC8536
1101 default 2 if ARCH_P1011 || \
1107 default 3 if ARCH_P1010 || \
1111 Select a temporary TLB entry to be used during boot to work
1112 around limitations in e500v1 and e500v2 external debugger
1113 support. This reduces the portions of the boot code where
1114 breakpoints and single stepping do not work. The value of this
1115 symbol should be set to the TLB1 entry to be used for this
1116 purpose. If unsure, do not change.
1118 config SYS_FSL_IFC_CLK_DIV
1119 int "Divider of platform clock"
1121 default 2 if ARCH_B4420 || \
1129 Defines divider of platform clock(clock input to
1132 config SYS_FSL_LBC_CLK_DIV
1133 int "Divider of platform clock"
1134 depends on FSL_ELBC || ARCH_MPC8540 || \
1138 default 2 if ARCH_P2041 || \
1145 Defines divider of platform clock(clock input to
1151 source "board/emulation/qemu-ppce500/Kconfig"
1152 source "board/freescale/corenet_ds/Kconfig"
1153 source "board/freescale/mpc8548cds/Kconfig"
1154 source "board/freescale/p1010rdb/Kconfig"
1155 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1156 source "board/freescale/p2041rdb/Kconfig"
1157 source "board/freescale/t102xrdb/Kconfig"
1158 source "board/freescale/t104xrdb/Kconfig"
1159 source "board/freescale/t208xqds/Kconfig"
1160 source "board/freescale/t208xrdb/Kconfig"
1161 source "board/freescale/t4rdb/Kconfig"
1162 source "board/keymile/Kconfig"
1163 source "board/socrates/Kconfig"