8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1020MBG
113 bool "Support P1020MBG-PC"
121 config TARGET_P1020RDB_PC
122 bool "Support P1020RDB-PC"
130 config TARGET_P1020RDB_PD
131 bool "Support P1020RDB-PD"
139 config TARGET_P1021RDB
140 bool "Support P1021RDB"
148 config TARGET_P1024RDB
149 bool "Support P1024RDB"
157 config TARGET_P2020RDB
158 bool "Support P2020RDB-PC"
166 config TARGET_P2041RDB
167 bool "Support P2041RDB"
169 select BOARD_LATE_INIT if CHAIN_OF_TRUST
174 config TARGET_QEMU_PPCE500
175 bool "Support qemu-ppce500"
176 select ARCH_QEMU_E500
179 config TARGET_T1023RDB
180 bool "Support T1023RDB"
182 select BOARD_LATE_INIT if CHAIN_OF_TRUST
185 select FSL_DDR_INTERACTIVE
189 config TARGET_T1024RDB
190 bool "Support T1024RDB"
192 select BOARD_LATE_INIT if CHAIN_OF_TRUST
195 select FSL_DDR_INTERACTIVE
199 config TARGET_T1040RDB
200 bool "Support T1040RDB"
202 select BOARD_LATE_INIT if CHAIN_OF_TRUST
208 config TARGET_T1040D4RDB
209 bool "Support T1040D4RDB"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
217 config TARGET_T1042RDB
218 bool "Support T1042RDB"
220 select BOARD_LATE_INIT if CHAIN_OF_TRUST
225 config TARGET_T1042D4RDB
226 bool "Support T1042D4RDB"
228 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_T1042RDB_PI
235 bool "Support T1042RDB_PI"
237 select BOARD_LATE_INIT if CHAIN_OF_TRUST
243 config TARGET_T2080QDS
244 bool "Support T2080QDS"
246 select BOARD_LATE_INIT if CHAIN_OF_TRUST
249 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
250 select FSL_DDR_INTERACTIVE
253 config TARGET_T2080RDB
254 bool "Support T2080RDB"
256 select BOARD_LATE_INIT if CHAIN_OF_TRUST
262 config TARGET_T2081QDS
263 bool "Support T2081QDS"
267 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
268 select FSL_DDR_INTERACTIVE
270 config TARGET_T4160RDB
271 bool "Support T4160RDB"
277 config TARGET_T4240RDB
278 bool "Support T4240RDB"
282 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
286 config TARGET_CONTROLCENTERD
287 bool "Support controlcenterd"
290 config TARGET_KMP204X
291 bool "Support kmp204x"
294 config TARGET_XPEDITE520X
295 bool "Support xpedite520x"
298 config TARGET_XPEDITE537X
299 bool "Support xpedite537x"
301 # Use DDR3 controller with DDR2 DIMMs on this board
302 select SYS_FSL_DDRC_GEN3
304 config TARGET_XPEDITE550X
305 bool "Support xpedite550x"
308 config TARGET_UCP1020
309 bool "Support uCP1020"
314 config TARGET_CYRUS_P5020
315 bool "Support Varisys Cyrus P5020"
320 config TARGET_CYRUS_P5040
321 bool "Support Varisys Cyrus P5040"
333 select SYS_FSL_DDR_VER_47
334 select SYS_FSL_ERRATUM_A004477
335 select SYS_FSL_ERRATUM_A005871
336 select SYS_FSL_ERRATUM_A006379
337 select SYS_FSL_ERRATUM_A006384
338 select SYS_FSL_ERRATUM_A006475
339 select SYS_FSL_ERRATUM_A006593
340 select SYS_FSL_ERRATUM_A007075
341 select SYS_FSL_ERRATUM_A007186
342 select SYS_FSL_ERRATUM_A007212
343 select SYS_FSL_ERRATUM_A009942
344 select SYS_FSL_HAS_DDR3
345 select SYS_FSL_HAS_SEC
346 select SYS_FSL_QORIQ_CHASSIS2
347 select SYS_FSL_SEC_BE
348 select SYS_FSL_SEC_COMPAT_4
360 select SYS_FSL_DDR_VER_47
361 select SYS_FSL_ERRATUM_A004477
362 select SYS_FSL_ERRATUM_A005871
363 select SYS_FSL_ERRATUM_A006379
364 select SYS_FSL_ERRATUM_A006384
365 select SYS_FSL_ERRATUM_A006475
366 select SYS_FSL_ERRATUM_A006593
367 select SYS_FSL_ERRATUM_A007075
368 select SYS_FSL_ERRATUM_A007186
369 select SYS_FSL_ERRATUM_A007212
370 select SYS_FSL_ERRATUM_A007907
371 select SYS_FSL_ERRATUM_A009942
372 select SYS_FSL_HAS_DDR3
373 select SYS_FSL_HAS_SEC
374 select SYS_FSL_QORIQ_CHASSIS2
375 select SYS_FSL_SEC_BE
376 select SYS_FSL_SEC_COMPAT_4
386 select SYS_FSL_DDR_VER_44
387 select SYS_FSL_ERRATUM_A004477
388 select SYS_FSL_ERRATUM_A005125
389 select SYS_FSL_ERRATUM_ESDHC111
390 select SYS_FSL_HAS_DDR3
391 select SYS_FSL_HAS_SEC
392 select SYS_FSL_SEC_BE
393 select SYS_FSL_SEC_COMPAT_4
402 select SYS_FSL_DDR_VER_46
403 select SYS_FSL_ERRATUM_A004477
404 select SYS_FSL_ERRATUM_A005125
405 select SYS_FSL_ERRATUM_A005434
406 select SYS_FSL_ERRATUM_ESDHC111
407 select SYS_FSL_ERRATUM_I2C_A004447
408 select SYS_FSL_ERRATUM_IFC_A002769
409 select FSL_PCIE_RESET
410 select SYS_FSL_HAS_DDR3
411 select SYS_FSL_HAS_SEC
412 select SYS_FSL_SEC_BE
413 select SYS_FSL_SEC_COMPAT_4
414 select SYS_PPC_E500_USE_DEBUG_TLB
425 select SYS_FSL_DDR_VER_46
426 select SYS_FSL_ERRATUM_A005125
427 select SYS_FSL_ERRATUM_ESDHC111
428 select FSL_PCIE_RESET
429 select SYS_FSL_HAS_DDR3
430 select SYS_FSL_HAS_SEC
431 select SYS_FSL_SEC_BE
432 select SYS_FSL_SEC_COMPAT_6
433 select SYS_PPC_E500_USE_DEBUG_TLB
442 select SYS_FSL_ERRATUM_A004508
443 select SYS_FSL_ERRATUM_A005125
444 select FSL_PCIE_RESET
445 select SYS_FSL_HAS_DDR2
446 select SYS_FSL_HAS_DDR3
447 select SYS_FSL_HAS_SEC
448 select SYS_FSL_SEC_BE
449 select SYS_FSL_SEC_COMPAT_2
450 select SYS_PPC_E500_USE_DEBUG_TLB
459 select SYS_FSL_HAS_DDR1
464 select SYS_FSL_HAS_DDR1
465 select SYS_FSL_HAS_SEC
466 select SYS_FSL_SEC_BE
467 select SYS_FSL_SEC_COMPAT_2
472 select SYS_FSL_ERRATUM_A005125
473 select FSL_PCIE_RESET
474 select SYS_FSL_HAS_DDR2
475 select SYS_FSL_HAS_SEC
476 select SYS_FSL_SEC_BE
477 select SYS_FSL_SEC_COMPAT_2
478 select SYS_PPC_E500_USE_DEBUG_TLB
484 select SYS_FSL_ERRATUM_A005125
485 select SYS_FSL_ERRATUM_NMG_DDR120
486 select SYS_FSL_ERRATUM_NMG_LBC103
487 select SYS_FSL_ERRATUM_NMG_ETSEC129
488 select SYS_FSL_ERRATUM_I2C_A004447
489 select FSL_PCIE_RESET
490 select SYS_FSL_HAS_DDR2
491 select SYS_FSL_HAS_DDR1
492 select SYS_FSL_HAS_SEC
493 select SYS_FSL_SEC_BE
494 select SYS_FSL_SEC_COMPAT_2
495 select SYS_PPC_E500_USE_DEBUG_TLB
501 select SYS_FSL_HAS_DDR1
502 select SYS_FSL_HAS_SEC
503 select SYS_FSL_SEC_BE
504 select SYS_FSL_SEC_COMPAT_2
509 select SYS_FSL_HAS_DDR1
514 select FSL_PCIE_RESET
515 select SYS_FSL_HAS_DDR2
516 select SYS_FSL_HAS_SEC
517 select SYS_FSL_SEC_BE
518 select SYS_FSL_SEC_COMPAT_2
523 select SYS_FSL_ERRATUM_A004508
524 select SYS_FSL_ERRATUM_A005125
525 select FSL_PCIE_RESET
526 select SYS_FSL_HAS_DDR3
527 select SYS_FSL_HAS_SEC
528 select SYS_FSL_SEC_BE
529 select SYS_FSL_SEC_COMPAT_2
536 select SYS_FSL_ERRATUM_A004508
537 select SYS_FSL_ERRATUM_A005125
538 select SYS_FSL_ERRATUM_DDR_115
539 select SYS_FSL_ERRATUM_DDR111_DDR134
540 select FSL_PCIE_RESET
541 select SYS_FSL_HAS_DDR2
542 select SYS_FSL_HAS_DDR3
543 select SYS_FSL_HAS_SEC
544 select SYS_FSL_SEC_BE
545 select SYS_FSL_SEC_COMPAT_2
546 select SYS_PPC_E500_USE_DEBUG_TLB
553 select SYS_FSL_ERRATUM_A004477
554 select SYS_FSL_ERRATUM_A004508
555 select SYS_FSL_ERRATUM_A005125
556 select SYS_FSL_ERRATUM_A005275
557 select SYS_FSL_ERRATUM_A006261
558 select SYS_FSL_ERRATUM_A007075
559 select SYS_FSL_ERRATUM_ESDHC111
560 select SYS_FSL_ERRATUM_I2C_A004447
561 select SYS_FSL_ERRATUM_IFC_A002769
562 select SYS_FSL_ERRATUM_P1010_A003549
563 select SYS_FSL_ERRATUM_SEC_A003571
564 select SYS_FSL_ERRATUM_IFC_A003399
565 select FSL_PCIE_RESET
566 select SYS_FSL_HAS_DDR3
567 select SYS_FSL_HAS_SEC
568 select SYS_FSL_SEC_BE
569 select SYS_FSL_SEC_COMPAT_4
570 select SYS_PPC_E500_USE_DEBUG_TLB
583 select SYS_FSL_ERRATUM_A004508
584 select SYS_FSL_ERRATUM_A005125
585 select SYS_FSL_ERRATUM_ELBC_A001
586 select SYS_FSL_ERRATUM_ESDHC111
587 select FSL_PCIE_DISABLE_ASPM
588 select SYS_FSL_HAS_DDR3
589 select SYS_FSL_HAS_SEC
590 select SYS_FSL_SEC_BE
591 select SYS_FSL_SEC_COMPAT_2
592 select SYS_PPC_E500_USE_DEBUG_TLB
598 select SYS_FSL_ERRATUM_A004508
599 select SYS_FSL_ERRATUM_A005125
600 select SYS_FSL_ERRATUM_ELBC_A001
601 select SYS_FSL_ERRATUM_ESDHC111
602 select FSL_PCIE_DISABLE_ASPM
603 select FSL_PCIE_RESET
604 select SYS_FSL_HAS_DDR3
605 select SYS_FSL_HAS_SEC
606 select SYS_FSL_SEC_BE
607 select SYS_FSL_SEC_COMPAT_2
608 select SYS_PPC_E500_USE_DEBUG_TLB
619 select SYS_FSL_ERRATUM_A004508
620 select SYS_FSL_ERRATUM_A005125
621 select SYS_FSL_ERRATUM_ELBC_A001
622 select SYS_FSL_ERRATUM_ESDHC111
623 select FSL_PCIE_DISABLE_ASPM
624 select FSL_PCIE_RESET
625 select SYS_FSL_HAS_DDR3
626 select SYS_FSL_HAS_SEC
627 select SYS_FSL_SEC_BE
628 select SYS_FSL_SEC_COMPAT_2
629 select SYS_PPC_E500_USE_DEBUG_TLB
640 select SYS_FSL_ERRATUM_A004477
641 select SYS_FSL_ERRATUM_A004508
642 select SYS_FSL_ERRATUM_A005125
643 select SYS_FSL_ERRATUM_ELBC_A001
644 select SYS_FSL_ERRATUM_ESDHC111
645 select SYS_FSL_ERRATUM_SATA_A001
646 select FSL_PCIE_RESET
647 select SYS_FSL_HAS_DDR3
648 select SYS_FSL_HAS_SEC
649 select SYS_FSL_SEC_BE
650 select SYS_FSL_SEC_COMPAT_2
651 select SYS_PPC_E500_USE_DEBUG_TLB
657 select SYS_FSL_ERRATUM_A004508
658 select SYS_FSL_ERRATUM_A005125
659 select SYS_FSL_ERRATUM_I2C_A004447
660 select FSL_PCIE_RESET
661 select SYS_FSL_HAS_DDR3
662 select SYS_FSL_HAS_SEC
663 select SYS_FSL_SEC_BE
664 select SYS_FSL_SEC_COMPAT_4
670 select SYS_FSL_ERRATUM_A004508
671 select SYS_FSL_ERRATUM_A005125
672 select SYS_FSL_ERRATUM_ELBC_A001
673 select SYS_FSL_ERRATUM_ESDHC111
674 select FSL_PCIE_DISABLE_ASPM
675 select FSL_PCIE_RESET
676 select SYS_FSL_HAS_DDR3
677 select SYS_FSL_HAS_SEC
678 select SYS_FSL_SEC_BE
679 select SYS_FSL_SEC_COMPAT_2
680 select SYS_PPC_E500_USE_DEBUG_TLB
692 select SYS_FSL_ERRATUM_A004508
693 select SYS_FSL_ERRATUM_A005125
694 select SYS_FSL_ERRATUM_ELBC_A001
695 select SYS_FSL_ERRATUM_ESDHC111
696 select FSL_PCIE_DISABLE_ASPM
697 select FSL_PCIE_RESET
698 select SYS_FSL_HAS_DDR3
699 select SYS_FSL_HAS_SEC
700 select SYS_FSL_SEC_BE
701 select SYS_FSL_SEC_COMPAT_2
702 select SYS_PPC_E500_USE_DEBUG_TLB
710 select SYS_FSL_ERRATUM_A004477
711 select SYS_FSL_ERRATUM_A004508
712 select SYS_FSL_ERRATUM_A005125
713 select SYS_FSL_ERRATUM_ESDHC111
714 select SYS_FSL_ERRATUM_ESDHC_A001
715 select FSL_PCIE_RESET
716 select SYS_FSL_HAS_DDR3
717 select SYS_FSL_HAS_SEC
718 select SYS_FSL_SEC_BE
719 select SYS_FSL_SEC_COMPAT_2
720 select SYS_PPC_E500_USE_DEBUG_TLB
730 select SYS_FSL_ERRATUM_A004510
731 select SYS_FSL_ERRATUM_A004849
732 select SYS_FSL_ERRATUM_A005275
733 select SYS_FSL_ERRATUM_A006261
734 select SYS_FSL_ERRATUM_CPU_A003999
735 select SYS_FSL_ERRATUM_DDR_A003
736 select SYS_FSL_ERRATUM_DDR_A003474
737 select SYS_FSL_ERRATUM_ESDHC111
738 select SYS_FSL_ERRATUM_I2C_A004447
739 select SYS_FSL_ERRATUM_NMG_CPU_A011
740 select SYS_FSL_ERRATUM_SRIO_A004034
741 select SYS_FSL_ERRATUM_USB14
742 select SYS_FSL_HAS_DDR3
743 select SYS_FSL_HAS_SEC
744 select SYS_FSL_QORIQ_CHASSIS1
745 select SYS_FSL_SEC_BE
746 select SYS_FSL_SEC_COMPAT_4
754 select SYS_FSL_DDR_VER_44
755 select SYS_FSL_ERRATUM_A004510
756 select SYS_FSL_ERRATUM_A004849
757 select SYS_FSL_ERRATUM_A005275
758 select SYS_FSL_ERRATUM_A005812
759 select SYS_FSL_ERRATUM_A006261
760 select SYS_FSL_ERRATUM_CPU_A003999
761 select SYS_FSL_ERRATUM_DDR_A003
762 select SYS_FSL_ERRATUM_DDR_A003474
763 select SYS_FSL_ERRATUM_ESDHC111
764 select SYS_FSL_ERRATUM_I2C_A004447
765 select SYS_FSL_ERRATUM_NMG_CPU_A011
766 select SYS_FSL_ERRATUM_SRIO_A004034
767 select SYS_FSL_ERRATUM_USB14
768 select SYS_FSL_HAS_DDR3
769 select SYS_FSL_HAS_SEC
770 select SYS_FSL_QORIQ_CHASSIS1
771 select SYS_FSL_SEC_BE
772 select SYS_FSL_SEC_COMPAT_4
783 select SYS_FSL_DDR_VER_44
784 select SYS_FSL_ERRATUM_A004510
785 select SYS_FSL_ERRATUM_A004580
786 select SYS_FSL_ERRATUM_A004849
787 select SYS_FSL_ERRATUM_A005812
788 select SYS_FSL_ERRATUM_A007075
789 select SYS_FSL_ERRATUM_CPC_A002
790 select SYS_FSL_ERRATUM_CPC_A003
791 select SYS_FSL_ERRATUM_CPU_A003999
792 select SYS_FSL_ERRATUM_DDR_A003
793 select SYS_FSL_ERRATUM_DDR_A003474
794 select SYS_FSL_ERRATUM_ELBC_A001
795 select SYS_FSL_ERRATUM_ESDHC111
796 select SYS_FSL_ERRATUM_ESDHC13
797 select SYS_FSL_ERRATUM_ESDHC135
798 select SYS_FSL_ERRATUM_I2C_A004447
799 select SYS_FSL_ERRATUM_NMG_CPU_A011
800 select SYS_FSL_ERRATUM_SRIO_A004034
801 select SYS_P4080_ERRATUM_CPU22
802 select SYS_P4080_ERRATUM_PCIE_A003
803 select SYS_P4080_ERRATUM_SERDES8
804 select SYS_P4080_ERRATUM_SERDES9
805 select SYS_P4080_ERRATUM_SERDES_A001
806 select SYS_P4080_ERRATUM_SERDES_A005
807 select SYS_FSL_HAS_DDR3
808 select SYS_FSL_HAS_SEC
809 select SYS_FSL_QORIQ_CHASSIS1
810 select SYS_FSL_SEC_BE
811 select SYS_FSL_SEC_COMPAT_4
821 select SYS_FSL_DDR_VER_44
822 select SYS_FSL_ERRATUM_A004510
823 select SYS_FSL_ERRATUM_A005275
824 select SYS_FSL_ERRATUM_A006261
825 select SYS_FSL_ERRATUM_DDR_A003
826 select SYS_FSL_ERRATUM_DDR_A003474
827 select SYS_FSL_ERRATUM_ESDHC111
828 select SYS_FSL_ERRATUM_I2C_A004447
829 select SYS_FSL_ERRATUM_SRIO_A004034
830 select SYS_FSL_ERRATUM_USB14
831 select SYS_FSL_HAS_DDR3
832 select SYS_FSL_HAS_SEC
833 select SYS_FSL_QORIQ_CHASSIS1
834 select SYS_FSL_SEC_BE
835 select SYS_FSL_SEC_COMPAT_4
846 select SYS_FSL_DDR_VER_44
847 select SYS_FSL_ERRATUM_A004510
848 select SYS_FSL_ERRATUM_A004699
849 select SYS_FSL_ERRATUM_A005275
850 select SYS_FSL_ERRATUM_A005812
851 select SYS_FSL_ERRATUM_A006261
852 select SYS_FSL_ERRATUM_DDR_A003
853 select SYS_FSL_ERRATUM_DDR_A003474
854 select SYS_FSL_ERRATUM_ESDHC111
855 select SYS_FSL_ERRATUM_USB14
856 select SYS_FSL_HAS_DDR3
857 select SYS_FSL_HAS_SEC
858 select SYS_FSL_QORIQ_CHASSIS1
859 select SYS_FSL_SEC_BE
860 select SYS_FSL_SEC_COMPAT_4
867 config ARCH_QEMU_E500
874 select SYS_FSL_DDR_VER_50
875 select SYS_FSL_ERRATUM_A008378
876 select SYS_FSL_ERRATUM_A008109
877 select SYS_FSL_ERRATUM_A009663
878 select SYS_FSL_ERRATUM_A009942
879 select SYS_FSL_ERRATUM_ESDHC111
880 select SYS_FSL_HAS_DDR3
881 select SYS_FSL_HAS_DDR4
882 select SYS_FSL_HAS_SEC
883 select SYS_FSL_QORIQ_CHASSIS2
884 select SYS_FSL_SEC_BE
885 select SYS_FSL_SEC_COMPAT_5
895 select SYS_FSL_DDR_VER_50
896 select SYS_FSL_ERRATUM_A008378
897 select SYS_FSL_ERRATUM_A008109
898 select SYS_FSL_ERRATUM_A009663
899 select SYS_FSL_ERRATUM_A009942
900 select SYS_FSL_ERRATUM_ESDHC111
901 select SYS_FSL_HAS_DDR3
902 select SYS_FSL_HAS_DDR4
903 select SYS_FSL_HAS_SEC
904 select SYS_FSL_QORIQ_CHASSIS2
905 select SYS_FSL_SEC_BE
906 select SYS_FSL_SEC_COMPAT_5
917 select SYS_FSL_DDR_VER_50
918 select SYS_FSL_ERRATUM_A008044
919 select SYS_FSL_ERRATUM_A008378
920 select SYS_FSL_ERRATUM_A008109
921 select SYS_FSL_ERRATUM_A009663
922 select SYS_FSL_ERRATUM_A009942
923 select SYS_FSL_ERRATUM_ESDHC111
924 select SYS_FSL_HAS_DDR3
925 select SYS_FSL_HAS_DDR4
926 select SYS_FSL_HAS_SEC
927 select SYS_FSL_QORIQ_CHASSIS2
928 select SYS_FSL_SEC_BE
929 select SYS_FSL_SEC_COMPAT_5
941 select SYS_FSL_DDR_VER_50
942 select SYS_FSL_ERRATUM_A008044
943 select SYS_FSL_ERRATUM_A008378
944 select SYS_FSL_ERRATUM_A008109
945 select SYS_FSL_ERRATUM_A009663
946 select SYS_FSL_ERRATUM_A009942
947 select SYS_FSL_ERRATUM_ESDHC111
948 select SYS_FSL_HAS_DDR3
949 select SYS_FSL_HAS_DDR4
950 select SYS_FSL_HAS_SEC
951 select SYS_FSL_QORIQ_CHASSIS2
952 select SYS_FSL_SEC_BE
953 select SYS_FSL_SEC_COMPAT_5
966 select SYS_FSL_DDR_VER_47
967 select SYS_FSL_ERRATUM_A006379
968 select SYS_FSL_ERRATUM_A006593
969 select SYS_FSL_ERRATUM_A007186
970 select SYS_FSL_ERRATUM_A007212
971 select SYS_FSL_ERRATUM_A007815
972 select SYS_FSL_ERRATUM_A007907
973 select SYS_FSL_ERRATUM_A008109
974 select SYS_FSL_ERRATUM_A009942
975 select SYS_FSL_ERRATUM_ESDHC111
976 select FSL_PCIE_RESET
977 select SYS_FSL_HAS_DDR3
978 select SYS_FSL_HAS_SEC
979 select SYS_FSL_QORIQ_CHASSIS2
980 select SYS_FSL_SEC_BE
981 select SYS_FSL_SEC_COMPAT_4
994 select SYS_FSL_DDR_VER_47
995 select SYS_FSL_ERRATUM_A006379
996 select SYS_FSL_ERRATUM_A006593
997 select SYS_FSL_ERRATUM_A007186
998 select SYS_FSL_ERRATUM_A007212
999 select SYS_FSL_ERRATUM_A009942
1000 select SYS_FSL_ERRATUM_ESDHC111
1001 select FSL_PCIE_RESET
1002 select SYS_FSL_HAS_DDR3
1003 select SYS_FSL_HAS_SEC
1004 select SYS_FSL_QORIQ_CHASSIS2
1005 select SYS_FSL_SEC_BE
1006 select SYS_FSL_SEC_COMPAT_4
1017 select SYS_FSL_DDR_VER_47
1018 select SYS_FSL_ERRATUM_A004468
1019 select SYS_FSL_ERRATUM_A005871
1020 select SYS_FSL_ERRATUM_A006379
1021 select SYS_FSL_ERRATUM_A006593
1022 select SYS_FSL_ERRATUM_A007186
1023 select SYS_FSL_ERRATUM_A007798
1024 select SYS_FSL_ERRATUM_A009942
1025 select SYS_FSL_HAS_DDR3
1026 select SYS_FSL_HAS_SEC
1027 select SYS_FSL_QORIQ_CHASSIS2
1028 select SYS_FSL_SEC_BE
1029 select SYS_FSL_SEC_COMPAT_4
1042 select SYS_FSL_DDR_VER_47
1043 select SYS_FSL_ERRATUM_A004468
1044 select SYS_FSL_ERRATUM_A005871
1045 select SYS_FSL_ERRATUM_A006261
1046 select SYS_FSL_ERRATUM_A006379
1047 select SYS_FSL_ERRATUM_A006593
1048 select SYS_FSL_ERRATUM_A007186
1049 select SYS_FSL_ERRATUM_A007798
1050 select SYS_FSL_ERRATUM_A007815
1051 select SYS_FSL_ERRATUM_A007907
1052 select SYS_FSL_ERRATUM_A008109
1053 select SYS_FSL_ERRATUM_A009942
1054 select SYS_FSL_HAS_DDR3
1055 select SYS_FSL_HAS_SEC
1056 select SYS_FSL_QORIQ_CHASSIS2
1057 select SYS_FSL_SEC_BE
1058 select SYS_FSL_SEC_COMPAT_4
1066 config MPC85XX_HAVE_RESET_VECTOR
1067 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1078 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1084 Enble PowerPC E500MC core
1089 Enable PowerPC E6500 core
1094 Use Freescale common code for Local Access Window
1099 Enable Freescale Secure Boot feature. Normally selected
1100 by defconfig. If unsure, do not change.
1103 int "Maximum number of CPUs permitted for MPC85xx"
1104 default 12 if ARCH_T4240
1105 default 8 if ARCH_P4080 || \
1107 default 4 if ARCH_B4860 || \
1115 default 2 if ARCH_B4420 || \
1130 Set this number to the maximum number of possible CPUs in the SoC.
1131 SoCs may have multiple clusters with each cluster may have multiple
1132 ports. If some ports are reserved but higher ports are used for
1133 cores, count the reserved ports. This will allocate enough memory
1134 in spin table to properly handle all cores.
1136 config SYS_CCSRBAR_DEFAULT
1137 hex "Default CCSRBAR address"
1138 default 0xff700000 if ARCH_BSC9131 || \
1159 default 0xff600000 if ARCH_P1023
1160 default 0xfe000000 if ARCH_B4420 || \
1175 default 0xe0000000 if ARCH_QEMU_E500
1177 Default value of CCSRBAR comes from power-on-reset. It
1178 is fixed on each SoC. Some SoCs can have different value
1179 if changed by pre-boot regime. The value here must match
1180 the current value in SoC. If not sure, do not change.
1182 config SYS_FSL_ERRATUM_A004468
1185 config SYS_FSL_ERRATUM_A004477
1188 config SYS_FSL_ERRATUM_A004508
1191 config SYS_FSL_ERRATUM_A004580
1194 config SYS_FSL_ERRATUM_A004699
1197 config SYS_FSL_ERRATUM_A004849
1200 config SYS_FSL_ERRATUM_A004510
1203 config SYS_FSL_ERRATUM_A004510_SVR_REV
1205 depends on SYS_FSL_ERRATUM_A004510
1206 default 0x20 if ARCH_P4080
1209 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1211 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1214 config SYS_FSL_ERRATUM_A005125
1217 config SYS_FSL_ERRATUM_A005434
1220 config SYS_FSL_ERRATUM_A005812
1223 config SYS_FSL_ERRATUM_A005871
1226 config SYS_FSL_ERRATUM_A005275
1229 config SYS_FSL_ERRATUM_A006261
1232 config SYS_FSL_ERRATUM_A006379
1235 config SYS_FSL_ERRATUM_A006384
1238 config SYS_FSL_ERRATUM_A006475
1241 config SYS_FSL_ERRATUM_A006593
1244 config SYS_FSL_ERRATUM_A007075
1247 config SYS_FSL_ERRATUM_A007186
1250 config SYS_FSL_ERRATUM_A007212
1253 config SYS_FSL_ERRATUM_A007815
1256 config SYS_FSL_ERRATUM_A007798
1259 config SYS_FSL_ERRATUM_A007907
1262 config SYS_FSL_ERRATUM_A008044
1265 config SYS_FSL_ERRATUM_CPC_A002
1268 config SYS_FSL_ERRATUM_CPC_A003
1271 config SYS_FSL_ERRATUM_CPU_A003999
1274 config SYS_FSL_ERRATUM_ELBC_A001
1277 config SYS_FSL_ERRATUM_I2C_A004447
1280 config SYS_FSL_A004447_SVR_REV
1282 depends on SYS_FSL_ERRATUM_I2C_A004447
1283 default 0x00 if ARCH_MPC8548
1284 default 0x10 if ARCH_P1010
1285 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1286 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1288 config SYS_FSL_ERRATUM_IFC_A002769
1291 config SYS_FSL_ERRATUM_IFC_A003399
1294 config SYS_FSL_ERRATUM_NMG_CPU_A011
1297 config SYS_FSL_ERRATUM_NMG_ETSEC129
1300 config SYS_FSL_ERRATUM_NMG_LBC103
1303 config SYS_FSL_ERRATUM_P1010_A003549
1306 config SYS_FSL_ERRATUM_SATA_A001
1309 config SYS_FSL_ERRATUM_SEC_A003571
1312 config SYS_FSL_ERRATUM_SRIO_A004034
1315 config SYS_FSL_ERRATUM_USB14
1318 config SYS_P4080_ERRATUM_CPU22
1321 config SYS_P4080_ERRATUM_PCIE_A003
1324 config SYS_P4080_ERRATUM_SERDES8
1327 config SYS_P4080_ERRATUM_SERDES9
1330 config SYS_P4080_ERRATUM_SERDES_A001
1333 config SYS_P4080_ERRATUM_SERDES_A005
1336 config FSL_PCIE_DISABLE_ASPM
1339 config FSL_PCIE_RESET
1342 config SYS_FSL_QORIQ_CHASSIS1
1345 config SYS_FSL_QORIQ_CHASSIS2
1348 config SYS_FSL_NUM_LAWS
1349 int "Number of local access windows"
1351 default 32 if ARCH_B4420 || \
1362 default 16 if ARCH_T1023 || \
1366 default 12 if ARCH_BSC9131 || \
1380 default 10 if ARCH_MPC8544 || \
1384 default 8 if ARCH_MPC8540 || \
1389 Number of local access windows. This is fixed per SoC.
1390 If not sure, do not change.
1392 config SYS_FSL_THREADS_PER_CORE
1397 config SYS_NUM_TLBCAMS
1398 int "Number of TLB CAM entries"
1399 default 64 if E500MC
1402 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1403 16 for other E500 SoCs.
1408 config SYS_PPC_E500_USE_DEBUG_TLB
1417 config SYS_PPC_E500_DEBUG_TLB
1418 int "Temporary TLB entry for external debugger"
1419 depends on SYS_PPC_E500_USE_DEBUG_TLB
1420 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1421 default 1 if ARCH_MPC8536
1422 default 2 if ARCH_MPC8572 || \
1430 default 3 if ARCH_P1010 || \
1434 Select a temporary TLB entry to be used during boot to work
1435 around limitations in e500v1 and e500v2 external debugger
1436 support. This reduces the portions of the boot code where
1437 breakpoints and single stepping do not work. The value of this
1438 symbol should be set to the TLB1 entry to be used for this
1439 purpose. If unsure, do not change.
1441 config SYS_FSL_IFC_CLK_DIV
1442 int "Divider of platform clock"
1444 default 2 if ARCH_B4420 || \
1454 Defines divider of platform clock(clock input to
1457 config SYS_FSL_LBC_CLK_DIV
1458 int "Divider of platform clock"
1459 depends on FSL_ELBC || ARCH_MPC8540 || \
1460 ARCH_MPC8548 || ARCH_MPC8541 || \
1461 ARCH_MPC8555 || ARCH_MPC8560 || \
1464 default 2 if ARCH_P2041 || \
1472 Defines divider of platform clock(clock input to
1475 source "board/freescale/corenet_ds/Kconfig"
1476 source "board/freescale/mpc8541cds/Kconfig"
1477 source "board/freescale/mpc8544ds/Kconfig"
1478 source "board/freescale/mpc8548cds/Kconfig"
1479 source "board/freescale/mpc8555cds/Kconfig"
1480 source "board/freescale/mpc8568mds/Kconfig"
1481 source "board/freescale/mpc8569mds/Kconfig"
1482 source "board/freescale/mpc8572ds/Kconfig"
1483 source "board/freescale/p1010rdb/Kconfig"
1484 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1485 source "board/freescale/p2041rdb/Kconfig"
1486 source "board/freescale/qemu-ppce500/Kconfig"
1487 source "board/freescale/t102xrdb/Kconfig"
1488 source "board/freescale/t104xrdb/Kconfig"
1489 source "board/freescale/t208xqds/Kconfig"
1490 source "board/freescale/t208xrdb/Kconfig"
1491 source "board/freescale/t4rdb/Kconfig"
1492 source "board/gdsys/p1022/Kconfig"
1493 source "board/keymile/Kconfig"
1494 source "board/sbc8548/Kconfig"
1495 source "board/socrates/Kconfig"
1496 source "board/varisys/cyrus/Kconfig"
1497 source "board/xes/xpedite520x/Kconfig"
1498 source "board/xes/xpedite537x/Kconfig"
1499 source "board/xes/xpedite550x/Kconfig"
1500 source "board/Arcturus/ucp1020/Kconfig"