arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 config CMD_ERRATA
   8         bool "Enable the 'errata' command"
   9         depends on MPC85xx
  10         default y
  11         help
  12           This enables the 'errata' command which displays a list of errata
  13           work-arounds which are enabled for the current board.
  14
  15 choice
  16         prompt "Target select"
  17         optional
  18
  19 config TARGET_SBC8548
  20         bool "Support sbc8548"
  21         select ARCH_MPC8548
  22
  23 config TARGET_SOCRATES
  24         bool "Support socrates"
  25         select ARCH_MPC8544
  26
  27 config TARGET_B4420QDS
  28         bool "Support B4420QDS"
  29         select ARCH_B4420
  30         select SUPPORT_SPL
  31         select PHYS_64BIT
  32
  33 config TARGET_B4860QDS
  34         bool "Support B4860QDS"
  35         select ARCH_B4860
  36         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  37         select SUPPORT_SPL
  38         select PHYS_64BIT
  39
  40 config TARGET_BSC9131RDB
  41         bool "Support BSC9131RDB"
  42         select ARCH_BSC9131
  43         select SUPPORT_SPL
  44         select BOARD_EARLY_INIT_F
  45
  46 config TARGET_BSC9132QDS
  47         bool "Support BSC9132QDS"
  48         select ARCH_BSC9132
  49         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  50         select SUPPORT_SPL
  51         select BOARD_EARLY_INIT_F
  52
  53 config TARGET_C29XPCIE
  54         bool "Support C29XPCIE"
  55         select ARCH_C29X
  56         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  57         select SUPPORT_SPL
  58         select SUPPORT_TPL
  59         select PHYS_64BIT
  60
  61 config TARGET_P3041DS
  62         bool "Support P3041DS"
  63         select PHYS_64BIT
  64         select ARCH_P3041
  65         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  66         imply CMD_SATA
  67
  68 config TARGET_P4080DS
  69         bool "Support P4080DS"
  70         select PHYS_64BIT
  71         select ARCH_P4080
  72         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  73         imply CMD_SATA
  74
  75 config TARGET_P5020DS
  76         bool "Support P5020DS"
  77         select PHYS_64BIT
  78         select ARCH_P5020
  79         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  80         imply CMD_SATA
  81
  82 config TARGET_P5040DS
  83         bool "Support P5040DS"
  84         select PHYS_64BIT
  85         select ARCH_P5040
  86         select BOARD_LATE_INIT if CHAIN_OF_TRUST
  87         imply CMD_SATA
  88
  89 config TARGET_MPC8536DS
  90         bool "Support MPC8536DS"
  91         select ARCH_MPC8536
  92 # Use DDR3 controller with DDR2 DIMMs on this board
  93         select SYS_FSL_DDRC_GEN3
  94         imply CMD_SATA
  95
  96 config TARGET_MPC8541CDS
  97         bool "Support MPC8541CDS"
  98         select ARCH_MPC8541
  99
 100 config TARGET_MPC8544DS
 101         bool "Support MPC8544DS"
 102         select ARCH_MPC8544
 103
 104 config TARGET_MPC8548CDS
 105         bool "Support MPC8548CDS"
 106         select ARCH_MPC8548
 107
 108 config TARGET_MPC8555CDS
 109         bool "Support MPC8555CDS"
 110         select ARCH_MPC8555
 111
 112 config TARGET_MPC8568MDS
 113         bool "Support MPC8568MDS"
 114         select ARCH_MPC8568
 115
 116 config TARGET_MPC8569MDS
 117         bool "Support MPC8569MDS"
 118         select ARCH_MPC8569
 119
 120 config TARGET_MPC8572DS
 121         bool "Support MPC8572DS"
 122         select ARCH_MPC8572
 123 # Use DDR3 controller with DDR2 DIMMs on this board
 124         select SYS_FSL_DDRC_GEN3
 125         imply SCSI
 126
 127 config TARGET_P1010RDB_PA
 128         bool "Support P1010RDB_PA"
 129         select ARCH_P1010
 130         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 131         select SUPPORT_SPL
 132         select SUPPORT_TPL
 133         imply CMD_EEPROM
 134         imply CMD_SATA
 135
 136 config TARGET_P1010RDB_PB
 137         bool "Support P1010RDB_PB"
 138         select ARCH_P1010
 139         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 140         select SUPPORT_SPL
 141         select SUPPORT_TPL
 142         imply CMD_EEPROM
 143         imply CMD_SATA
 144
 145 config TARGET_P1022DS
 146         bool "Support P1022DS"
 147         select ARCH_P1022
 148         select SUPPORT_SPL
 149         select SUPPORT_TPL
 150         imply CMD_SATA
 151
 152 config TARGET_P1023RDB
 153         bool "Support P1023RDB"
 154         select ARCH_P1023
 155         imply CMD_EEPROM
 156
 157 config TARGET_P1020MBG
 158         bool "Support P1020MBG-PC"
 159         select SUPPORT_SPL
 160         select SUPPORT_TPL
 161         select ARCH_P1020
 162         imply CMD_EEPROM
 163         imply CMD_SATA
 164
 165 config TARGET_P1020RDB_PC
 166         bool "Support P1020RDB-PC"
 167         select SUPPORT_SPL
 168         select SUPPORT_TPL
 169         select ARCH_P1020
 170         imply CMD_EEPROM
 171         imply CMD_SATA
 172
 173 config TARGET_P1020RDB_PD
 174         bool "Support P1020RDB-PD"
 175         select SUPPORT_SPL
 176         select SUPPORT_TPL
 177         select ARCH_P1020
 178         imply CMD_EEPROM
 179         imply CMD_SATA
 180
 181 config TARGET_P1020UTM
 182         bool "Support P1020UTM"
 183         select SUPPORT_SPL
 184         select SUPPORT_TPL
 185         select ARCH_P1020
 186         imply CMD_EEPROM
 187         imply CMD_SATA
 188
 189 config TARGET_P1021RDB
 190         bool "Support P1021RDB"
 191         select SUPPORT_SPL
 192         select SUPPORT_TPL
 193         select ARCH_P1021
 194         imply CMD_EEPROM
 195         imply CMD_SATA
 196
 197 config TARGET_P1024RDB
 198         bool "Support P1024RDB"
 199         select SUPPORT_SPL
 200         select SUPPORT_TPL
 201         select ARCH_P1024
 202         imply CMD_EEPROM
 203         imply CMD_SATA
 204
 205 config TARGET_P1025RDB
 206         bool "Support P1025RDB"
 207         select SUPPORT_SPL
 208         select SUPPORT_TPL
 209         select ARCH_P1025
 210         imply CMD_EEPROM
 211         imply CMD_SATA
 212
 213 config TARGET_P2020RDB
 214         bool "Support P2020RDB-PC"
 215         select SUPPORT_SPL
 216         select SUPPORT_TPL
 217         select ARCH_P2020
 218         imply CMD_EEPROM
 219         imply CMD_SATA
 220
 221 config TARGET_P1_TWR
 222         bool "Support p1_twr"
 223         select ARCH_P1025
 224
 225 config TARGET_P2041RDB
 226         bool "Support P2041RDB"
 227         select ARCH_P2041
 228         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 229         select PHYS_64BIT
 230         imply CMD_SATA
 231
 232 config TARGET_QEMU_PPCE500
 233         bool "Support qemu-ppce500"
 234         select ARCH_QEMU_E500
 235         select PHYS_64BIT
 236
 237 config TARGET_T1024QDS
 238         bool "Support T1024QDS"
 239         select ARCH_T1024
 240         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 241         select SUPPORT_SPL
 242         select PHYS_64BIT
 243         imply CMD_EEPROM
 244         imply CMD_SATA
 245
 246 config TARGET_T1023RDB
 247         bool "Support T1023RDB"
 248         select ARCH_T1023
 249         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 250         select SUPPORT_SPL
 251         select PHYS_64BIT
 252         imply CMD_EEPROM
 253
 254 config TARGET_T1024RDB
 255         bool "Support T1024RDB"
 256         select ARCH_T1024
 257         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 258         select SUPPORT_SPL
 259         select PHYS_64BIT
 260         imply CMD_EEPROM
 261
 262 config TARGET_T1040QDS
 263         bool "Support T1040QDS"
 264         select ARCH_T1040
 265         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 266         select PHYS_64BIT
 267         imply CMD_EEPROM
 268         imply CMD_SATA
 269
 270 config TARGET_T1040RDB
 271         bool "Support T1040RDB"
 272         select ARCH_T1040
 273         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 274         select SUPPORT_SPL
 275         select PHYS_64BIT
 276         imply CMD_SATA
 277
 278 config TARGET_T1040D4RDB
 279         bool "Support T1040D4RDB"
 280         select ARCH_T1040
 281         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 282         select SUPPORT_SPL
 283         select PHYS_64BIT
 284         imply CMD_SATA
 285
 286 config TARGET_T1042RDB
 287         bool "Support T1042RDB"
 288         select ARCH_T1042
 289         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 290         select SUPPORT_SPL
 291         select PHYS_64BIT
 292         imply CMD_SATA
 293
 294 config TARGET_T1042D4RDB
 295         bool "Support T1042D4RDB"
 296         select ARCH_T1042
 297         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 298         select SUPPORT_SPL
 299         select PHYS_64BIT
 300         imply CMD_SATA
 301
 302 config TARGET_T1042RDB_PI
 303         bool "Support T1042RDB_PI"
 304         select ARCH_T1042
 305         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 306         select SUPPORT_SPL
 307         select PHYS_64BIT
 308         imply CMD_SATA
 309
 310 config TARGET_T2080QDS
 311         bool "Support T2080QDS"
 312         select ARCH_T2080
 313         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 314         select SUPPORT_SPL
 315         select PHYS_64BIT
 316         imply CMD_SATA
 317
 318 config TARGET_T2080RDB
 319         bool "Support T2080RDB"
 320         select ARCH_T2080
 321         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 322         select SUPPORT_SPL
 323         select PHYS_64BIT
 324         imply CMD_SATA
 325
 326 config TARGET_T2081QDS
 327         bool "Support T2081QDS"
 328         select ARCH_T2081
 329         select SUPPORT_SPL
 330         select PHYS_64BIT
 331
 332 config TARGET_T4160QDS
 333         bool "Support T4160QDS"
 334         select ARCH_T4160
 335         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 336         select SUPPORT_SPL
 337         select PHYS_64BIT
 338         imply CMD_SATA
 339
 340 config TARGET_T4160RDB
 341         bool "Support T4160RDB"
 342         select ARCH_T4160
 343         select SUPPORT_SPL
 344         select PHYS_64BIT
 345
 346 config TARGET_T4240QDS
 347         bool "Support T4240QDS"
 348         select ARCH_T4240
 349         select BOARD_LATE_INIT if CHAIN_OF_TRUST
 350         select SUPPORT_SPL
 351         select PHYS_64BIT
 352         imply CMD_SATA
 353
 354 config TARGET_T4240RDB
 355         bool "Support T4240RDB"
 356         select ARCH_T4240
 357         select SUPPORT_SPL
 358         select PHYS_64BIT
 359         imply CMD_SATA
 360
 361 config TARGET_CONTROLCENTERD
 362         bool "Support controlcenterd"
 363         select ARCH_P1022
 364
 365 config TARGET_KMP204X
 366         bool "Support kmp204x"
 367         select ARCH_P2041
 368         select PHYS_64BIT
 369         imply CMD_CRAMFS
 370         imply FS_CRAMFS
 371
 372 config TARGET_XPEDITE520X
 373         bool "Support xpedite520x"
 374         select ARCH_MPC8548
 375
 376 config TARGET_XPEDITE537X
 377         bool "Support xpedite537x"
 378         select ARCH_MPC8572
 379 # Use DDR3 controller with DDR2 DIMMs on this board
 380         select SYS_FSL_DDRC_GEN3
 381
 382 config TARGET_XPEDITE550X
 383         bool "Support xpedite550x"
 384         select ARCH_P2020
 385
 386 config TARGET_UCP1020
 387         bool "Support uCP1020"
 388         select ARCH_P1020
 389         imply CMD_SATA
 390
 391 config TARGET_CYRUS_P5020
 392         bool "Support Varisys Cyrus P5020"
 393         select ARCH_P5020
 394         select PHYS_64BIT
 395
 396 config TARGET_CYRUS_P5040
 397          bool "Support Varisys Cyrus P5040"
 398         select ARCH_P5040
 399         select PHYS_64BIT
 400
 401 endchoice
 402
 403 config ARCH_B4420
 404         bool
 405         select E500MC
 406         select E6500
 407         select FSL_LAW
 408         select SYS_FSL_DDR_VER_47
 409         select SYS_FSL_ERRATUM_A004477
 410         select SYS_FSL_ERRATUM_A005871
 411         select SYS_FSL_ERRATUM_A006379
 412         select SYS_FSL_ERRATUM_A006384
 413         select SYS_FSL_ERRATUM_A006475
 414         select SYS_FSL_ERRATUM_A006593
 415         select SYS_FSL_ERRATUM_A007075
 416         select SYS_FSL_ERRATUM_A007186
 417         select SYS_FSL_ERRATUM_A007212
 418         select SYS_FSL_ERRATUM_A009942
 419         select SYS_FSL_HAS_DDR3
 420         select SYS_FSL_HAS_SEC
 421         select SYS_FSL_QORIQ_CHASSIS2
 422         select SYS_FSL_SEC_BE
 423         select SYS_FSL_SEC_COMPAT_4
 424         select SYS_PPC64
 425         select FSL_IFC
 426         imply CMD_EEPROM
 427
 428 config ARCH_B4860
 429         bool
 430         select E500MC
 431         select E6500
 432         select FSL_LAW
 433         select SYS_FSL_DDR_VER_47
 434         select SYS_FSL_ERRATUM_A004477
 435         select SYS_FSL_ERRATUM_A005871
 436         select SYS_FSL_ERRATUM_A006379
 437         select SYS_FSL_ERRATUM_A006384
 438         select SYS_FSL_ERRATUM_A006475
 439         select SYS_FSL_ERRATUM_A006593
 440         select SYS_FSL_ERRATUM_A007075
 441         select SYS_FSL_ERRATUM_A007186
 442         select SYS_FSL_ERRATUM_A007212
 443         select SYS_FSL_ERRATUM_A007907
 444         select SYS_FSL_ERRATUM_A009942
 445         select SYS_FSL_HAS_DDR3
 446         select SYS_FSL_HAS_SEC
 447         select SYS_FSL_QORIQ_CHASSIS2
 448         select SYS_FSL_SEC_BE
 449         select SYS_FSL_SEC_COMPAT_4
 450         select SYS_PPC64
 451         select FSL_IFC
 452         imply CMD_EEPROM
 453
 454 config ARCH_BSC9131
 455         bool
 456         select FSL_LAW
 457         select SYS_FSL_DDR_VER_44
 458         select SYS_FSL_ERRATUM_A004477
 459         select SYS_FSL_ERRATUM_A005125
 460         select SYS_FSL_ERRATUM_ESDHC111
 461         select SYS_FSL_HAS_DDR3
 462         select SYS_FSL_HAS_SEC
 463         select SYS_FSL_SEC_BE
 464         select SYS_FSL_SEC_COMPAT_4
 465         select FSL_IFC
 466         imply CMD_EEPROM
 467
 468 config ARCH_BSC9132
 469         bool
 470         select FSL_LAW
 471         select SYS_FSL_DDR_VER_46
 472         select SYS_FSL_ERRATUM_A004477
 473         select SYS_FSL_ERRATUM_A005125
 474         select SYS_FSL_ERRATUM_A005434
 475         select SYS_FSL_ERRATUM_ESDHC111
 476         select SYS_FSL_ERRATUM_I2C_A004447
 477         select SYS_FSL_ERRATUM_IFC_A002769
 478         select SYS_FSL_HAS_DDR3
 479         select SYS_FSL_HAS_SEC
 480         select SYS_FSL_SEC_BE
 481         select SYS_FSL_SEC_COMPAT_4
 482         select SYS_PPC_E500_USE_DEBUG_TLB
 483         select FSL_IFC
 484         imply CMD_EEPROM
 485         imply CMD_MTDPARTS
 486
 487 config ARCH_C29X
 488         bool
 489         select FSL_LAW
 490         select SYS_FSL_DDR_VER_46
 491         select SYS_FSL_ERRATUM_A005125
 492         select SYS_FSL_ERRATUM_ESDHC111
 493         select SYS_FSL_HAS_DDR3
 494         select SYS_FSL_HAS_SEC
 495         select SYS_FSL_SEC_BE
 496         select SYS_FSL_SEC_COMPAT_6
 497         select SYS_PPC_E500_USE_DEBUG_TLB
 498         select FSL_IFC
 499
 500 config ARCH_MPC8536
 501         bool
 502         select FSL_LAW
 503         select SYS_FSL_ERRATUM_A004508
 504         select SYS_FSL_ERRATUM_A005125
 505         select SYS_FSL_HAS_DDR2
 506         select SYS_FSL_HAS_DDR3
 507         select SYS_FSL_HAS_SEC
 508         select SYS_FSL_SEC_BE
 509         select SYS_FSL_SEC_COMPAT_2
 510         select SYS_PPC_E500_USE_DEBUG_TLB
 511         select FSL_ELBC
 512         imply CMD_SATA
 513
 514 config ARCH_MPC8540
 515         bool
 516         select FSL_LAW
 517         select SYS_FSL_HAS_DDR1
 518
 519 config ARCH_MPC8541
 520         bool
 521         select FSL_LAW
 522         select SYS_FSL_HAS_DDR1
 523         select SYS_FSL_HAS_SEC
 524         select SYS_FSL_SEC_BE
 525         select SYS_FSL_SEC_COMPAT_2
 526
 527 config ARCH_MPC8544
 528         bool
 529         select FSL_LAW
 530         select SYS_FSL_ERRATUM_A005125
 531         select SYS_FSL_HAS_DDR2
 532         select SYS_FSL_HAS_SEC
 533         select SYS_FSL_SEC_BE
 534         select SYS_FSL_SEC_COMPAT_2
 535         select SYS_PPC_E500_USE_DEBUG_TLB
 536         select FSL_ELBC
 537
 538 config ARCH_MPC8548
 539         bool
 540         select FSL_LAW
 541         select SYS_FSL_ERRATUM_A005125
 542         select SYS_FSL_ERRATUM_NMG_DDR120
 543         select SYS_FSL_ERRATUM_NMG_LBC103
 544         select SYS_FSL_ERRATUM_NMG_ETSEC129
 545         select SYS_FSL_ERRATUM_I2C_A004447
 546         select SYS_FSL_HAS_DDR2
 547         select SYS_FSL_HAS_DDR1
 548         select SYS_FSL_HAS_SEC
 549         select SYS_FSL_SEC_BE
 550         select SYS_FSL_SEC_COMPAT_2
 551         select SYS_PPC_E500_USE_DEBUG_TLB
 552
 553 config ARCH_MPC8555
 554         bool
 555         select FSL_LAW
 556         select SYS_FSL_HAS_DDR1
 557         select SYS_FSL_HAS_SEC
 558         select SYS_FSL_SEC_BE
 559         select SYS_FSL_SEC_COMPAT_2
 560
 561 config ARCH_MPC8560
 562         bool
 563         select FSL_LAW
 564         select SYS_FSL_HAS_DDR1
 565
 566 config ARCH_MPC8568
 567         bool
 568         select FSL_LAW
 569         select SYS_FSL_HAS_DDR2
 570         select SYS_FSL_HAS_SEC
 571         select SYS_FSL_SEC_BE
 572         select SYS_FSL_SEC_COMPAT_2
 573
 574 config ARCH_MPC8569
 575         bool
 576         select FSL_LAW
 577         select SYS_FSL_ERRATUM_A004508
 578         select SYS_FSL_ERRATUM_A005125
 579         select SYS_FSL_HAS_DDR3
 580         select SYS_FSL_HAS_SEC
 581         select SYS_FSL_SEC_BE
 582         select SYS_FSL_SEC_COMPAT_2
 583         select FSL_ELBC
 584
 585 config ARCH_MPC8572
 586         bool
 587         select FSL_LAW
 588         select SYS_FSL_ERRATUM_A004508
 589         select SYS_FSL_ERRATUM_A005125
 590         select SYS_FSL_ERRATUM_DDR_115
 591         select SYS_FSL_ERRATUM_DDR111_DDR134
 592         select SYS_FSL_HAS_DDR2
 593         select SYS_FSL_HAS_DDR3
 594         select SYS_FSL_HAS_SEC
 595         select SYS_FSL_SEC_BE
 596         select SYS_FSL_SEC_COMPAT_2
 597         select SYS_PPC_E500_USE_DEBUG_TLB
 598         select FSL_ELBC
 599
 600 config ARCH_P1010
 601         bool
 602         select FSL_LAW
 603         select SYS_FSL_ERRATUM_A004477
 604         select SYS_FSL_ERRATUM_A004508
 605         select SYS_FSL_ERRATUM_A005125
 606         select SYS_FSL_ERRATUM_A006261
 607         select SYS_FSL_ERRATUM_A007075
 608         select SYS_FSL_ERRATUM_ESDHC111
 609         select SYS_FSL_ERRATUM_I2C_A004447
 610         select SYS_FSL_ERRATUM_IFC_A002769
 611         select SYS_FSL_ERRATUM_P1010_A003549
 612         select SYS_FSL_ERRATUM_SEC_A003571
 613         select SYS_FSL_ERRATUM_IFC_A003399
 614         select SYS_FSL_HAS_DDR3
 615         select SYS_FSL_HAS_SEC
 616         select SYS_FSL_SEC_BE
 617         select SYS_FSL_SEC_COMPAT_4
 618         select SYS_PPC_E500_USE_DEBUG_TLB
 619         select FSL_IFC
 620         imply CMD_EEPROM
 621         imply CMD_MTDPARTS
 622         imply CMD_SATA
 623
 624 config ARCH_P1011
 625         bool
 626         select FSL_LAW
 627         select SYS_FSL_ERRATUM_A004508
 628         select SYS_FSL_ERRATUM_A005125
 629         select SYS_FSL_ERRATUM_ELBC_A001
 630         select SYS_FSL_ERRATUM_ESDHC111
 631         select SYS_FSL_HAS_DDR3
 632         select SYS_FSL_HAS_SEC
 633         select SYS_FSL_SEC_BE
 634         select SYS_FSL_SEC_COMPAT_2
 635         select SYS_PPC_E500_USE_DEBUG_TLB
 636         select FSL_ELBC
 637
 638 config ARCH_P1020
 639         bool
 640         select FSL_LAW
 641         select SYS_FSL_ERRATUM_A004508
 642         select SYS_FSL_ERRATUM_A005125
 643         select SYS_FSL_ERRATUM_ELBC_A001
 644         select SYS_FSL_ERRATUM_ESDHC111
 645         select SYS_FSL_HAS_DDR3
 646         select SYS_FSL_HAS_SEC
 647         select SYS_FSL_SEC_BE
 648         select SYS_FSL_SEC_COMPAT_2
 649         select SYS_PPC_E500_USE_DEBUG_TLB
 650         select FSL_ELBC
 651         imply CMD_SATA
 652
 653 config ARCH_P1021
 654         bool
 655         select FSL_LAW
 656         select SYS_FSL_ERRATUM_A004508
 657         select SYS_FSL_ERRATUM_A005125
 658         select SYS_FSL_ERRATUM_ELBC_A001
 659         select SYS_FSL_ERRATUM_ESDHC111
 660         select SYS_FSL_HAS_DDR3
 661         select SYS_FSL_HAS_SEC
 662         select SYS_FSL_SEC_BE
 663         select SYS_FSL_SEC_COMPAT_2
 664         select SYS_PPC_E500_USE_DEBUG_TLB
 665         select FSL_ELBC
 666         imply CMD_SATA
 667
 668 config ARCH_P1022
 669         bool
 670         select FSL_LAW
 671         select SYS_FSL_ERRATUM_A004477
 672         select SYS_FSL_ERRATUM_A004508
 673         select SYS_FSL_ERRATUM_A005125
 674         select SYS_FSL_ERRATUM_ELBC_A001
 675         select SYS_FSL_ERRATUM_ESDHC111
 676         select SYS_FSL_ERRATUM_SATA_A001
 677         select SYS_FSL_HAS_DDR3
 678         select SYS_FSL_HAS_SEC
 679         select SYS_FSL_SEC_BE
 680         select SYS_FSL_SEC_COMPAT_2
 681         select SYS_PPC_E500_USE_DEBUG_TLB
 682         select FSL_ELBC
 683
 684 config ARCH_P1023
 685         bool
 686         select FSL_LAW
 687         select SYS_FSL_ERRATUM_A004508
 688         select SYS_FSL_ERRATUM_A005125
 689         select SYS_FSL_ERRATUM_I2C_A004447
 690         select SYS_FSL_HAS_DDR3
 691         select SYS_FSL_HAS_SEC
 692         select SYS_FSL_SEC_BE
 693         select SYS_FSL_SEC_COMPAT_4
 694         select FSL_ELBC
 695
 696 config ARCH_P1024
 697         bool
 698         select FSL_LAW
 699         select SYS_FSL_ERRATUM_A004508
 700         select SYS_FSL_ERRATUM_A005125
 701         select SYS_FSL_ERRATUM_ELBC_A001
 702         select SYS_FSL_ERRATUM_ESDHC111
 703         select SYS_FSL_HAS_DDR3
 704         select SYS_FSL_HAS_SEC
 705         select SYS_FSL_SEC_BE
 706         select SYS_FSL_SEC_COMPAT_2
 707         select SYS_PPC_E500_USE_DEBUG_TLB
 708         select FSL_ELBC
 709         imply CMD_EEPROM
 710         imply CMD_SATA
 711
 712 config ARCH_P1025
 713         bool
 714         select FSL_LAW
 715         select SYS_FSL_ERRATUM_A004508
 716         select SYS_FSL_ERRATUM_A005125
 717         select SYS_FSL_ERRATUM_ELBC_A001
 718         select SYS_FSL_ERRATUM_ESDHC111
 719         select SYS_FSL_HAS_DDR3
 720         select SYS_FSL_HAS_SEC
 721         select SYS_FSL_SEC_BE
 722         select SYS_FSL_SEC_COMPAT_2
 723         select SYS_PPC_E500_USE_DEBUG_TLB
 724         select FSL_ELBC
 725         imply CMD_SATA
 726
 727 config ARCH_P2020
 728         bool
 729         select FSL_LAW
 730         select SYS_FSL_ERRATUM_A004477
 731         select SYS_FSL_ERRATUM_A004508
 732         select SYS_FSL_ERRATUM_A005125
 733         select SYS_FSL_ERRATUM_ESDHC111
 734         select SYS_FSL_ERRATUM_ESDHC_A001
 735         select SYS_FSL_HAS_DDR3
 736         select SYS_FSL_HAS_SEC
 737         select SYS_FSL_SEC_BE
 738         select SYS_FSL_SEC_COMPAT_2
 739         select SYS_PPC_E500_USE_DEBUG_TLB
 740         select FSL_ELBC
 741         imply CMD_EEPROM
 742
 743 config ARCH_P2041
 744         bool
 745         select E500MC
 746         select FSL_LAW
 747         select SYS_FSL_ERRATUM_A004510
 748         select SYS_FSL_ERRATUM_A004849
 749         select SYS_FSL_ERRATUM_A006261
 750         select SYS_FSL_ERRATUM_CPU_A003999
 751         select SYS_FSL_ERRATUM_DDR_A003
 752         select SYS_FSL_ERRATUM_DDR_A003474
 753         select SYS_FSL_ERRATUM_ESDHC111
 754         select SYS_FSL_ERRATUM_I2C_A004447
 755         select SYS_FSL_ERRATUM_NMG_CPU_A011
 756         select SYS_FSL_ERRATUM_SRIO_A004034
 757         select SYS_FSL_ERRATUM_USB14
 758         select SYS_FSL_HAS_DDR3
 759         select SYS_FSL_HAS_SEC
 760         select SYS_FSL_QORIQ_CHASSIS1
 761         select SYS_FSL_SEC_BE
 762         select SYS_FSL_SEC_COMPAT_4
 763         select FSL_ELBC
 764
 765 config ARCH_P3041
 766         bool
 767         select E500MC
 768         select FSL_LAW
 769         select SYS_FSL_DDR_VER_44
 770         select SYS_FSL_ERRATUM_A004510
 771         select SYS_FSL_ERRATUM_A004849
 772         select SYS_FSL_ERRATUM_A005812
 773         select SYS_FSL_ERRATUM_A006261
 774         select SYS_FSL_ERRATUM_CPU_A003999
 775         select SYS_FSL_ERRATUM_DDR_A003
 776         select SYS_FSL_ERRATUM_DDR_A003474
 777         select SYS_FSL_ERRATUM_ESDHC111
 778         select SYS_FSL_ERRATUM_I2C_A004447
 779         select SYS_FSL_ERRATUM_NMG_CPU_A011
 780         select SYS_FSL_ERRATUM_SRIO_A004034
 781         select SYS_FSL_ERRATUM_USB14
 782         select SYS_FSL_HAS_DDR3
 783         select SYS_FSL_HAS_SEC
 784         select SYS_FSL_QORIQ_CHASSIS1
 785         select SYS_FSL_SEC_BE
 786         select SYS_FSL_SEC_COMPAT_4
 787         select FSL_ELBC
 788         imply CMD_SATA
 789
 790 config ARCH_P4080
 791         bool
 792         select E500MC
 793         select FSL_LAW
 794         select SYS_FSL_DDR_VER_44
 795         select SYS_FSL_ERRATUM_A004510
 796         select SYS_FSL_ERRATUM_A004580
 797         select SYS_FSL_ERRATUM_A004849
 798         select SYS_FSL_ERRATUM_A005812
 799         select SYS_FSL_ERRATUM_A007075
 800         select SYS_FSL_ERRATUM_CPC_A002
 801         select SYS_FSL_ERRATUM_CPC_A003
 802         select SYS_FSL_ERRATUM_CPU_A003999
 803         select SYS_FSL_ERRATUM_DDR_A003
 804         select SYS_FSL_ERRATUM_DDR_A003474
 805         select SYS_FSL_ERRATUM_ELBC_A001
 806         select SYS_FSL_ERRATUM_ESDHC111
 807         select SYS_FSL_ERRATUM_ESDHC13
 808         select SYS_FSL_ERRATUM_ESDHC135
 809         select SYS_FSL_ERRATUM_I2C_A004447
 810         select SYS_FSL_ERRATUM_NMG_CPU_A011
 811         select SYS_FSL_ERRATUM_SRIO_A004034
 812         select SYS_P4080_ERRATUM_CPU22
 813         select SYS_P4080_ERRATUM_PCIE_A003
 814         select SYS_P4080_ERRATUM_SERDES8
 815         select SYS_P4080_ERRATUM_SERDES9
 816         select SYS_P4080_ERRATUM_SERDES_A001
 817         select SYS_P4080_ERRATUM_SERDES_A005
 818         select SYS_FSL_HAS_DDR3
 819         select SYS_FSL_HAS_SEC
 820         select SYS_FSL_QORIQ_CHASSIS1
 821         select SYS_FSL_SEC_BE
 822         select SYS_FSL_SEC_COMPAT_4
 823         select FSL_ELBC
 824         imply CMD_SATA
 825
 826 config ARCH_P5020
 827         bool
 828         select E500MC
 829         select FSL_LAW
 830         select SYS_FSL_DDR_VER_44
 831         select SYS_FSL_ERRATUM_A004510
 832         select SYS_FSL_ERRATUM_A006261
 833         select SYS_FSL_ERRATUM_DDR_A003
 834         select SYS_FSL_ERRATUM_DDR_A003474
 835         select SYS_FSL_ERRATUM_ESDHC111
 836         select SYS_FSL_ERRATUM_I2C_A004447
 837         select SYS_FSL_ERRATUM_SRIO_A004034
 838         select SYS_FSL_ERRATUM_USB14
 839         select SYS_FSL_HAS_DDR3
 840         select SYS_FSL_HAS_SEC
 841         select SYS_FSL_QORIQ_CHASSIS1
 842         select SYS_FSL_SEC_BE
 843         select SYS_FSL_SEC_COMPAT_4
 844         select SYS_PPC64
 845         select FSL_ELBC
 846         imply CMD_SATA
 847
 848 config ARCH_P5040
 849         bool
 850         select E500MC
 851         select FSL_LAW
 852         select SYS_FSL_DDR_VER_44
 853         select SYS_FSL_ERRATUM_A004510
 854         select SYS_FSL_ERRATUM_A004699
 855         select SYS_FSL_ERRATUM_A005812
 856         select SYS_FSL_ERRATUM_A006261
 857         select SYS_FSL_ERRATUM_DDR_A003
 858         select SYS_FSL_ERRATUM_DDR_A003474
 859         select SYS_FSL_ERRATUM_ESDHC111
 860         select SYS_FSL_ERRATUM_USB14
 861         select SYS_FSL_HAS_DDR3
 862         select SYS_FSL_HAS_SEC
 863         select SYS_FSL_QORIQ_CHASSIS1
 864         select SYS_FSL_SEC_BE
 865         select SYS_FSL_SEC_COMPAT_4
 866         select SYS_PPC64
 867         select FSL_ELBC
 868         imply CMD_SATA
 869
 870 config ARCH_QEMU_E500
 871         bool
 872
 873 config ARCH_T1023
 874         bool
 875         select E500MC
 876         select FSL_LAW
 877         select SYS_FSL_DDR_VER_50
 878         select SYS_FSL_ERRATUM_A008378
 879         select SYS_FSL_ERRATUM_A009663
 880         select SYS_FSL_ERRATUM_A009942
 881         select SYS_FSL_ERRATUM_ESDHC111
 882         select SYS_FSL_HAS_DDR3
 883         select SYS_FSL_HAS_DDR4
 884         select SYS_FSL_HAS_SEC
 885         select SYS_FSL_QORIQ_CHASSIS2
 886         select SYS_FSL_SEC_BE
 887         select SYS_FSL_SEC_COMPAT_5
 888         select FSL_IFC
 889         imply CMD_EEPROM
 890
 891 config ARCH_T1024
 892         bool
 893         select E500MC
 894         select FSL_LAW
 895         select SYS_FSL_DDR_VER_50
 896         select SYS_FSL_ERRATUM_A008378
 897         select SYS_FSL_ERRATUM_A009663
 898         select SYS_FSL_ERRATUM_A009942
 899         select SYS_FSL_ERRATUM_ESDHC111
 900         select SYS_FSL_HAS_DDR3
 901         select SYS_FSL_HAS_DDR4
 902         select SYS_FSL_HAS_SEC
 903         select SYS_FSL_QORIQ_CHASSIS2
 904         select SYS_FSL_SEC_BE
 905         select SYS_FSL_SEC_COMPAT_5
 906         select FSL_IFC
 907         imply CMD_EEPROM
 908         imply CMD_MTDPARTS
 909
 910 config ARCH_T1040
 911         bool
 912         select E500MC
 913         select FSL_LAW
 914         select SYS_FSL_DDR_VER_50
 915         select SYS_FSL_ERRATUM_A008044
 916         select SYS_FSL_ERRATUM_A008378
 917         select SYS_FSL_ERRATUM_A009663
 918         select SYS_FSL_ERRATUM_A009942
 919         select SYS_FSL_ERRATUM_ESDHC111
 920         select SYS_FSL_HAS_DDR3
 921         select SYS_FSL_HAS_DDR4
 922         select SYS_FSL_HAS_SEC
 923         select SYS_FSL_QORIQ_CHASSIS2
 924         select SYS_FSL_SEC_BE
 925         select SYS_FSL_SEC_COMPAT_5
 926         select FSL_IFC
 927         imply CMD_MTDPARTS
 928         imply CMD_SATA
 929
 930 config ARCH_T1042
 931         bool
 932         select E500MC
 933         select FSL_LAW
 934         select SYS_FSL_DDR_VER_50
 935         select SYS_FSL_ERRATUM_A008044
 936         select SYS_FSL_ERRATUM_A008378
 937         select SYS_FSL_ERRATUM_A009663
 938         select SYS_FSL_ERRATUM_A009942
 939         select SYS_FSL_ERRATUM_ESDHC111
 940         select SYS_FSL_HAS_DDR3
 941         select SYS_FSL_HAS_DDR4
 942         select SYS_FSL_HAS_SEC
 943         select SYS_FSL_QORIQ_CHASSIS2
 944         select SYS_FSL_SEC_BE
 945         select SYS_FSL_SEC_COMPAT_5
 946         select FSL_IFC
 947         imply CMD_MTDPARTS
 948         imply CMD_SATA
 949
 950 config ARCH_T2080
 951         bool
 952         select E500MC
 953         select E6500
 954         select FSL_LAW
 955         select SYS_FSL_DDR_VER_47
 956         select SYS_FSL_ERRATUM_A006379
 957         select SYS_FSL_ERRATUM_A006593
 958         select SYS_FSL_ERRATUM_A007186
 959         select SYS_FSL_ERRATUM_A007212
 960         select SYS_FSL_ERRATUM_A007815
 961         select SYS_FSL_ERRATUM_A007907
 962         select SYS_FSL_ERRATUM_A009942
 963         select SYS_FSL_ERRATUM_ESDHC111
 964         select SYS_FSL_HAS_DDR3
 965         select SYS_FSL_HAS_SEC
 966         select SYS_FSL_QORIQ_CHASSIS2
 967         select SYS_FSL_SEC_BE
 968         select SYS_FSL_SEC_COMPAT_4
 969         select SYS_PPC64
 970         select FSL_IFC
 971         imply CMD_SATA
 972
 973 config ARCH_T2081
 974         bool
 975         select E500MC
 976         select E6500
 977         select FSL_LAW
 978         select SYS_FSL_DDR_VER_47
 979         select SYS_FSL_ERRATUM_A006379
 980         select SYS_FSL_ERRATUM_A006593
 981         select SYS_FSL_ERRATUM_A007186
 982         select SYS_FSL_ERRATUM_A007212
 983         select SYS_FSL_ERRATUM_A009942
 984         select SYS_FSL_ERRATUM_ESDHC111
 985         select SYS_FSL_HAS_DDR3
 986         select SYS_FSL_HAS_SEC
 987         select SYS_FSL_QORIQ_CHASSIS2
 988         select SYS_FSL_SEC_BE
 989         select SYS_FSL_SEC_COMPAT_4
 990         select SYS_PPC64
 991         select FSL_IFC
 992
 993 config ARCH_T4160
 994         bool
 995         select E500MC
 996         select E6500
 997         select FSL_LAW
 998         select SYS_FSL_DDR_VER_47
 999         select SYS_FSL_ERRATUM_A004468
1000         select SYS_FSL_ERRATUM_A005871
1001         select SYS_FSL_ERRATUM_A006379
1002         select SYS_FSL_ERRATUM_A006593
1003         select SYS_FSL_ERRATUM_A007186
1004         select SYS_FSL_ERRATUM_A007798
1005         select SYS_FSL_ERRATUM_A009942
1006         select SYS_FSL_HAS_DDR3
1007         select SYS_FSL_HAS_SEC
1008         select SYS_FSL_QORIQ_CHASSIS2
1009         select SYS_FSL_SEC_BE
1010         select SYS_FSL_SEC_COMPAT_4
1011         select SYS_PPC64
1012         select FSL_IFC
1013         imply CMD_SATA
1014
1015 config ARCH_T4240
1016         bool
1017         select E500MC
1018         select E6500
1019         select FSL_LAW
1020         select SYS_FSL_DDR_VER_47
1021         select SYS_FSL_ERRATUM_A004468
1022         select SYS_FSL_ERRATUM_A005871
1023         select SYS_FSL_ERRATUM_A006261
1024         select SYS_FSL_ERRATUM_A006379
1025         select SYS_FSL_ERRATUM_A006593
1026         select SYS_FSL_ERRATUM_A007186
1027         select SYS_FSL_ERRATUM_A007798
1028         select SYS_FSL_ERRATUM_A007815
1029         select SYS_FSL_ERRATUM_A007907
1030         select SYS_FSL_ERRATUM_A009942
1031         select SYS_FSL_HAS_DDR3
1032         select SYS_FSL_HAS_SEC
1033         select SYS_FSL_QORIQ_CHASSIS2
1034         select SYS_FSL_SEC_BE
1035         select SYS_FSL_SEC_COMPAT_4
1036         select SYS_PPC64
1037         select FSL_IFC
1038         imply CMD_SATA
1039
1040 config BOOKE
1041         bool
1042         default y
1043
1044 config E500
1045         bool
1046         default y
1047         help
1048                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1049
1050 config E500MC
1051         bool
1052         help
1053                 Enble PowerPC E500MC core
1054
1055 config E6500
1056         bool
1057         help
1058                 Enable PowerPC E6500 core
1059
1060 config FSL_LAW
1061         bool
1062         help
1063                 Use Freescale common code for Local Access Window
1064
1065 config SECURE_BOOT
1066         bool    "Secure Boot"
1067         help
1068                 Enable Freescale Secure Boot feature. Normally selected
1069                 by defconfig. If unsure, do not change.
1070
1071 config MAX_CPUS
1072         int "Maximum number of CPUs permitted for MPC85xx"
1073         default 12 if ARCH_T4240
1074         default 8 if ARCH_P4080 || \
1075                      ARCH_T4160
1076         default 4 if ARCH_B4860 || \
1077                      ARCH_P2041 || \
1078                      ARCH_P3041 || \
1079                      ARCH_P5040 || \
1080                      ARCH_T1040 || \
1081                      ARCH_T1042 || \
1082                      ARCH_T2080 || \
1083                      ARCH_T2081
1084         default 2 if ARCH_B4420 || \
1085                      ARCH_BSC9132 || \
1086                      ARCH_MPC8572 || \
1087                      ARCH_P1020 || \
1088                      ARCH_P1021 || \
1089                      ARCH_P1022 || \
1090                      ARCH_P1023 || \
1091                      ARCH_P1024 || \
1092                      ARCH_P1025 || \
1093                      ARCH_P2020 || \
1094                      ARCH_P5020 || \
1095                      ARCH_T1023 || \
1096                      ARCH_T1024
1097         default 1
1098         help
1099           Set this number to the maximum number of possible CPUs in the SoC.
1100           SoCs may have multiple clusters with each cluster may have multiple
1101           ports. If some ports are reserved but higher ports are used for
1102           cores, count the reserved ports. This will allocate enough memory
1103           in spin table to properly handle all cores.
1104
1105 config SYS_CCSRBAR_DEFAULT
1106         hex "Default CCSRBAR address"
1107         default 0xff700000 if   ARCH_BSC9131    || \
1108                                 ARCH_BSC9132    || \
1109                                 ARCH_C29X       || \
1110                                 ARCH_MPC8536    || \
1111                                 ARCH_MPC8540    || \
1112                                 ARCH_MPC8541    || \
1113                                 ARCH_MPC8544    || \
1114                                 ARCH_MPC8548    || \
1115                                 ARCH_MPC8555    || \
1116                                 ARCH_MPC8560    || \
1117                                 ARCH_MPC8568    || \
1118                                 ARCH_MPC8569    || \
1119                                 ARCH_MPC8572    || \
1120                                 ARCH_P1010      || \
1121                                 ARCH_P1011      || \
1122                                 ARCH_P1020      || \
1123                                 ARCH_P1021      || \
1124                                 ARCH_P1022      || \
1125                                 ARCH_P1024      || \
1126                                 ARCH_P1025      || \
1127                                 ARCH_P2020
1128         default 0xff600000 if   ARCH_P1023
1129         default 0xfe000000 if   ARCH_B4420      || \
1130                                 ARCH_B4860      || \
1131                                 ARCH_P2041      || \
1132                                 ARCH_P3041      || \
1133                                 ARCH_P4080      || \
1134                                 ARCH_P5020      || \
1135                                 ARCH_P5040      || \
1136                                 ARCH_T1023      || \
1137                                 ARCH_T1024      || \
1138                                 ARCH_T1040      || \
1139                                 ARCH_T1042      || \
1140                                 ARCH_T2080      || \
1141                                 ARCH_T2081      || \
1142                                 ARCH_T4160      || \
1143                                 ARCH_T4240
1144         default 0xe0000000 if ARCH_QEMU_E500
1145         help
1146                 Default value of CCSRBAR comes from power-on-reset. It
1147                 is fixed on each SoC. Some SoCs can have different value
1148                 if changed by pre-boot regime. The value here must match
1149                 the current value in SoC. If not sure, do not change.
1150
1151 config SYS_FSL_ERRATUM_A004468
1152         bool
1153
1154 config SYS_FSL_ERRATUM_A004477
1155         bool
1156
1157 config SYS_FSL_ERRATUM_A004508
1158         bool
1159
1160 config SYS_FSL_ERRATUM_A004580
1161         bool
1162
1163 config SYS_FSL_ERRATUM_A004699
1164         bool
1165
1166 config SYS_FSL_ERRATUM_A004849
1167         bool
1168
1169 config SYS_FSL_ERRATUM_A004510
1170         bool
1171
1172 config SYS_FSL_ERRATUM_A004510_SVR_REV
1173         hex
1174         depends on SYS_FSL_ERRATUM_A004510
1175         default 0x20 if ARCH_P4080
1176         default 0x10
1177
1178 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1179         hex
1180         depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1181         default 0x11
1182
1183 config SYS_FSL_ERRATUM_A005125
1184         bool
1185
1186 config SYS_FSL_ERRATUM_A005434
1187         bool
1188
1189 config SYS_FSL_ERRATUM_A005812
1190         bool
1191
1192 config SYS_FSL_ERRATUM_A005871
1193         bool
1194
1195 config SYS_FSL_ERRATUM_A006261
1196         bool
1197
1198 config SYS_FSL_ERRATUM_A006379
1199         bool
1200
1201 config SYS_FSL_ERRATUM_A006384
1202         bool
1203
1204 config SYS_FSL_ERRATUM_A006475
1205         bool
1206
1207 config SYS_FSL_ERRATUM_A006593
1208         bool
1209
1210 config SYS_FSL_ERRATUM_A007075
1211         bool
1212
1213 config SYS_FSL_ERRATUM_A007186
1214         bool
1215
1216 config SYS_FSL_ERRATUM_A007212
1217         bool
1218
1219 config SYS_FSL_ERRATUM_A007815
1220         bool
1221
1222 config SYS_FSL_ERRATUM_A007798
1223         bool
1224
1225 config SYS_FSL_ERRATUM_A007907
1226         bool
1227
1228 config SYS_FSL_ERRATUM_A008044
1229         bool
1230
1231 config SYS_FSL_ERRATUM_CPC_A002
1232         bool
1233
1234 config SYS_FSL_ERRATUM_CPC_A003
1235         bool
1236
1237 config SYS_FSL_ERRATUM_CPU_A003999
1238         bool
1239
1240 config SYS_FSL_ERRATUM_ELBC_A001
1241         bool
1242
1243 config SYS_FSL_ERRATUM_I2C_A004447
1244         bool
1245
1246 config SYS_FSL_A004447_SVR_REV
1247         hex
1248         depends on SYS_FSL_ERRATUM_I2C_A004447
1249         default 0x00 if ARCH_MPC8548
1250         default 0x10 if ARCH_P1010
1251         default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1252         default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1253
1254 config SYS_FSL_ERRATUM_IFC_A002769
1255         bool
1256
1257 config SYS_FSL_ERRATUM_IFC_A003399
1258         bool
1259
1260 config SYS_FSL_ERRATUM_NMG_CPU_A011
1261         bool
1262
1263 config SYS_FSL_ERRATUM_NMG_ETSEC129
1264         bool
1265
1266 config SYS_FSL_ERRATUM_NMG_LBC103
1267         bool
1268
1269 config SYS_FSL_ERRATUM_P1010_A003549
1270         bool
1271
1272 config SYS_FSL_ERRATUM_SATA_A001
1273         bool
1274
1275 config SYS_FSL_ERRATUM_SEC_A003571
1276         bool
1277
1278 config SYS_FSL_ERRATUM_SRIO_A004034
1279         bool
1280
1281 config SYS_FSL_ERRATUM_USB14
1282         bool
1283
1284 config SYS_P4080_ERRATUM_CPU22
1285         bool
1286
1287 config SYS_P4080_ERRATUM_PCIE_A003
1288         bool
1289
1290 config SYS_P4080_ERRATUM_SERDES8
1291         bool
1292
1293 config SYS_P4080_ERRATUM_SERDES9
1294         bool
1295
1296 config SYS_P4080_ERRATUM_SERDES_A001
1297         bool
1298
1299 config SYS_P4080_ERRATUM_SERDES_A005
1300         bool
1301
1302 config SYS_FSL_QORIQ_CHASSIS1
1303         bool
1304
1305 config SYS_FSL_QORIQ_CHASSIS2
1306         bool
1307
1308 config SYS_FSL_NUM_LAWS
1309         int "Number of local access windows"
1310         depends on FSL_LAW
1311         default 32 if   ARCH_B4420      || \
1312                         ARCH_B4860      || \
1313                         ARCH_P2041      || \
1314                         ARCH_P3041      || \
1315                         ARCH_P4080      || \
1316                         ARCH_P5020      || \
1317                         ARCH_P5040      || \
1318                         ARCH_T2080      || \
1319                         ARCH_T2081      || \
1320                         ARCH_T4160      || \
1321                         ARCH_T4240
1322         default 16 if   ARCH_T1023      || \
1323                         ARCH_T1024      || \
1324                         ARCH_T1040      || \
1325                         ARCH_T1042
1326         default 12 if   ARCH_BSC9131    || \
1327                         ARCH_BSC9132    || \
1328                         ARCH_C29X       || \
1329                         ARCH_MPC8536    || \
1330                         ARCH_MPC8572    || \
1331                         ARCH_P1010      || \
1332                         ARCH_P1011      || \
1333                         ARCH_P1020      || \
1334                         ARCH_P1021      || \
1335                         ARCH_P1022      || \
1336                         ARCH_P1023      || \
1337                         ARCH_P1024      || \
1338                         ARCH_P1025      || \
1339                         ARCH_P2020
1340         default 10 if   ARCH_MPC8544    || \
1341                         ARCH_MPC8548    || \
1342                         ARCH_MPC8568    || \
1343                         ARCH_MPC8569
1344         default 8 if    ARCH_MPC8540    || \
1345                         ARCH_MPC8541    || \
1346                         ARCH_MPC8555    || \
1347                         ARCH_MPC8560
1348         help
1349                 Number of local access windows. This is fixed per SoC.
1350                 If not sure, do not change.
1351
1352 config SYS_FSL_THREADS_PER_CORE
1353         int
1354         default 2 if E6500
1355         default 1
1356
1357 config SYS_NUM_TLBCAMS
1358         int "Number of TLB CAM entries"
1359         default 64 if E500MC
1360         default 16
1361         help
1362                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1363                 16 for other E500 SoCs.
1364
1365 config SYS_PPC64
1366         bool
1367
1368 config SYS_PPC_E500_USE_DEBUG_TLB
1369         bool
1370
1371 config FSL_IFC
1372         bool
1373
1374 config FSL_ELBC
1375         bool
1376
1377 config SYS_PPC_E500_DEBUG_TLB
1378         int "Temporary TLB entry for external debugger"
1379         depends on SYS_PPC_E500_USE_DEBUG_TLB
1380         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
1381         default 1 if    ARCH_MPC8536
1382         default 2 if    ARCH_MPC8572    || \
1383                         ARCH_P1011      || \
1384                         ARCH_P1020      || \
1385                         ARCH_P1021      || \
1386                         ARCH_P1022      || \
1387                         ARCH_P1024      || \
1388                         ARCH_P1025      || \
1389                         ARCH_P2020
1390         default 3 if    ARCH_P1010      || \
1391                         ARCH_BSC9132    || \
1392                         ARCH_C29X
1393         help
1394                 Select a temporary TLB entry to be used during boot to work
1395                 around limitations in e500v1 and e500v2 external debugger
1396                 support. This reduces the portions of the boot code where
1397                 breakpoints and single stepping do not work. The value of this
1398                 symbol should be set to the TLB1 entry to be used for this
1399                 purpose. If unsure, do not change.
1400
1401 config SYS_FSL_IFC_CLK_DIV
1402         int "Divider of platform clock"
1403         depends on FSL_IFC
1404         default 2 if    ARCH_B4420      || \
1405                         ARCH_B4860      || \
1406                         ARCH_T1024      || \
1407                         ARCH_T1023      || \
1408                         ARCH_T1040      || \
1409                         ARCH_T1042      || \
1410                         ARCH_T4160      || \
1411                         ARCH_T4240
1412         default 1
1413         help
1414                 Defines divider of platform clock(clock input to
1415                 IFC controller).
1416
1417 config SYS_FSL_LBC_CLK_DIV
1418         int "Divider of platform clock"
1419         depends on FSL_ELBC || ARCH_MPC8540 || \
1420                 ARCH_MPC8548 || ARCH_MPC8541 || \
1421                 ARCH_MPC8555 || ARCH_MPC8560 || \
1422                 ARCH_MPC8568
1423
1424         default 2 if    ARCH_P2041      || \
1425                         ARCH_P3041      || \
1426                         ARCH_P4080      || \
1427                         ARCH_P5020      || \
1428                         ARCH_P5040
1429         default 1
1430
1431         help
1432                 Defines divider of platform clock(clock input to
1433                 eLBC controller).
1434
1435 source "board/freescale/b4860qds/Kconfig"
1436 source "board/freescale/bsc9131rdb/Kconfig"
1437 source "board/freescale/bsc9132qds/Kconfig"
1438 source "board/freescale/c29xpcie/Kconfig"
1439 source "board/freescale/corenet_ds/Kconfig"
1440 source "board/freescale/mpc8536ds/Kconfig"
1441 source "board/freescale/mpc8541cds/Kconfig"
1442 source "board/freescale/mpc8544ds/Kconfig"
1443 source "board/freescale/mpc8548cds/Kconfig"
1444 source "board/freescale/mpc8555cds/Kconfig"
1445 source "board/freescale/mpc8568mds/Kconfig"
1446 source "board/freescale/mpc8569mds/Kconfig"
1447 source "board/freescale/mpc8572ds/Kconfig"
1448 source "board/freescale/p1010rdb/Kconfig"
1449 source "board/freescale/p1022ds/Kconfig"
1450 source "board/freescale/p1023rdb/Kconfig"
1451 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1452 source "board/freescale/p1_twr/Kconfig"
1453 source "board/freescale/p2041rdb/Kconfig"
1454 source "board/freescale/qemu-ppce500/Kconfig"
1455 source "board/freescale/t102xqds/Kconfig"
1456 source "board/freescale/t102xrdb/Kconfig"
1457 source "board/freescale/t1040qds/Kconfig"
1458 source "board/freescale/t104xrdb/Kconfig"
1459 source "board/freescale/t208xqds/Kconfig"
1460 source "board/freescale/t208xrdb/Kconfig"
1461 source "board/freescale/t4qds/Kconfig"
1462 source "board/freescale/t4rdb/Kconfig"
1463 source "board/gdsys/p1022/Kconfig"
1464 source "board/keymile/kmp204x/Kconfig"
1465 source "board/sbc8548/Kconfig"
1466 source "board/socrates/Kconfig"
1467 source "board/varisys/cyrus/Kconfig"
1468 source "board/xes/xpedite520x/Kconfig"
1469 source "board/xes/xpedite537x/Kconfig"
1470 source "board/xes/xpedite550x/Kconfig"
1471 source "board/Arcturus/ucp1020/Kconfig"
1472
1473 endmenu