8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
20 bool "Support sbc8548"
23 config TARGET_SOCRATES
24 bool "Support socrates"
28 bool "Support P3041DS"
31 select BOARD_LATE_INIT if CHAIN_OF_TRUST
36 bool "Support P4080DS"
39 select BOARD_LATE_INIT if CHAIN_OF_TRUST
44 bool "Support P5020DS"
47 select BOARD_LATE_INIT if CHAIN_OF_TRUST
52 bool "Support P5040DS"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
59 config TARGET_MPC8541CDS
60 bool "Support MPC8541CDS"
63 config TARGET_MPC8544DS
64 bool "Support MPC8544DS"
68 config TARGET_MPC8548CDS
69 bool "Support MPC8548CDS"
72 config TARGET_MPC8555CDS
73 bool "Support MPC8555CDS"
76 config TARGET_MPC8568MDS
77 bool "Support MPC8568MDS"
80 config TARGET_MPC8569MDS
81 bool "Support MPC8569MDS"
84 config TARGET_MPC8572DS
85 bool "Support MPC8572DS"
87 # Use DDR3 controller with DDR2 DIMMs on this board
88 select SYS_FSL_DDRC_GEN3
92 config TARGET_P1010RDB_PA
93 bool "Support P1010RDB_PA"
95 select BOARD_LATE_INIT if CHAIN_OF_TRUST
102 config TARGET_P1010RDB_PB
103 bool "Support P1010RDB_PB"
105 select BOARD_LATE_INIT if CHAIN_OF_TRUST
112 config TARGET_P1020MBG
113 bool "Support P1020MBG-PC"
121 config TARGET_P1020RDB_PC
122 bool "Support P1020RDB-PC"
130 config TARGET_P1020RDB_PD
131 bool "Support P1020RDB-PD"
139 config TARGET_P1020UTM
140 bool "Support P1020UTM"
148 config TARGET_P1021RDB
149 bool "Support P1021RDB"
157 config TARGET_P1024RDB
158 bool "Support P1024RDB"
166 config TARGET_P2020RDB
167 bool "Support P2020RDB-PC"
175 config TARGET_P2041RDB
176 bool "Support P2041RDB"
178 select BOARD_LATE_INIT if CHAIN_OF_TRUST
183 config TARGET_QEMU_PPCE500
184 bool "Support qemu-ppce500"
185 select ARCH_QEMU_E500
188 config TARGET_T1023RDB
189 bool "Support T1023RDB"
191 select BOARD_LATE_INIT if CHAIN_OF_TRUST
194 select FSL_DDR_INTERACTIVE
198 config TARGET_T1024RDB
199 bool "Support T1024RDB"
201 select BOARD_LATE_INIT if CHAIN_OF_TRUST
204 select FSL_DDR_INTERACTIVE
208 config TARGET_T1040RDB
209 bool "Support T1040RDB"
211 select BOARD_LATE_INIT if CHAIN_OF_TRUST
217 config TARGET_T1040D4RDB
218 bool "Support T1040D4RDB"
220 select BOARD_LATE_INIT if CHAIN_OF_TRUST
226 config TARGET_T1042RDB
227 bool "Support T1042RDB"
229 select BOARD_LATE_INIT if CHAIN_OF_TRUST
234 config TARGET_T1042D4RDB
235 bool "Support T1042D4RDB"
237 select BOARD_LATE_INIT if CHAIN_OF_TRUST
243 config TARGET_T1042RDB_PI
244 bool "Support T1042RDB_PI"
246 select BOARD_LATE_INIT if CHAIN_OF_TRUST
252 config TARGET_T2080QDS
253 bool "Support T2080QDS"
255 select BOARD_LATE_INIT if CHAIN_OF_TRUST
258 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
259 select FSL_DDR_INTERACTIVE
262 config TARGET_T2080RDB
263 bool "Support T2080RDB"
265 select BOARD_LATE_INIT if CHAIN_OF_TRUST
271 config TARGET_T2081QDS
272 bool "Support T2081QDS"
276 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
277 select FSL_DDR_INTERACTIVE
279 config TARGET_T4160RDB
280 bool "Support T4160RDB"
286 config TARGET_T4240RDB
287 bool "Support T4240RDB"
291 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
295 config TARGET_CONTROLCENTERD
296 bool "Support controlcenterd"
299 config TARGET_KMP204X
300 bool "Support kmp204x"
303 config TARGET_XPEDITE520X
304 bool "Support xpedite520x"
307 config TARGET_XPEDITE537X
308 bool "Support xpedite537x"
310 # Use DDR3 controller with DDR2 DIMMs on this board
311 select SYS_FSL_DDRC_GEN3
313 config TARGET_XPEDITE550X
314 bool "Support xpedite550x"
317 config TARGET_UCP1020
318 bool "Support uCP1020"
323 config TARGET_CYRUS_P5020
324 bool "Support Varisys Cyrus P5020"
329 config TARGET_CYRUS_P5040
330 bool "Support Varisys Cyrus P5040"
342 select SYS_FSL_DDR_VER_47
343 select SYS_FSL_ERRATUM_A004477
344 select SYS_FSL_ERRATUM_A005871
345 select SYS_FSL_ERRATUM_A006379
346 select SYS_FSL_ERRATUM_A006384
347 select SYS_FSL_ERRATUM_A006475
348 select SYS_FSL_ERRATUM_A006593
349 select SYS_FSL_ERRATUM_A007075
350 select SYS_FSL_ERRATUM_A007186
351 select SYS_FSL_ERRATUM_A007212
352 select SYS_FSL_ERRATUM_A009942
353 select SYS_FSL_HAS_DDR3
354 select SYS_FSL_HAS_SEC
355 select SYS_FSL_QORIQ_CHASSIS2
356 select SYS_FSL_SEC_BE
357 select SYS_FSL_SEC_COMPAT_4
369 select SYS_FSL_DDR_VER_47
370 select SYS_FSL_ERRATUM_A004477
371 select SYS_FSL_ERRATUM_A005871
372 select SYS_FSL_ERRATUM_A006379
373 select SYS_FSL_ERRATUM_A006384
374 select SYS_FSL_ERRATUM_A006475
375 select SYS_FSL_ERRATUM_A006593
376 select SYS_FSL_ERRATUM_A007075
377 select SYS_FSL_ERRATUM_A007186
378 select SYS_FSL_ERRATUM_A007212
379 select SYS_FSL_ERRATUM_A007907
380 select SYS_FSL_ERRATUM_A009942
381 select SYS_FSL_HAS_DDR3
382 select SYS_FSL_HAS_SEC
383 select SYS_FSL_QORIQ_CHASSIS2
384 select SYS_FSL_SEC_BE
385 select SYS_FSL_SEC_COMPAT_4
395 select SYS_FSL_DDR_VER_44
396 select SYS_FSL_ERRATUM_A004477
397 select SYS_FSL_ERRATUM_A005125
398 select SYS_FSL_ERRATUM_ESDHC111
399 select SYS_FSL_HAS_DDR3
400 select SYS_FSL_HAS_SEC
401 select SYS_FSL_SEC_BE
402 select SYS_FSL_SEC_COMPAT_4
411 select SYS_FSL_DDR_VER_46
412 select SYS_FSL_ERRATUM_A004477
413 select SYS_FSL_ERRATUM_A005125
414 select SYS_FSL_ERRATUM_A005434
415 select SYS_FSL_ERRATUM_ESDHC111
416 select SYS_FSL_ERRATUM_I2C_A004447
417 select SYS_FSL_ERRATUM_IFC_A002769
418 select FSL_PCIE_RESET
419 select SYS_FSL_HAS_DDR3
420 select SYS_FSL_HAS_SEC
421 select SYS_FSL_SEC_BE
422 select SYS_FSL_SEC_COMPAT_4
423 select SYS_PPC_E500_USE_DEBUG_TLB
434 select SYS_FSL_DDR_VER_46
435 select SYS_FSL_ERRATUM_A005125
436 select SYS_FSL_ERRATUM_ESDHC111
437 select FSL_PCIE_RESET
438 select SYS_FSL_HAS_DDR3
439 select SYS_FSL_HAS_SEC
440 select SYS_FSL_SEC_BE
441 select SYS_FSL_SEC_COMPAT_6
442 select SYS_PPC_E500_USE_DEBUG_TLB
451 select SYS_FSL_ERRATUM_A004508
452 select SYS_FSL_ERRATUM_A005125
453 select FSL_PCIE_RESET
454 select SYS_FSL_HAS_DDR2
455 select SYS_FSL_HAS_DDR3
456 select SYS_FSL_HAS_SEC
457 select SYS_FSL_SEC_BE
458 select SYS_FSL_SEC_COMPAT_2
459 select SYS_PPC_E500_USE_DEBUG_TLB
468 select SYS_FSL_HAS_DDR1
473 select SYS_FSL_HAS_DDR1
474 select SYS_FSL_HAS_SEC
475 select SYS_FSL_SEC_BE
476 select SYS_FSL_SEC_COMPAT_2
481 select SYS_FSL_ERRATUM_A005125
482 select FSL_PCIE_RESET
483 select SYS_FSL_HAS_DDR2
484 select SYS_FSL_HAS_SEC
485 select SYS_FSL_SEC_BE
486 select SYS_FSL_SEC_COMPAT_2
487 select SYS_PPC_E500_USE_DEBUG_TLB
493 select SYS_FSL_ERRATUM_A005125
494 select SYS_FSL_ERRATUM_NMG_DDR120
495 select SYS_FSL_ERRATUM_NMG_LBC103
496 select SYS_FSL_ERRATUM_NMG_ETSEC129
497 select SYS_FSL_ERRATUM_I2C_A004447
498 select FSL_PCIE_RESET
499 select SYS_FSL_HAS_DDR2
500 select SYS_FSL_HAS_DDR1
501 select SYS_FSL_HAS_SEC
502 select SYS_FSL_SEC_BE
503 select SYS_FSL_SEC_COMPAT_2
504 select SYS_PPC_E500_USE_DEBUG_TLB
510 select SYS_FSL_HAS_DDR1
511 select SYS_FSL_HAS_SEC
512 select SYS_FSL_SEC_BE
513 select SYS_FSL_SEC_COMPAT_2
518 select SYS_FSL_HAS_DDR1
523 select FSL_PCIE_RESET
524 select SYS_FSL_HAS_DDR2
525 select SYS_FSL_HAS_SEC
526 select SYS_FSL_SEC_BE
527 select SYS_FSL_SEC_COMPAT_2
532 select SYS_FSL_ERRATUM_A004508
533 select SYS_FSL_ERRATUM_A005125
534 select FSL_PCIE_RESET
535 select SYS_FSL_HAS_DDR3
536 select SYS_FSL_HAS_SEC
537 select SYS_FSL_SEC_BE
538 select SYS_FSL_SEC_COMPAT_2
545 select SYS_FSL_ERRATUM_A004508
546 select SYS_FSL_ERRATUM_A005125
547 select SYS_FSL_ERRATUM_DDR_115
548 select SYS_FSL_ERRATUM_DDR111_DDR134
549 select FSL_PCIE_RESET
550 select SYS_FSL_HAS_DDR2
551 select SYS_FSL_HAS_DDR3
552 select SYS_FSL_HAS_SEC
553 select SYS_FSL_SEC_BE
554 select SYS_FSL_SEC_COMPAT_2
555 select SYS_PPC_E500_USE_DEBUG_TLB
562 select SYS_FSL_ERRATUM_A004477
563 select SYS_FSL_ERRATUM_A004508
564 select SYS_FSL_ERRATUM_A005125
565 select SYS_FSL_ERRATUM_A005275
566 select SYS_FSL_ERRATUM_A006261
567 select SYS_FSL_ERRATUM_A007075
568 select SYS_FSL_ERRATUM_ESDHC111
569 select SYS_FSL_ERRATUM_I2C_A004447
570 select SYS_FSL_ERRATUM_IFC_A002769
571 select SYS_FSL_ERRATUM_P1010_A003549
572 select SYS_FSL_ERRATUM_SEC_A003571
573 select SYS_FSL_ERRATUM_IFC_A003399
574 select FSL_PCIE_RESET
575 select SYS_FSL_HAS_DDR3
576 select SYS_FSL_HAS_SEC
577 select SYS_FSL_SEC_BE
578 select SYS_FSL_SEC_COMPAT_4
579 select SYS_PPC_E500_USE_DEBUG_TLB
592 select SYS_FSL_ERRATUM_A004508
593 select SYS_FSL_ERRATUM_A005125
594 select SYS_FSL_ERRATUM_ELBC_A001
595 select SYS_FSL_ERRATUM_ESDHC111
596 select FSL_PCIE_DISABLE_ASPM
597 select SYS_FSL_HAS_DDR3
598 select SYS_FSL_HAS_SEC
599 select SYS_FSL_SEC_BE
600 select SYS_FSL_SEC_COMPAT_2
601 select SYS_PPC_E500_USE_DEBUG_TLB
607 select SYS_FSL_ERRATUM_A004508
608 select SYS_FSL_ERRATUM_A005125
609 select SYS_FSL_ERRATUM_ELBC_A001
610 select SYS_FSL_ERRATUM_ESDHC111
611 select FSL_PCIE_DISABLE_ASPM
612 select FSL_PCIE_RESET
613 select SYS_FSL_HAS_DDR3
614 select SYS_FSL_HAS_SEC
615 select SYS_FSL_SEC_BE
616 select SYS_FSL_SEC_COMPAT_2
617 select SYS_PPC_E500_USE_DEBUG_TLB
628 select SYS_FSL_ERRATUM_A004508
629 select SYS_FSL_ERRATUM_A005125
630 select SYS_FSL_ERRATUM_ELBC_A001
631 select SYS_FSL_ERRATUM_ESDHC111
632 select FSL_PCIE_DISABLE_ASPM
633 select FSL_PCIE_RESET
634 select SYS_FSL_HAS_DDR3
635 select SYS_FSL_HAS_SEC
636 select SYS_FSL_SEC_BE
637 select SYS_FSL_SEC_COMPAT_2
638 select SYS_PPC_E500_USE_DEBUG_TLB
649 select SYS_FSL_ERRATUM_A004477
650 select SYS_FSL_ERRATUM_A004508
651 select SYS_FSL_ERRATUM_A005125
652 select SYS_FSL_ERRATUM_ELBC_A001
653 select SYS_FSL_ERRATUM_ESDHC111
654 select SYS_FSL_ERRATUM_SATA_A001
655 select FSL_PCIE_RESET
656 select SYS_FSL_HAS_DDR3
657 select SYS_FSL_HAS_SEC
658 select SYS_FSL_SEC_BE
659 select SYS_FSL_SEC_COMPAT_2
660 select SYS_PPC_E500_USE_DEBUG_TLB
666 select SYS_FSL_ERRATUM_A004508
667 select SYS_FSL_ERRATUM_A005125
668 select SYS_FSL_ERRATUM_I2C_A004447
669 select FSL_PCIE_RESET
670 select SYS_FSL_HAS_DDR3
671 select SYS_FSL_HAS_SEC
672 select SYS_FSL_SEC_BE
673 select SYS_FSL_SEC_COMPAT_4
679 select SYS_FSL_ERRATUM_A004508
680 select SYS_FSL_ERRATUM_A005125
681 select SYS_FSL_ERRATUM_ELBC_A001
682 select SYS_FSL_ERRATUM_ESDHC111
683 select FSL_PCIE_DISABLE_ASPM
684 select FSL_PCIE_RESET
685 select SYS_FSL_HAS_DDR3
686 select SYS_FSL_HAS_SEC
687 select SYS_FSL_SEC_BE
688 select SYS_FSL_SEC_COMPAT_2
689 select SYS_PPC_E500_USE_DEBUG_TLB
701 select SYS_FSL_ERRATUM_A004508
702 select SYS_FSL_ERRATUM_A005125
703 select SYS_FSL_ERRATUM_ELBC_A001
704 select SYS_FSL_ERRATUM_ESDHC111
705 select FSL_PCIE_DISABLE_ASPM
706 select FSL_PCIE_RESET
707 select SYS_FSL_HAS_DDR3
708 select SYS_FSL_HAS_SEC
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_2
711 select SYS_PPC_E500_USE_DEBUG_TLB
719 select SYS_FSL_ERRATUM_A004477
720 select SYS_FSL_ERRATUM_A004508
721 select SYS_FSL_ERRATUM_A005125
722 select SYS_FSL_ERRATUM_ESDHC111
723 select SYS_FSL_ERRATUM_ESDHC_A001
724 select FSL_PCIE_RESET
725 select SYS_FSL_HAS_DDR3
726 select SYS_FSL_HAS_SEC
727 select SYS_FSL_SEC_BE
728 select SYS_FSL_SEC_COMPAT_2
729 select SYS_PPC_E500_USE_DEBUG_TLB
739 select SYS_FSL_ERRATUM_A004510
740 select SYS_FSL_ERRATUM_A004849
741 select SYS_FSL_ERRATUM_A005275
742 select SYS_FSL_ERRATUM_A006261
743 select SYS_FSL_ERRATUM_CPU_A003999
744 select SYS_FSL_ERRATUM_DDR_A003
745 select SYS_FSL_ERRATUM_DDR_A003474
746 select SYS_FSL_ERRATUM_ESDHC111
747 select SYS_FSL_ERRATUM_I2C_A004447
748 select SYS_FSL_ERRATUM_NMG_CPU_A011
749 select SYS_FSL_ERRATUM_SRIO_A004034
750 select SYS_FSL_ERRATUM_USB14
751 select SYS_FSL_HAS_DDR3
752 select SYS_FSL_HAS_SEC
753 select SYS_FSL_QORIQ_CHASSIS1
754 select SYS_FSL_SEC_BE
755 select SYS_FSL_SEC_COMPAT_4
763 select SYS_FSL_DDR_VER_44
764 select SYS_FSL_ERRATUM_A004510
765 select SYS_FSL_ERRATUM_A004849
766 select SYS_FSL_ERRATUM_A005275
767 select SYS_FSL_ERRATUM_A005812
768 select SYS_FSL_ERRATUM_A006261
769 select SYS_FSL_ERRATUM_CPU_A003999
770 select SYS_FSL_ERRATUM_DDR_A003
771 select SYS_FSL_ERRATUM_DDR_A003474
772 select SYS_FSL_ERRATUM_ESDHC111
773 select SYS_FSL_ERRATUM_I2C_A004447
774 select SYS_FSL_ERRATUM_NMG_CPU_A011
775 select SYS_FSL_ERRATUM_SRIO_A004034
776 select SYS_FSL_ERRATUM_USB14
777 select SYS_FSL_HAS_DDR3
778 select SYS_FSL_HAS_SEC
779 select SYS_FSL_QORIQ_CHASSIS1
780 select SYS_FSL_SEC_BE
781 select SYS_FSL_SEC_COMPAT_4
792 select SYS_FSL_DDR_VER_44
793 select SYS_FSL_ERRATUM_A004510
794 select SYS_FSL_ERRATUM_A004580
795 select SYS_FSL_ERRATUM_A004849
796 select SYS_FSL_ERRATUM_A005812
797 select SYS_FSL_ERRATUM_A007075
798 select SYS_FSL_ERRATUM_CPC_A002
799 select SYS_FSL_ERRATUM_CPC_A003
800 select SYS_FSL_ERRATUM_CPU_A003999
801 select SYS_FSL_ERRATUM_DDR_A003
802 select SYS_FSL_ERRATUM_DDR_A003474
803 select SYS_FSL_ERRATUM_ELBC_A001
804 select SYS_FSL_ERRATUM_ESDHC111
805 select SYS_FSL_ERRATUM_ESDHC13
806 select SYS_FSL_ERRATUM_ESDHC135
807 select SYS_FSL_ERRATUM_I2C_A004447
808 select SYS_FSL_ERRATUM_NMG_CPU_A011
809 select SYS_FSL_ERRATUM_SRIO_A004034
810 select SYS_P4080_ERRATUM_CPU22
811 select SYS_P4080_ERRATUM_PCIE_A003
812 select SYS_P4080_ERRATUM_SERDES8
813 select SYS_P4080_ERRATUM_SERDES9
814 select SYS_P4080_ERRATUM_SERDES_A001
815 select SYS_P4080_ERRATUM_SERDES_A005
816 select SYS_FSL_HAS_DDR3
817 select SYS_FSL_HAS_SEC
818 select SYS_FSL_QORIQ_CHASSIS1
819 select SYS_FSL_SEC_BE
820 select SYS_FSL_SEC_COMPAT_4
830 select SYS_FSL_DDR_VER_44
831 select SYS_FSL_ERRATUM_A004510
832 select SYS_FSL_ERRATUM_A005275
833 select SYS_FSL_ERRATUM_A006261
834 select SYS_FSL_ERRATUM_DDR_A003
835 select SYS_FSL_ERRATUM_DDR_A003474
836 select SYS_FSL_ERRATUM_ESDHC111
837 select SYS_FSL_ERRATUM_I2C_A004447
838 select SYS_FSL_ERRATUM_SRIO_A004034
839 select SYS_FSL_ERRATUM_USB14
840 select SYS_FSL_HAS_DDR3
841 select SYS_FSL_HAS_SEC
842 select SYS_FSL_QORIQ_CHASSIS1
843 select SYS_FSL_SEC_BE
844 select SYS_FSL_SEC_COMPAT_4
855 select SYS_FSL_DDR_VER_44
856 select SYS_FSL_ERRATUM_A004510
857 select SYS_FSL_ERRATUM_A004699
858 select SYS_FSL_ERRATUM_A005275
859 select SYS_FSL_ERRATUM_A005812
860 select SYS_FSL_ERRATUM_A006261
861 select SYS_FSL_ERRATUM_DDR_A003
862 select SYS_FSL_ERRATUM_DDR_A003474
863 select SYS_FSL_ERRATUM_ESDHC111
864 select SYS_FSL_ERRATUM_USB14
865 select SYS_FSL_HAS_DDR3
866 select SYS_FSL_HAS_SEC
867 select SYS_FSL_QORIQ_CHASSIS1
868 select SYS_FSL_SEC_BE
869 select SYS_FSL_SEC_COMPAT_4
876 config ARCH_QEMU_E500
883 select SYS_FSL_DDR_VER_50
884 select SYS_FSL_ERRATUM_A008378
885 select SYS_FSL_ERRATUM_A008109
886 select SYS_FSL_ERRATUM_A009663
887 select SYS_FSL_ERRATUM_A009942
888 select SYS_FSL_ERRATUM_ESDHC111
889 select SYS_FSL_HAS_DDR3
890 select SYS_FSL_HAS_DDR4
891 select SYS_FSL_HAS_SEC
892 select SYS_FSL_QORIQ_CHASSIS2
893 select SYS_FSL_SEC_BE
894 select SYS_FSL_SEC_COMPAT_5
904 select SYS_FSL_DDR_VER_50
905 select SYS_FSL_ERRATUM_A008378
906 select SYS_FSL_ERRATUM_A008109
907 select SYS_FSL_ERRATUM_A009663
908 select SYS_FSL_ERRATUM_A009942
909 select SYS_FSL_ERRATUM_ESDHC111
910 select SYS_FSL_HAS_DDR3
911 select SYS_FSL_HAS_DDR4
912 select SYS_FSL_HAS_SEC
913 select SYS_FSL_QORIQ_CHASSIS2
914 select SYS_FSL_SEC_BE
915 select SYS_FSL_SEC_COMPAT_5
926 select SYS_FSL_DDR_VER_50
927 select SYS_FSL_ERRATUM_A008044
928 select SYS_FSL_ERRATUM_A008378
929 select SYS_FSL_ERRATUM_A008109
930 select SYS_FSL_ERRATUM_A009663
931 select SYS_FSL_ERRATUM_A009942
932 select SYS_FSL_ERRATUM_ESDHC111
933 select SYS_FSL_HAS_DDR3
934 select SYS_FSL_HAS_DDR4
935 select SYS_FSL_HAS_SEC
936 select SYS_FSL_QORIQ_CHASSIS2
937 select SYS_FSL_SEC_BE
938 select SYS_FSL_SEC_COMPAT_5
950 select SYS_FSL_DDR_VER_50
951 select SYS_FSL_ERRATUM_A008044
952 select SYS_FSL_ERRATUM_A008378
953 select SYS_FSL_ERRATUM_A008109
954 select SYS_FSL_ERRATUM_A009663
955 select SYS_FSL_ERRATUM_A009942
956 select SYS_FSL_ERRATUM_ESDHC111
957 select SYS_FSL_HAS_DDR3
958 select SYS_FSL_HAS_DDR4
959 select SYS_FSL_HAS_SEC
960 select SYS_FSL_QORIQ_CHASSIS2
961 select SYS_FSL_SEC_BE
962 select SYS_FSL_SEC_COMPAT_5
975 select SYS_FSL_DDR_VER_47
976 select SYS_FSL_ERRATUM_A006379
977 select SYS_FSL_ERRATUM_A006593
978 select SYS_FSL_ERRATUM_A007186
979 select SYS_FSL_ERRATUM_A007212
980 select SYS_FSL_ERRATUM_A007815
981 select SYS_FSL_ERRATUM_A007907
982 select SYS_FSL_ERRATUM_A008109
983 select SYS_FSL_ERRATUM_A009942
984 select SYS_FSL_ERRATUM_ESDHC111
985 select FSL_PCIE_RESET
986 select SYS_FSL_HAS_DDR3
987 select SYS_FSL_HAS_SEC
988 select SYS_FSL_QORIQ_CHASSIS2
989 select SYS_FSL_SEC_BE
990 select SYS_FSL_SEC_COMPAT_4
1003 select SYS_FSL_DDR_VER_47
1004 select SYS_FSL_ERRATUM_A006379
1005 select SYS_FSL_ERRATUM_A006593
1006 select SYS_FSL_ERRATUM_A007186
1007 select SYS_FSL_ERRATUM_A007212
1008 select SYS_FSL_ERRATUM_A009942
1009 select SYS_FSL_ERRATUM_ESDHC111
1010 select FSL_PCIE_RESET
1011 select SYS_FSL_HAS_DDR3
1012 select SYS_FSL_HAS_SEC
1013 select SYS_FSL_QORIQ_CHASSIS2
1014 select SYS_FSL_SEC_BE
1015 select SYS_FSL_SEC_COMPAT_4
1026 select SYS_FSL_DDR_VER_47
1027 select SYS_FSL_ERRATUM_A004468
1028 select SYS_FSL_ERRATUM_A005871
1029 select SYS_FSL_ERRATUM_A006379
1030 select SYS_FSL_ERRATUM_A006593
1031 select SYS_FSL_ERRATUM_A007186
1032 select SYS_FSL_ERRATUM_A007798
1033 select SYS_FSL_ERRATUM_A009942
1034 select SYS_FSL_HAS_DDR3
1035 select SYS_FSL_HAS_SEC
1036 select SYS_FSL_QORIQ_CHASSIS2
1037 select SYS_FSL_SEC_BE
1038 select SYS_FSL_SEC_COMPAT_4
1051 select SYS_FSL_DDR_VER_47
1052 select SYS_FSL_ERRATUM_A004468
1053 select SYS_FSL_ERRATUM_A005871
1054 select SYS_FSL_ERRATUM_A006261
1055 select SYS_FSL_ERRATUM_A006379
1056 select SYS_FSL_ERRATUM_A006593
1057 select SYS_FSL_ERRATUM_A007186
1058 select SYS_FSL_ERRATUM_A007798
1059 select SYS_FSL_ERRATUM_A007815
1060 select SYS_FSL_ERRATUM_A007907
1061 select SYS_FSL_ERRATUM_A008109
1062 select SYS_FSL_ERRATUM_A009942
1063 select SYS_FSL_HAS_DDR3
1064 select SYS_FSL_HAS_SEC
1065 select SYS_FSL_QORIQ_CHASSIS2
1066 select SYS_FSL_SEC_BE
1067 select SYS_FSL_SEC_COMPAT_4
1075 config MPC85XX_HAVE_RESET_VECTOR
1076 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
1087 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
1093 Enble PowerPC E500MC core
1098 Enable PowerPC E6500 core
1103 Use Freescale common code for Local Access Window
1108 Enable Freescale Secure Boot feature. Normally selected
1109 by defconfig. If unsure, do not change.
1112 int "Maximum number of CPUs permitted for MPC85xx"
1113 default 12 if ARCH_T4240
1114 default 8 if ARCH_P4080 || \
1116 default 4 if ARCH_B4860 || \
1124 default 2 if ARCH_B4420 || \
1139 Set this number to the maximum number of possible CPUs in the SoC.
1140 SoCs may have multiple clusters with each cluster may have multiple
1141 ports. If some ports are reserved but higher ports are used for
1142 cores, count the reserved ports. This will allocate enough memory
1143 in spin table to properly handle all cores.
1145 config SYS_CCSRBAR_DEFAULT
1146 hex "Default CCSRBAR address"
1147 default 0xff700000 if ARCH_BSC9131 || \
1168 default 0xff600000 if ARCH_P1023
1169 default 0xfe000000 if ARCH_B4420 || \
1184 default 0xe0000000 if ARCH_QEMU_E500
1186 Default value of CCSRBAR comes from power-on-reset. It
1187 is fixed on each SoC. Some SoCs can have different value
1188 if changed by pre-boot regime. The value here must match
1189 the current value in SoC. If not sure, do not change.
1191 config SYS_FSL_ERRATUM_A004468
1194 config SYS_FSL_ERRATUM_A004477
1197 config SYS_FSL_ERRATUM_A004508
1200 config SYS_FSL_ERRATUM_A004580
1203 config SYS_FSL_ERRATUM_A004699
1206 config SYS_FSL_ERRATUM_A004849
1209 config SYS_FSL_ERRATUM_A004510
1212 config SYS_FSL_ERRATUM_A004510_SVR_REV
1214 depends on SYS_FSL_ERRATUM_A004510
1215 default 0x20 if ARCH_P4080
1218 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1220 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1223 config SYS_FSL_ERRATUM_A005125
1226 config SYS_FSL_ERRATUM_A005434
1229 config SYS_FSL_ERRATUM_A005812
1232 config SYS_FSL_ERRATUM_A005871
1235 config SYS_FSL_ERRATUM_A005275
1238 config SYS_FSL_ERRATUM_A006261
1241 config SYS_FSL_ERRATUM_A006379
1244 config SYS_FSL_ERRATUM_A006384
1247 config SYS_FSL_ERRATUM_A006475
1250 config SYS_FSL_ERRATUM_A006593
1253 config SYS_FSL_ERRATUM_A007075
1256 config SYS_FSL_ERRATUM_A007186
1259 config SYS_FSL_ERRATUM_A007212
1262 config SYS_FSL_ERRATUM_A007815
1265 config SYS_FSL_ERRATUM_A007798
1268 config SYS_FSL_ERRATUM_A007907
1271 config SYS_FSL_ERRATUM_A008044
1274 config SYS_FSL_ERRATUM_CPC_A002
1277 config SYS_FSL_ERRATUM_CPC_A003
1280 config SYS_FSL_ERRATUM_CPU_A003999
1283 config SYS_FSL_ERRATUM_ELBC_A001
1286 config SYS_FSL_ERRATUM_I2C_A004447
1289 config SYS_FSL_A004447_SVR_REV
1291 depends on SYS_FSL_ERRATUM_I2C_A004447
1292 default 0x00 if ARCH_MPC8548
1293 default 0x10 if ARCH_P1010
1294 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1295 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
1297 config SYS_FSL_ERRATUM_IFC_A002769
1300 config SYS_FSL_ERRATUM_IFC_A003399
1303 config SYS_FSL_ERRATUM_NMG_CPU_A011
1306 config SYS_FSL_ERRATUM_NMG_ETSEC129
1309 config SYS_FSL_ERRATUM_NMG_LBC103
1312 config SYS_FSL_ERRATUM_P1010_A003549
1315 config SYS_FSL_ERRATUM_SATA_A001
1318 config SYS_FSL_ERRATUM_SEC_A003571
1321 config SYS_FSL_ERRATUM_SRIO_A004034
1324 config SYS_FSL_ERRATUM_USB14
1327 config SYS_P4080_ERRATUM_CPU22
1330 config SYS_P4080_ERRATUM_PCIE_A003
1333 config SYS_P4080_ERRATUM_SERDES8
1336 config SYS_P4080_ERRATUM_SERDES9
1339 config SYS_P4080_ERRATUM_SERDES_A001
1342 config SYS_P4080_ERRATUM_SERDES_A005
1345 config FSL_PCIE_DISABLE_ASPM
1348 config FSL_PCIE_RESET
1351 config SYS_FSL_QORIQ_CHASSIS1
1354 config SYS_FSL_QORIQ_CHASSIS2
1357 config SYS_FSL_NUM_LAWS
1358 int "Number of local access windows"
1360 default 32 if ARCH_B4420 || \
1371 default 16 if ARCH_T1023 || \
1375 default 12 if ARCH_BSC9131 || \
1389 default 10 if ARCH_MPC8544 || \
1393 default 8 if ARCH_MPC8540 || \
1398 Number of local access windows. This is fixed per SoC.
1399 If not sure, do not change.
1401 config SYS_FSL_THREADS_PER_CORE
1406 config SYS_NUM_TLBCAMS
1407 int "Number of TLB CAM entries"
1408 default 64 if E500MC
1411 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1412 16 for other E500 SoCs.
1417 config SYS_PPC_E500_USE_DEBUG_TLB
1426 config SYS_PPC_E500_DEBUG_TLB
1427 int "Temporary TLB entry for external debugger"
1428 depends on SYS_PPC_E500_USE_DEBUG_TLB
1429 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1430 default 1 if ARCH_MPC8536
1431 default 2 if ARCH_MPC8572 || \
1439 default 3 if ARCH_P1010 || \
1443 Select a temporary TLB entry to be used during boot to work
1444 around limitations in e500v1 and e500v2 external debugger
1445 support. This reduces the portions of the boot code where
1446 breakpoints and single stepping do not work. The value of this
1447 symbol should be set to the TLB1 entry to be used for this
1448 purpose. If unsure, do not change.
1450 config SYS_FSL_IFC_CLK_DIV
1451 int "Divider of platform clock"
1453 default 2 if ARCH_B4420 || \
1463 Defines divider of platform clock(clock input to
1466 config SYS_FSL_LBC_CLK_DIV
1467 int "Divider of platform clock"
1468 depends on FSL_ELBC || ARCH_MPC8540 || \
1469 ARCH_MPC8548 || ARCH_MPC8541 || \
1470 ARCH_MPC8555 || ARCH_MPC8560 || \
1473 default 2 if ARCH_P2041 || \
1481 Defines divider of platform clock(clock input to
1484 source "board/freescale/corenet_ds/Kconfig"
1485 source "board/freescale/mpc8541cds/Kconfig"
1486 source "board/freescale/mpc8544ds/Kconfig"
1487 source "board/freescale/mpc8548cds/Kconfig"
1488 source "board/freescale/mpc8555cds/Kconfig"
1489 source "board/freescale/mpc8568mds/Kconfig"
1490 source "board/freescale/mpc8569mds/Kconfig"
1491 source "board/freescale/mpc8572ds/Kconfig"
1492 source "board/freescale/p1010rdb/Kconfig"
1493 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1494 source "board/freescale/p2041rdb/Kconfig"
1495 source "board/freescale/qemu-ppce500/Kconfig"
1496 source "board/freescale/t102xrdb/Kconfig"
1497 source "board/freescale/t104xrdb/Kconfig"
1498 source "board/freescale/t208xqds/Kconfig"
1499 source "board/freescale/t208xrdb/Kconfig"
1500 source "board/freescale/t4rdb/Kconfig"
1501 source "board/gdsys/p1022/Kconfig"
1502 source "board/keymile/Kconfig"
1503 source "board/sbc8548/Kconfig"
1504 source "board/socrates/Kconfig"
1505 source "board/varisys/cyrus/Kconfig"
1506 source "board/xes/xpedite520x/Kconfig"
1507 source "board/xes/xpedite537x/Kconfig"
1508 source "board/xes/xpedite550x/Kconfig"
1509 source "board/Arcturus/ucp1020/Kconfig"