arch/powerpc/cpu/mpc85xx/Kconfig

   1 menu "mpc85xx CPU"
   2         depends on MPC85xx
   3
   4 config SYS_CPU
   5         default "mpc85xx"
   6
   7 choice
   8         prompt "Target select"
   9         optional
  10
  11 config TARGET_SBC8548
  12         bool "Support sbc8548"
  13         select ARCH_MPC8548
  14
  15 config TARGET_SOCRATES
  16         bool "Support socrates"
  17         select ARCH_MPC8544
  18
  19 config TARGET_B4420QDS
  20         bool "Support B4420QDS"
  21         select ARCH_B4420
  22         select SUPPORT_SPL
  23         select PHYS_64BIT
  24
  25 config TARGET_B4860QDS
  26         bool "Support B4860QDS"
  27         select ARCH_B4860
  28         select SUPPORT_SPL
  29         select PHYS_64BIT
  30
  31 config TARGET_BSC9131RDB
  32         bool "Support BSC9131RDB"
  33         select ARCH_BSC9131
  34         select SUPPORT_SPL
  35
  36 config TARGET_BSC9132QDS
  37         bool "Support BSC9132QDS"
  38         select ARCH_BSC9132
  39         select SUPPORT_SPL
  40
  41 config TARGET_C29XPCIE
  42         bool "Support C29XPCIE"
  43         select ARCH_C29X
  44         select SUPPORT_SPL
  45         select SUPPORT_TPL
  46         select PHYS_64BIT
  47
  48 config TARGET_P3041DS
  49         bool "Support P3041DS"
  50         select PHYS_64BIT
  51         select ARCH_P3041
  52
  53 config TARGET_P4080DS
  54         bool "Support P4080DS"
  55         select PHYS_64BIT
  56         select ARCH_P4080
  57
  58 config TARGET_P5020DS
  59         bool "Support P5020DS"
  60         select PHYS_64BIT
  61         select ARCH_P5020
  62
  63 config TARGET_P5040DS
  64         bool "Support P5040DS"
  65         select PHYS_64BIT
  66         select ARCH_P5040
  67
  68 config TARGET_MPC8536DS
  69         bool "Support MPC8536DS"
  70         select ARCH_MPC8536
  71 # Use DDR3 controller with DDR2 DIMMs on this board
  72         select SYS_FSL_DDRC_GEN3
  73
  74 config TARGET_MPC8540ADS
  75         bool "Support MPC8540ADS"
  76         select ARCH_MPC8540
  77
  78 config TARGET_MPC8541CDS
  79         bool "Support MPC8541CDS"
  80         select ARCH_MPC8541
  81
  82 config TARGET_MPC8544DS
  83         bool "Support MPC8544DS"
  84         select ARCH_MPC8544
  85
  86 config TARGET_MPC8548CDS
  87         bool "Support MPC8548CDS"
  88         select ARCH_MPC8548
  89
  90 config TARGET_MPC8555CDS
  91         bool "Support MPC8555CDS"
  92         select ARCH_MPC8555
  93
  94 config TARGET_MPC8560ADS
  95         bool "Support MPC8560ADS"
  96         select ARCH_MPC8560
  97
  98 config TARGET_MPC8568MDS
  99         bool "Support MPC8568MDS"
 100         select ARCH_MPC8568
 101
 102 config TARGET_MPC8569MDS
 103         bool "Support MPC8569MDS"
 104         select ARCH_MPC8569
 105
 106 config TARGET_MPC8572DS
 107         bool "Support MPC8572DS"
 108         select ARCH_MPC8572
 109 # Use DDR3 controller with DDR2 DIMMs on this board
 110         select SYS_FSL_DDRC_GEN3
 111
 112 config TARGET_P1010RDB_PA
 113         bool "Support P1010RDB_PA"
 114         select ARCH_P1010
 115         select SUPPORT_SPL
 116         select SUPPORT_TPL
 117
 118 config TARGET_P1010RDB_PB
 119         bool "Support P1010RDB_PB"
 120         select ARCH_P1010
 121         select SUPPORT_SPL
 122         select SUPPORT_TPL
 123
 124 config TARGET_P1022DS
 125         bool "Support P1022DS"
 126         select ARCH_P1022
 127         select SUPPORT_SPL
 128         select SUPPORT_TPL
 129
 130 config TARGET_P1023RDB
 131         bool "Support P1023RDB"
 132         select ARCH_P1023
 133
 134 config TARGET_P1020MBG
 135         bool "Support P1020MBG-PC"
 136         select SUPPORT_SPL
 137         select SUPPORT_TPL
 138         select ARCH_P1020
 139
 140 config TARGET_P1020RDB_PC
 141         bool "Support P1020RDB-PC"
 142         select SUPPORT_SPL
 143         select SUPPORT_TPL
 144         select ARCH_P1020
 145
 146 config TARGET_P1020RDB_PD
 147         bool "Support P1020RDB-PD"
 148         select SUPPORT_SPL
 149         select SUPPORT_TPL
 150         select ARCH_P1020
 151
 152 config TARGET_P1020UTM
 153         bool "Support P1020UTM"
 154         select SUPPORT_SPL
 155         select SUPPORT_TPL
 156         select ARCH_P1020
 157
 158 config TARGET_P1021RDB
 159         bool "Support P1021RDB"
 160         select SUPPORT_SPL
 161         select SUPPORT_TPL
 162         select ARCH_P1021
 163
 164 config TARGET_P1024RDB
 165         bool "Support P1024RDB"
 166         select SUPPORT_SPL
 167         select SUPPORT_TPL
 168         select ARCH_P1024
 169
 170 config TARGET_P1025RDB
 171         bool "Support P1025RDB"
 172         select SUPPORT_SPL
 173         select SUPPORT_TPL
 174         select ARCH_P1025
 175
 176 config TARGET_P2020RDB
 177         bool "Support P2020RDB-PC"
 178         select SUPPORT_SPL
 179         select SUPPORT_TPL
 180         select ARCH_P2020
 181
 182 config TARGET_P1_TWR
 183         bool "Support p1_twr"
 184         select ARCH_P1025
 185
 186 config TARGET_P2041RDB
 187         bool "Support P2041RDB"
 188         select ARCH_P2041
 189         select PHYS_64BIT
 190
 191 config TARGET_QEMU_PPCE500
 192         bool "Support qemu-ppce500"
 193         select ARCH_QEMU_E500
 194         select PHYS_64BIT
 195
 196 config TARGET_T1024QDS
 197         bool "Support T1024QDS"
 198         select ARCH_T1024
 199         select SUPPORT_SPL
 200         select PHYS_64BIT
 201
 202 config TARGET_T1023RDB
 203         bool "Support T1023RDB"
 204         select ARCH_T1023
 205         select SUPPORT_SPL
 206         select PHYS_64BIT
 207
 208 config TARGET_T1024RDB
 209         bool "Support T1024RDB"
 210         select ARCH_T1024
 211         select SUPPORT_SPL
 212         select PHYS_64BIT
 213
 214 config TARGET_T1040QDS
 215         bool "Support T1040QDS"
 216         select ARCH_T1040
 217         select PHYS_64BIT
 218
 219 config TARGET_T1040RDB
 220         bool "Support T1040RDB"
 221         select ARCH_T1040
 222         select SUPPORT_SPL
 223         select PHYS_64BIT
 224
 225 config TARGET_T1040D4RDB
 226         bool "Support T1040D4RDB"
 227         select ARCH_T1040
 228         select SUPPORT_SPL
 229         select PHYS_64BIT
 230
 231 config TARGET_T1042RDB
 232         bool "Support T1042RDB"
 233         select ARCH_T1042
 234         select SUPPORT_SPL
 235         select PHYS_64BIT
 236
 237 config TARGET_T1042D4RDB
 238         bool "Support T1042D4RDB"
 239         select ARCH_T1042
 240         select SUPPORT_SPL
 241         select PHYS_64BIT
 242
 243 config TARGET_T1042RDB_PI
 244         bool "Support T1042RDB_PI"
 245         select ARCH_T1042
 246         select SUPPORT_SPL
 247         select PHYS_64BIT
 248
 249 config TARGET_T2080QDS
 250         bool "Support T2080QDS"
 251         select ARCH_T2080
 252         select SUPPORT_SPL
 253         select PHYS_64BIT
 254
 255 config TARGET_T2080RDB
 256         bool "Support T2080RDB"
 257         select ARCH_T2080
 258         select SUPPORT_SPL
 259         select PHYS_64BIT
 260
 261 config TARGET_T2081QDS
 262         bool "Support T2081QDS"
 263         select ARCH_T2081
 264         select SUPPORT_SPL
 265         select PHYS_64BIT
 266
 267 config TARGET_T4160QDS
 268         bool "Support T4160QDS"
 269         select ARCH_T4160
 270         select SUPPORT_SPL
 271         select PHYS_64BIT
 272
 273 config TARGET_T4160RDB
 274         bool "Support T4160RDB"
 275         select ARCH_T4160
 276         select SUPPORT_SPL
 277         select PHYS_64BIT
 278
 279 config TARGET_T4240QDS
 280         bool "Support T4240QDS"
 281         select ARCH_T4240
 282         select SUPPORT_SPL
 283         select PHYS_64BIT
 284
 285 config TARGET_T4240RDB
 286         bool "Support T4240RDB"
 287         select ARCH_T4240
 288         select SUPPORT_SPL
 289         select PHYS_64BIT
 290
 291 config TARGET_CONTROLCENTERD
 292         bool "Support controlcenterd"
 293         select ARCH_P1022
 294
 295 config TARGET_KMP204X
 296         bool "Support kmp204x"
 297         select ARCH_P2041
 298         select PHYS_64BIT
 299
 300 config TARGET_XPEDITE520X
 301         bool "Support xpedite520x"
 302         select ARCH_MPC8548
 303
 304 config TARGET_XPEDITE537X
 305         bool "Support xpedite537x"
 306         select ARCH_MPC8572
 307 # Use DDR3 controller with DDR2 DIMMs on this board
 308         select SYS_FSL_DDRC_GEN3
 309
 310 config TARGET_XPEDITE550X
 311         bool "Support xpedite550x"
 312         select ARCH_P2020
 313
 314 config TARGET_UCP1020
 315         bool "Support uCP1020"
 316         select ARCH_P1020
 317
 318 config TARGET_CYRUS_P5020
 319         bool "Support Varisys Cyrus P5020"
 320         select ARCH_P5020
 321         select PHYS_64BIT
 322
 323 config TARGET_CYRUS_P5040
 324          bool "Support Varisys Cyrus P5040"
 325         select ARCH_P5040
 326         select PHYS_64BIT
 327
 328 endchoice
 329
 330 config ARCH_B4420
 331         bool
 332         select E500MC
 333         select FSL_LAW
 334         select SYS_FSL_HAS_DDR3
 335         select SYS_FSL_HAS_SEC
 336         select SYS_FSL_SEC_BE
 337         select SYS_FSL_SEC_COMPAT_4
 338
 339 config ARCH_B4860
 340         bool
 341         select E500MC
 342         select FSL_LAW
 343         select SYS_FSL_HAS_DDR3
 344         select SYS_FSL_HAS_SEC
 345         select SYS_FSL_SEC_BE
 346         select SYS_FSL_SEC_COMPAT_4
 347
 348 config ARCH_BSC9131
 349         bool
 350         select FSL_LAW
 351         select SYS_FSL_HAS_DDR3
 352         select SYS_FSL_HAS_SEC
 353         select SYS_FSL_SEC_BE
 354         select SYS_FSL_SEC_COMPAT_4
 355
 356 config ARCH_BSC9132
 357         bool
 358         select FSL_LAW
 359         select SYS_FSL_HAS_DDR3
 360         select SYS_FSL_HAS_SEC
 361         select SYS_FSL_SEC_BE
 362         select SYS_FSL_SEC_COMPAT_4
 363         select SYS_PPC_E500_USE_DEBUG_TLB
 364
 365 config ARCH_C29X
 366         bool
 367         select FSL_LAW
 368         select SYS_FSL_HAS_DDR3
 369         select SYS_FSL_HAS_SEC
 370         select SYS_FSL_SEC_BE
 371         select SYS_FSL_SEC_COMPAT_6
 372         select SYS_PPC_E500_USE_DEBUG_TLB
 373
 374 config ARCH_MPC8536
 375         bool
 376         select FSL_LAW
 377         select SYS_FSL_HAS_DDR2
 378         select SYS_FSL_HAS_DDR3
 379         select SYS_FSL_HAS_SEC
 380         select SYS_FSL_SEC_BE
 381         select SYS_FSL_SEC_COMPAT_2
 382         select SYS_PPC_E500_USE_DEBUG_TLB
 383
 384 config ARCH_MPC8540
 385         bool
 386         select FSL_LAW
 387         select SYS_FSL_HAS_DDR1
 388
 389 config ARCH_MPC8541
 390         bool
 391         select FSL_LAW
 392         select SYS_FSL_HAS_DDR1
 393         select SYS_FSL_HAS_SEC
 394         select SYS_FSL_SEC_BE
 395         select SYS_FSL_SEC_COMPAT_2
 396
 397 config ARCH_MPC8544
 398         bool
 399         select FSL_LAW
 400         select SYS_FSL_HAS_DDR2
 401         select SYS_FSL_HAS_SEC
 402         select SYS_FSL_SEC_BE
 403         select SYS_FSL_SEC_COMPAT_2
 404         select SYS_PPC_E500_USE_DEBUG_TLB
 405
 406 config ARCH_MPC8548
 407         bool
 408         select FSL_LAW
 409         select SYS_FSL_HAS_DDR2
 410         select SYS_FSL_HAS_DDR1
 411         select SYS_FSL_HAS_SEC
 412         select SYS_FSL_SEC_BE
 413         select SYS_FSL_SEC_COMPAT_2
 414         select SYS_PPC_E500_USE_DEBUG_TLB
 415
 416 config ARCH_MPC8555
 417         bool
 418         select FSL_LAW
 419         select SYS_FSL_HAS_DDR1
 420         select SYS_FSL_HAS_SEC
 421         select SYS_FSL_SEC_BE
 422         select SYS_FSL_SEC_COMPAT_2
 423
 424 config ARCH_MPC8560
 425         bool
 426         select FSL_LAW
 427         select SYS_FSL_HAS_DDR1
 428
 429 config ARCH_MPC8568
 430         bool
 431         select FSL_LAW
 432         select SYS_FSL_HAS_DDR2
 433         select SYS_FSL_HAS_SEC
 434         select SYS_FSL_SEC_BE
 435         select SYS_FSL_SEC_COMPAT_2
 436
 437 config ARCH_MPC8569
 438         bool
 439         select FSL_LAW
 440         select SYS_FSL_HAS_DDR3
 441         select SYS_FSL_HAS_SEC
 442         select SYS_FSL_SEC_BE
 443         select SYS_FSL_SEC_COMPAT_2
 444
 445 config ARCH_MPC8572
 446         bool
 447         select FSL_LAW
 448         select SYS_FSL_HAS_DDR2
 449         select SYS_FSL_HAS_DDR3
 450         select SYS_FSL_HAS_SEC
 451         select SYS_FSL_SEC_BE
 452         select SYS_FSL_SEC_COMPAT_2
 453         select SYS_PPC_E500_USE_DEBUG_TLB
 454
 455 config ARCH_P1010
 456         bool
 457         select FSL_LAW
 458         select SYS_FSL_HAS_DDR3
 459         select SYS_FSL_HAS_SEC
 460         select SYS_FSL_SEC_BE
 461         select SYS_FSL_SEC_COMPAT_4
 462         select SYS_PPC_E500_USE_DEBUG_TLB
 463
 464 config ARCH_P1011
 465         bool
 466         select FSL_LAW
 467         select SYS_FSL_HAS_DDR3
 468         select SYS_FSL_HAS_SEC
 469         select SYS_FSL_SEC_BE
 470         select SYS_FSL_SEC_COMPAT_2
 471         select SYS_PPC_E500_USE_DEBUG_TLB
 472
 473 config ARCH_P1020
 474         bool
 475         select FSL_LAW
 476         select SYS_FSL_HAS_DDR3
 477         select SYS_FSL_HAS_SEC
 478         select SYS_FSL_SEC_BE
 479         select SYS_FSL_SEC_COMPAT_2
 480         select SYS_PPC_E500_USE_DEBUG_TLB
 481
 482 config ARCH_P1021
 483         bool
 484         select FSL_LAW
 485         select SYS_FSL_HAS_DDR3
 486         select SYS_FSL_HAS_SEC
 487         select SYS_FSL_SEC_BE
 488         select SYS_FSL_SEC_COMPAT_2
 489         select SYS_PPC_E500_USE_DEBUG_TLB
 490
 491 config ARCH_P1022
 492         bool
 493         select FSL_LAW
 494         select SYS_FSL_HAS_DDR3
 495         select SYS_FSL_HAS_SEC
 496         select SYS_FSL_SEC_BE
 497         select SYS_FSL_SEC_COMPAT_2
 498         select SYS_PPC_E500_USE_DEBUG_TLB
 499
 500 config ARCH_P1023
 501         bool
 502         select FSL_LAW
 503         select SYS_FSL_HAS_DDR3
 504         select SYS_FSL_HAS_SEC
 505         select SYS_FSL_SEC_BE
 506         select SYS_FSL_SEC_COMPAT_4
 507
 508 config ARCH_P1024
 509         bool
 510         select FSL_LAW
 511         select SYS_FSL_HAS_DDR3
 512         select SYS_FSL_HAS_SEC
 513         select SYS_FSL_SEC_BE
 514         select SYS_FSL_SEC_COMPAT_2
 515         select SYS_PPC_E500_USE_DEBUG_TLB
 516
 517 config ARCH_P1025
 518         bool
 519         select FSL_LAW
 520         select SYS_FSL_HAS_DDR3
 521         select SYS_FSL_HAS_SEC
 522         select SYS_FSL_SEC_BE
 523         select SYS_FSL_SEC_COMPAT_2
 524         select SYS_PPC_E500_USE_DEBUG_TLB
 525
 526 config ARCH_P2020
 527         bool
 528         select FSL_LAW
 529         select SYS_FSL_HAS_DDR3
 530         select SYS_FSL_HAS_SEC
 531         select SYS_FSL_SEC_BE
 532         select SYS_FSL_SEC_COMPAT_2
 533         select SYS_PPC_E500_USE_DEBUG_TLB
 534
 535 config ARCH_P2041
 536         bool
 537         select E500MC
 538         select FSL_LAW
 539         select SYS_FSL_HAS_DDR3
 540         select SYS_FSL_HAS_SEC
 541         select SYS_FSL_SEC_BE
 542         select SYS_FSL_SEC_COMPAT_4
 543
 544 config ARCH_P3041
 545         bool
 546         select E500MC
 547         select FSL_LAW
 548         select SYS_FSL_HAS_DDR3
 549         select SYS_FSL_HAS_SEC
 550         select SYS_FSL_SEC_BE
 551         select SYS_FSL_SEC_COMPAT_4
 552
 553 config ARCH_P4080
 554         bool
 555         select E500MC
 556         select FSL_LAW
 557         select SYS_FSL_HAS_DDR3
 558         select SYS_FSL_HAS_SEC
 559         select SYS_FSL_SEC_BE
 560         select SYS_FSL_SEC_COMPAT_4
 561
 562 config ARCH_P5020
 563         bool
 564         select E500MC
 565         select FSL_LAW
 566         select SYS_FSL_HAS_DDR3
 567         select SYS_FSL_HAS_SEC
 568         select SYS_FSL_SEC_BE
 569         select SYS_FSL_SEC_COMPAT_4
 570
 571 config ARCH_P5040
 572         bool
 573         select E500MC
 574         select FSL_LAW
 575         select SYS_FSL_HAS_DDR3
 576         select SYS_FSL_HAS_SEC
 577         select SYS_FSL_SEC_BE
 578         select SYS_FSL_SEC_COMPAT_4
 579
 580 config ARCH_QEMU_E500
 581         bool
 582
 583 config ARCH_T1023
 584         bool
 585         select E500MC
 586         select FSL_LAW
 587         select SYS_FSL_HAS_DDR3
 588         select SYS_FSL_HAS_DDR4
 589         select SYS_FSL_HAS_SEC
 590         select SYS_FSL_SEC_BE
 591         select SYS_FSL_SEC_COMPAT_5
 592
 593 config ARCH_T1024
 594         bool
 595         select E500MC
 596         select FSL_LAW
 597         select SYS_FSL_HAS_DDR3
 598         select SYS_FSL_HAS_DDR4
 599         select SYS_FSL_HAS_SEC
 600         select SYS_FSL_SEC_BE
 601         select SYS_FSL_SEC_COMPAT_5
 602
 603 config ARCH_T1040
 604         bool
 605         select E500MC
 606         select FSL_LAW
 607         select SYS_FSL_HAS_DDR3
 608         select SYS_FSL_HAS_DDR4
 609         select SYS_FSL_HAS_SEC
 610         select SYS_FSL_SEC_BE
 611         select SYS_FSL_SEC_COMPAT_5
 612
 613 config ARCH_T1042
 614         bool
 615         select E500MC
 616         select FSL_LAW
 617         select SYS_FSL_HAS_DDR3
 618         select SYS_FSL_HAS_DDR4
 619         select SYS_FSL_HAS_SEC
 620         select SYS_FSL_SEC_BE
 621         select SYS_FSL_SEC_COMPAT_5
 622
 623 config ARCH_T2080
 624         bool
 625         select E500MC
 626         select FSL_LAW
 627         select SYS_FSL_HAS_DDR3
 628         select SYS_FSL_HAS_SEC
 629         select SYS_FSL_SEC_BE
 630         select SYS_FSL_SEC_COMPAT_4
 631
 632 config ARCH_T2081
 633         bool
 634         select E500MC
 635         select FSL_LAW
 636         select SYS_FSL_HAS_DDR3
 637         select SYS_FSL_HAS_SEC
 638         select SYS_FSL_SEC_BE
 639         select SYS_FSL_SEC_COMPAT_4
 640
 641 config ARCH_T4160
 642         bool
 643         select E500MC
 644         select FSL_LAW
 645         select SYS_FSL_HAS_DDR3
 646         select SYS_FSL_HAS_SEC
 647         select SYS_FSL_SEC_BE
 648         select SYS_FSL_SEC_COMPAT_4
 649
 650 config ARCH_T4240
 651         bool
 652         select E500MC
 653         select FSL_LAW
 654         select SYS_FSL_HAS_DDR3
 655         select SYS_FSL_HAS_SEC
 656         select SYS_FSL_SEC_BE
 657         select SYS_FSL_SEC_COMPAT_4
 658
 659 config BOOKE
 660         bool
 661         default y
 662
 663 config E500
 664         bool
 665         default y
 666         help
 667                 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
 668
 669 config E500MC
 670         bool
 671         help
 672                 Enble PowerPC E500MC core
 673
 674 config FSL_LAW
 675         bool
 676         help
 677                 Use Freescale common code for Local Access Window
 678
 679 config SECURE_BOOT
 680         bool    "Secure Boot"
 681         help
 682                 Enable Freescale Secure Boot feature. Normally selected
 683                 by defconfig. If unsure, do not change.
 684
 685 config MAX_CPUS
 686         int "Maximum number of CPUs permitted for MPC85xx"
 687         default 12 if ARCH_T4240
 688         default 8 if ARCH_P4080 || \
 689                      ARCH_T4160
 690         default 4 if ARCH_B4860 || \
 691                      ARCH_P2041 || \
 692                      ARCH_P3041 || \
 693                      ARCH_P5040 || \
 694                      ARCH_T1040 || \
 695                      ARCH_T1042 || \
 696                      ARCH_T2080 || \
 697                      ARCH_T2081
 698         default 2 if ARCH_B4420 || \
 699                      ARCH_BSC9132 || \
 700                      ARCH_MPC8572 || \
 701                      ARCH_P1020 || \
 702                      ARCH_P1021 || \
 703                      ARCH_P1022 || \
 704                      ARCH_P1023 || \
 705                      ARCH_P1024 || \
 706                      ARCH_P1025 || \
 707                      ARCH_P2020 || \
 708                      ARCH_P5020 || \
 709                      ARCH_T1023 || \
 710                      ARCH_T1024
 711         default 1
 712         help
 713           Set this number to the maximum number of possible CPUs in the SoC.
 714           SoCs may have multiple clusters with each cluster may have multiple
 715           ports. If some ports are reserved but higher ports are used for
 716           cores, count the reserved ports. This will allocate enough memory
 717           in spin table to properly handle all cores.
 718
 719 config SYS_CCSRBAR_DEFAULT
 720         hex "Default CCSRBAR address"
 721         default 0xff700000 if   ARCH_BSC9131    || \
 722                                 ARCH_BSC9132    || \
 723                                 ARCH_C29X       || \
 724                                 ARCH_MPC8536    || \
 725                                 ARCH_MPC8540    || \
 726                                 ARCH_MPC8541    || \
 727                                 ARCH_MPC8544    || \
 728                                 ARCH_MPC8548    || \
 729                                 ARCH_MPC8555    || \
 730                                 ARCH_MPC8560    || \
 731                                 ARCH_MPC8568    || \
 732                                 ARCH_MPC8569    || \
 733                                 ARCH_MPC8572    || \
 734                                 ARCH_P1010      || \
 735                                 ARCH_P1011      || \
 736                                 ARCH_P1020      || \
 737                                 ARCH_P1021      || \
 738                                 ARCH_P1022      || \
 739                                 ARCH_P1024      || \
 740                                 ARCH_P1025      || \
 741                                 ARCH_P2020
 742         default 0xff600000 if   ARCH_P1023
 743         default 0xfe000000 if   ARCH_B4420      || \
 744                                 ARCH_B4860      || \
 745                                 ARCH_P2041      || \
 746                                 ARCH_P3041      || \
 747                                 ARCH_P4080      || \
 748                                 ARCH_P5020      || \
 749                                 ARCH_P5040      || \
 750                                 ARCH_T1023      || \
 751                                 ARCH_T1024      || \
 752                                 ARCH_T1040      || \
 753                                 ARCH_T1042      || \
 754                                 ARCH_T2080      || \
 755                                 ARCH_T2081      || \
 756                                 ARCH_T4160      || \
 757                                 ARCH_T4240
 758         default 0xe0000000 if ARCH_QEMU_E500
 759         help
 760                 Default value of CCSRBAR comes from power-on-reset. It
 761                 is fixed on each SoC. Some SoCs can have different value
 762                 if changed by pre-boot regime. The value here must match
 763                 the current value in SoC. If not sure, do not change.
 764
 765 config SYS_FSL_NUM_LAWS
 766         int "Number of local access windows"
 767         depends on FSL_LAW
 768         default 32 if   ARCH_B4420      || \
 769                         ARCH_B4860      || \
 770                         ARCH_P2041      || \
 771                         ARCH_P3041      || \
 772                         ARCH_P4080      || \
 773                         ARCH_P5020      || \
 774                         ARCH_P5040      || \
 775                         ARCH_T2080      || \
 776                         ARCH_T2081      || \
 777                         ARCH_T4160      || \
 778                         ARCH_T4240
 779         default 16 if   ARCH_T1023      || \
 780                         ARCH_T1024      || \
 781                         ARCH_T1040      || \
 782                         ARCH_T1042
 783         default 12 if   ARCH_BSC9131    || \
 784                         ARCH_BSC9132    || \
 785                         ARCH_C29X       || \
 786                         ARCH_MPC8536    || \
 787                         ARCH_MPC8572    || \
 788                         ARCH_P1010      || \
 789                         ARCH_P1011      || \
 790                         ARCH_P1020      || \
 791                         ARCH_P1021      || \
 792                         ARCH_P1022      || \
 793                         ARCH_P1023      || \
 794                         ARCH_P1024      || \
 795                         ARCH_P1025      || \
 796                         ARCH_P2020
 797         default 10 if   ARCH_MPC8544    || \
 798                         ARCH_MPC8548    || \
 799                         ARCH_MPC8568    || \
 800                         ARCH_MPC8569
 801         default 8 if    ARCH_MPC8540    || \
 802                         ARCH_MPC8541    || \
 803                         ARCH_MPC8555    || \
 804                         ARCH_MPC8560
 805         help
 806                 Number of local access windows. This is fixed per SoC.
 807                 If not sure, do not change.
 808
 809 config SYS_NUM_TLBCAMS
 810         int "Number of TLB CAM entries"
 811         default 64 if E500MC
 812         default 16
 813         help
 814                 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
 815                 16 for other E500 SoCs.
 816
 817 config SYS_PPC_E500_USE_DEBUG_TLB
 818         bool
 819
 820 config SYS_PPC_E500_DEBUG_TLB
 821         int "Temporary TLB entry for external debugger"
 822         depends on SYS_PPC_E500_USE_DEBUG_TLB
 823         default 0 if    ARCH_MPC8544 || ARCH_MPC8548
 824         default 1 if    ARCH_MPC8536
 825         default 2 if    ARCH_MPC8572    || \
 826                         ARCH_P1011      || \
 827                         ARCH_P1020      || \
 828                         ARCH_P1021      || \
 829                         ARCH_P1022      || \
 830                         ARCH_P1024      || \
 831                         ARCH_P1025      || \
 832                         ARCH_P2020
 833         default 3 if    ARCH_P1010      || \
 834                         ARCH_BSC9132    || \
 835                         ARCH_C29X
 836         help
 837                 Select a temporary TLB entry to be used during boot to work
 838                 around limitations in e500v1 and e500v2 external debugger
 839                 support. This reduces the portions of the boot code where
 840                 breakpoints and single stepping do not work. The value of this
 841                 symbol should be set to the TLB1 entry to be used for this
 842                 purpose. If unsure, do not change.
 843
 844 source "board/freescale/b4860qds/Kconfig"
 845 source "board/freescale/bsc9131rdb/Kconfig"
 846 source "board/freescale/bsc9132qds/Kconfig"
 847 source "board/freescale/c29xpcie/Kconfig"
 848 source "board/freescale/corenet_ds/Kconfig"
 849 source "board/freescale/mpc8536ds/Kconfig"
 850 source "board/freescale/mpc8540ads/Kconfig"
 851 source "board/freescale/mpc8541cds/Kconfig"
 852 source "board/freescale/mpc8544ds/Kconfig"
 853 source "board/freescale/mpc8548cds/Kconfig"
 854 source "board/freescale/mpc8555cds/Kconfig"
 855 source "board/freescale/mpc8560ads/Kconfig"
 856 source "board/freescale/mpc8568mds/Kconfig"
 857 source "board/freescale/mpc8569mds/Kconfig"
 858 source "board/freescale/mpc8572ds/Kconfig"
 859 source "board/freescale/p1010rdb/Kconfig"
 860 source "board/freescale/p1022ds/Kconfig"
 861 source "board/freescale/p1023rdb/Kconfig"
 862 source "board/freescale/p1_p2_rdb_pc/Kconfig"
 863 source "board/freescale/p1_twr/Kconfig"
 864 source "board/freescale/p2041rdb/Kconfig"
 865 source "board/freescale/qemu-ppce500/Kconfig"
 866 source "board/freescale/t102xqds/Kconfig"
 867 source "board/freescale/t102xrdb/Kconfig"
 868 source "board/freescale/t1040qds/Kconfig"
 869 source "board/freescale/t104xrdb/Kconfig"
 870 source "board/freescale/t208xqds/Kconfig"
 871 source "board/freescale/t208xrdb/Kconfig"
 872 source "board/freescale/t4qds/Kconfig"
 873 source "board/freescale/t4rdb/Kconfig"
 874 source "board/gdsys/p1022/Kconfig"
 875 source "board/keymile/kmp204x/Kconfig"
 876 source "board/sbc8548/Kconfig"
 877 source "board/socrates/Kconfig"
 878 source "board/varisys/cyrus/Kconfig"
 879 source "board/xes/xpedite520x/Kconfig"
 880 source "board/xes/xpedite537x/Kconfig"
 881 source "board/xes/xpedite550x/Kconfig"
 882 source "board/Arcturus/ucp1020/Kconfig"
 883
 884 endmenu